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6#ifndef _DV_AINTC_DEFS_H_
7#define _DV_AINTC_DEFS_H_
8
9struct dv_aintc_regs {
10 unsigned int fiq0;
11 unsigned int fiq1;
12 unsigned int irq0;
13 unsigned int irq1;
14 unsigned int fiqentry;
15 unsigned int irqentry;
16 unsigned int eint0;
17 unsigned int eint1;
18 unsigned int intctl;
19 unsigned int eabase;
20 unsigned char rsvd0[8];
21 unsigned int intpri0;
22 unsigned int intpri1;
23 unsigned int intpri2;
24 unsigned int intpri3;
25 unsigned int intpri4;
26 unsigned int intpri5;
27 unsigned int intpri6;
28 unsigned int intpri7;
29};
30
31#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
32
33#define DV_AINTC_INTCTL_IDMODE (1 << 2)
34
35#endif
36