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6#ifndef _DV_PLL_DEFS_H_
7#define _DV_PLL_DEFS_H_
8
9struct dv_pll_regs {
10 unsigned int pid;
11 unsigned char rsvd0[224];
12 unsigned int rstype;
13 unsigned char rsvd1[24];
14 unsigned int pllctl;
15 unsigned char rsvd2[4];
16 unsigned int secctl;
17 unsigned int rv;
18 unsigned int pllm;
19 unsigned int prediv;
20 unsigned int plldiv1;
21 unsigned int plldiv2;
22 unsigned int plldiv3;
23 unsigned int oscdiv1;
24 unsigned int postdiv;
25 unsigned int bpdiv;
26 unsigned char rsvd5[8];
27 unsigned int pllcmd;
28 unsigned int pllstat;
29 unsigned int alnctl;
30 unsigned int dchange;
31 unsigned int cken;
32 unsigned int ckstat;
33 unsigned int systat;
34 unsigned char rsvd6[12];
35 unsigned int plldiv4;
36 unsigned int plldiv5;
37 unsigned int plldiv6;
38 unsigned int plldiv7;
39 unsigned int plldiv8;
40 unsigned int plldiv9;
41};
42
43#define PLL_MASTER_LOCK (1 << 4)
44
45#define PLLCTL_CLOCK_MODE_SHIFT 8
46#define PLLCTL_PLLEN (1 << 0)
47#define PLLCTL_PLLPWRDN (1 << 1)
48#define PLLCTL_PLLRST (1 << 3)
49#define PLLCTL_PLLDIS (1 << 4)
50#define PLLCTL_PLLENSRC (1 << 5)
51#define PLLCTL_RES_9 (1 << 8)
52#define PLLCTL_EXTCLKSRC (1 << 9)
53
54#define PLL_DIVEN (1 << 15)
55#define PLL_POSTDEN PLL_DIVEN
56
57#define PLL_SCSCFG3_DIV45PENA (1 << 2)
58#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
59
60#define PLL_RSTYPE_POR (1 << 0)
61#define PLL_RSTYPE_XWRST (1 << 1)
62
63#define PLLSECCTL_TINITZ (1 << 16)
64#define PLLSECCTL_TENABLE (1 << 17)
65#define PLLSECCTL_TENABLEDIV (1 << 18)
66#define PLLSECCTL_STOPMODE (1 << 22)
67
68#define PLLCMD_GOSET (1 << 0)
69#define PLLCMD_GOSTAT (1 << 0)
70
71#define PLL0_LOCK 0x07000000
72#define PLL1_LOCK 0x07000000
73
74#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
75#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
76
77#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
78#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
79#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
80
81unsigned int davinci_clk_get(unsigned int div);
82#endif
83