LXR uboot/arch/arm/mach-keystone/init.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Keystone2: Architecture initialization
   4 *
   5 * (C) Copyright 2012-2014
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 */
   8
   9#include <common.h>
  10#include <cpu_func.h>
  11#include <init.h>
  12#include <ns16550.h>
  13#include <asm/cache.h>
  14#include <asm/io.h>
  15#include <asm/arch/msmc.h>
  16#include <asm/arch/clock.h>
  17#include <asm/arch/hardware.h>
  18#include <asm/arch/psc_defs.h>
  19#include <linux/bitops.h>
  20
  21#define MAX_PCI_PORTS           2
  22enum pci_mode   {
  23        ENDPOINT,
  24        LEGACY_ENDPOINT,
  25        ROOTCOMPLEX,
  26};
  27
  28#define DEVCFG_MODE_MASK                (BIT(2) | BIT(1))
  29#define DEVCFG_MODE_SHIFT               1
  30
  31void chip_configuration_unlock(void)
  32{
  33        __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  34        __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  35}
  36
  37#ifdef CONFIG_SOC_K2L
  38void osr_init(void)
  39{
  40        u32 i;
  41        u32 j;
  42        u32 val;
  43        u32 base = KS2_OSR_CFG_BASE;
  44        u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  45
  46        /* Enable the OSR clock domain */
  47        psc_enable_module(KS2_LPSC_OSR);
  48
  49        /* Disable OSR ECC check for all the ram banks */
  50        for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  51                val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  52                        (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  53
  54                writel(val , base + KS2_OSR_ECC_VEC);
  55
  56                /**
  57                 * wait till read is done.
  58                 * Print should be added after earlyprintk support is added.
  59                 */
  60                for (j = 0; j < 10000; j++) {
  61                        val = readl(base + KS2_OSR_ECC_VEC);
  62                        if (val & KS2_OSR_ECC_VEC_RD_DONE)
  63                                break;
  64                }
  65
  66                ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  67                                                KS2_OSR_ECC_CTRL_CHK;
  68
  69                writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  70                writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  71        }
  72
  73        /* Reset OSR memory to all zeros */
  74        for (i = 0; i < KS2_OSR_SIZE; i += 4)
  75                writel(0, KS2_OSR_DATA_BASE + i);
  76
  77        /* Enable OSR ECC check for all the ram banks */
  78        for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  79                writel(ecc_ctrl[i] |
  80                       KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  81}
  82#endif
  83
  84/* Function to set up PCIe mode */
  85static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
  86{
  87        u32 val = __raw_readl(KS2_DEVCFG);
  88
  89        if (pcie_port >= MAX_PCI_PORTS)
  90                return;
  91
  92        /**
  93         * each pci port has two bits for mode and it starts at
  94         * bit 1. So use port number to get the right bit position.
  95         */
  96        pcie_port <<= 1;
  97        val &= ~(DEVCFG_MODE_MASK << pcie_port);
  98        val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  99        __raw_writel(val, KS2_DEVCFG);
 100}
 101
 102static void msmc_k2hkle_common_setup(void)
 103{
 104        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 105        msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 106        msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
 107        msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
 108        msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
 109        msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 110}
 111
 112static void msmc_k2hk_setup(void)
 113{
 114        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 115        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 116        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 117        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
 118        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
 119        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
 120        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
 121        msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 122}
 123
 124static inline void msmc_k2l_setup(void)
 125{
 126        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 127        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 128        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 129        msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
 130}
 131
 132static inline void msmc_k2e_setup(void)
 133{
 134        msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
 135        msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 136        msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
 137}
 138
 139static void msmc_k2g_setup(void)
 140{
 141        msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 142        msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
 143        msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
 144        msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
 145        msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
 146        msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
 147        msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
 148        msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
 149        msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
 150        msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
 151        msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
 152        msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 153}
 154
 155int arch_cpu_init(void)
 156{
 157        chip_configuration_unlock();
 158        icache_enable();
 159
 160        if (cpu_is_k2g()) {
 161                msmc_k2g_setup();
 162        } else {
 163                msmc_k2hkle_common_setup();
 164                if (cpu_is_k2e())
 165                        msmc_k2e_setup();
 166                else if (cpu_is_k2l())
 167                        msmc_k2l_setup();
 168                else
 169                        msmc_k2hk_setup();
 170        }
 171
 172        /* Initialize the PCIe-0 to work as Root Complex */
 173        config_pcie_mode(0, ROOTCOMPLEX);
 174#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 175        /* Initialize the PCIe-1 to work as Root Complex */
 176        config_pcie_mode(1, ROOTCOMPLEX);
 177#endif
 178#ifdef CONFIG_SOC_K2L
 179        osr_init();
 180#endif
 181
 182        /*
 183         * just initialise the COM2 port so that TI specific
 184         * UART register PWREMU_MGMT is initialized. Linux UART
 185         * driver doesn't handle this.
 186         */
 187#ifndef CONFIG_DM_SERIAL
 188        ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2),
 189                     CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 190#endif
 191
 192        return 0;
 193}
 194
 195void reset_cpu(void)
 196{
 197        volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
 198        u32 tmp;
 199
 200        tmp = *rstctrl & KS2_RSTCTRL_MASK;
 201        *rstctrl = tmp | KS2_RSTCTRL_KEY;
 202
 203        *rstctrl &= KS2_RSTCTRL_SWRST;
 204
 205        for (;;)
 206                ;
 207}
 208
 209void enable_caches(void)
 210{
 211#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 212        /* Enable D-cache. I-cache is already enabled in start.S */
 213        dcache_enable();
 214#endif
 215}
 216
 217#if defined(CONFIG_DISPLAY_CPUINFO)
 218int print_cpuinfo(void)
 219{
 220        u16 cpu = get_part_number();
 221        u8 rev = cpu_revision();
 222
 223        puts("CPU: ");
 224        switch (cpu) {
 225        case CPU_66AK2Hx:
 226                puts("66AK2Hx SR");
 227                break;
 228        case CPU_66AK2Lx:
 229                puts("66AK2Lx SR");
 230                break;
 231        case CPU_66AK2Ex:
 232                puts("66AK2Ex SR");
 233                break;
 234        case CPU_66AK2Gx:
 235                puts("66AK2Gx");
 236#ifdef CONFIG_SOC_K2G
 237                {
 238                        int speed = get_max_arm_speed(speeds);
 239                        if (speed == SPD1000)
 240                                puts("-100 ");
 241                        else if (speed == SPD600)
 242                                puts("-60 ");
 243                        else
 244                                puts("-xx ");
 245                }
 246#endif
 247                puts("SR");
 248                break;
 249        default:
 250                puts("Unknown\n");
 251        }
 252
 253        if (rev == 2)
 254                puts("2.0\n");
 255        else if (rev == 1)
 256                puts("1.1\n");
 257        else if (rev == 0)
 258                puts("1.0\n");
 259        else if (rev == 8)
 260                puts("1.0\n");
 261        return 0;
 262}
 263#endif
 264