1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon dpi. 7 */ 8 9#ifndef __CVMX_DPI_DEFS_H__ 10#define __CVMX_DPI_DEFS_H__ 11 12#define CVMX_DPI_BIST_STATUS (0x0001DF0000000000ull) 13#define CVMX_DPI_CTL (0x0001DF0000000040ull) 14#define CVMX_DPI_DMAX_COUNTS(offset) (0x0001DF0000000300ull + ((offset) & 7) * 8) 15#define CVMX_DPI_DMAX_DBELL(offset) (0x0001DF0000000200ull + ((offset) & 7) * 8) 16#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (0x0001DF0000000A80ull + ((offset) & 7) * 8) 17#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (0x0001DF0000000280ull + ((offset) & 7) * 8) 18#define CVMX_DPI_DMAX_IFLIGHT(offset) (0x0001DF0000000A00ull + ((offset) & 7) * 8) 19#define CVMX_DPI_DMAX_NADDR(offset) (0x0001DF0000000380ull + ((offset) & 7) * 8) 20#define CVMX_DPI_DMAX_REQBNK0(offset) (0x0001DF0000000400ull + ((offset) & 7) * 8) 21#define CVMX_DPI_DMAX_REQBNK1(offset) (0x0001DF0000000480ull + ((offset) & 7) * 8) 22#define CVMX_DPI_DMAX_REQQ_CTL(offset) (0x0001DF0000000180ull + ((offset) & 7) * 8) 23#define CVMX_DPI_DMA_CONTROL (0x0001DF0000000048ull) 24#define CVMX_DPI_DMA_ENGX_EN(offset) (0x0001DF0000000080ull + ((offset) & 7) * 8) 25static inline u64 CVMX_DPI_DMA_PPX_CNT(unsigned long offset) 26{ 27 switch (cvmx_get_octeon_family()) { 28 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 29 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 30 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 31 return 0x0001DF0000000B00ull + (offset) * 8; 32 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 33 return 0x0001DF0000000B00ull + (offset) * 8; 34 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 35 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 36 return 0x0001DF0000000C00ull + (offset) * 8; 37 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 38 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 39 return 0x0001DF0000000C00ull + (offset) * 8; 40 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 41 return 0x0001DF0000000C00ull + (offset) * 8; 42 } 43 return 0x0001DF0000000C00ull + (offset) * 8; 44} 45 46#define CVMX_DPI_DMA_PP_INT (0x0001DF0000000038ull) 47#define CVMX_DPI_ECC_CTL (0x0001DF0000000018ull) 48#define CVMX_DPI_ECC_INT (0x0001DF0000000020ull) 49#define CVMX_DPI_ENGX_BUF(offset) (0x0001DF0000000880ull + ((offset) & 7) * 8) 50#define CVMX_DPI_INFO_REG (0x0001DF0000000980ull) 51#define CVMX_DPI_INT_EN (0x0001DF0000000010ull) 52#define CVMX_DPI_INT_REG (0x0001DF0000000008ull) 53#define CVMX_DPI_NCBX_CFG(offset) (0x0001DF0000000800ull) 54#define CVMX_DPI_NCB_CTL (0x0001DF0000000028ull) 55#define CVMX_DPI_PINT_INFO (0x0001DF0000000830ull) 56#define CVMX_DPI_PKT_ERR_RSP (0x0001DF0000000078ull) 57#define CVMX_DPI_REQ_ERR_RSP (0x0001DF0000000058ull) 58#define CVMX_DPI_REQ_ERR_RSP_EN (0x0001DF0000000068ull) 59#define CVMX_DPI_REQ_ERR_RST (0x0001DF0000000060ull) 60#define CVMX_DPI_REQ_ERR_RST_EN (0x0001DF0000000070ull) 61#define CVMX_DPI_REQ_ERR_SKIP_COMP (0x0001DF0000000838ull) 62#define CVMX_DPI_REQ_GBL_EN (0x0001DF0000000050ull) 63#define CVMX_DPI_SLI_PRTX_CFG(offset) (0x0001DF0000000900ull + ((offset) & 3) * 8) 64static inline u64 CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) 65{ 66 switch (cvmx_get_octeon_family()) { 67 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 68 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 69 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 70 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 71 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 72 return 0x0001DF0000000920ull + (offset) * 8; 73 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 74 return 0x0001DF0000000920ull + (offset) * 8; 75 return 0x0001DF0000000920ull + (offset) * 8; 76 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 77 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 78 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 79 80 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) 81 return 0x0001DF0000000928ull + (offset) * 8; 82 83 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) 84 return 0x0001DF0000000920ull + (offset) * 8; 85 return 0x0001DF0000000920ull + (offset) * 8; 86 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 87 return 0x0001DF0000000920ull + (offset) * 8; 88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 89 return 0x0001DF0000000928ull + (offset) * 8; 90 } 91 return 0x0001DF0000000920ull + (offset) * 8; 92} 93 94#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (0x0001DF0000000940ull + ((offset) & 3) * 8) 95#define CVMX_DPI_SRIO_RX_BELLX(offset) (0x0001DF0000080200ull + ((offset) & 31) * 8) 96#define CVMX_DPI_SRIO_RX_BELL_SEQX(offset) (0x0001DF0000080400ull + ((offset) & 31) * 8) 97#define CVMX_DPI_SWA_Q_VMID (0x0001DF0000000030ull) 98 99/** 100 * cvmx_dpi_bist_status 101 * 102 * This is the built-in self-test (BIST) status register. Each bit is the BIST result of an 103 * individual memory (per bit, 0 = pass and 1 = fail). 104 */ 105union cvmx_dpi_bist_status { 106 u64 u64; 107 struct cvmx_dpi_bist_status_s { 108 u64 reserved_57_63 : 7; 109 u64 bist : 57; 110 } s; 111 struct cvmx_dpi_bist_status_cn61xx { 112 u64 reserved_47_63 : 17; 113 u64 bist : 47; 114 } cn61xx; 115 struct cvmx_dpi_bist_status_cn63xx { 116 u64 reserved_45_63 : 19; 117 u64 bist : 45; 118 } cn63xx; 119 struct cvmx_dpi_bist_status_cn63xxp1 { 120 u64 reserved_37_63 : 27; 121 u64 bist : 37; 122 } cn63xxp1; 123 struct cvmx_dpi_bist_status_cn61xx cn66xx; 124 struct cvmx_dpi_bist_status_cn63xx cn68xx; 125 struct cvmx_dpi_bist_status_cn63xx cn68xxp1; 126 struct cvmx_dpi_bist_status_cn61xx cn70xx; 127 struct cvmx_dpi_bist_status_cn61xx cn70xxp1; 128 struct cvmx_dpi_bist_status_s cn73xx; 129 struct cvmx_dpi_bist_status_s cn78xx; 130 struct cvmx_dpi_bist_status_cn78xxp1 { 131 u64 reserved_51_63 : 13; 132 u64 bist : 51; 133 } cn78xxp1; 134 struct cvmx_dpi_bist_status_cn61xx cnf71xx; 135 struct cvmx_dpi_bist_status_s cnf75xx; 136}; 137 138typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t; 139 140/** 141 * cvmx_dpi_ctl 142 * 143 * This register provides the enable bit for the DMA and packet state machines. 144 * 145 */ 146union cvmx_dpi_ctl { 147 u64 u64; 148 struct cvmx_dpi_ctl_s { 149 u64 reserved_2_63 : 62; 150 u64 clk : 1; 151 u64 en : 1; 152 } s; 153 struct cvmx_dpi_ctl_cn61xx { 154 u64 reserved_1_63 : 63; 155 u64 en : 1; 156 } cn61xx; 157 struct cvmx_dpi_ctl_s cn63xx; 158 struct cvmx_dpi_ctl_s cn63xxp1; 159 struct cvmx_dpi_ctl_s cn66xx; 160 struct cvmx_dpi_ctl_s cn68xx; 161 struct cvmx_dpi_ctl_s cn68xxp1; 162 struct cvmx_dpi_ctl_cn61xx cn70xx; 163 struct cvmx_dpi_ctl_cn61xx cn70xxp1; 164 struct cvmx_dpi_ctl_cn61xx cn73xx; 165 struct cvmx_dpi_ctl_cn61xx cn78xx; 166 struct cvmx_dpi_ctl_cn61xx cn78xxp1; 167 struct cvmx_dpi_ctl_cn61xx cnf71xx; 168 struct cvmx_dpi_ctl_cn61xx cnf75xx; 169}; 170 171typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t; 172 173/** 174 * cvmx_dpi_dma#_counts 175 * 176 * These registers provide values for determining the number of instructions in the local 177 * instruction FIFO. 178 */ 179union cvmx_dpi_dmax_counts { 180 u64 u64; 181 struct cvmx_dpi_dmax_counts_s { 182 u64 reserved_39_63 : 25; 183 u64 fcnt : 7; 184 u64 dbell : 32; 185 } s; 186 struct cvmx_dpi_dmax_counts_s cn61xx; 187 struct cvmx_dpi_dmax_counts_s cn63xx; 188 struct cvmx_dpi_dmax_counts_s cn63xxp1; 189 struct cvmx_dpi_dmax_counts_s cn66xx; 190 struct cvmx_dpi_dmax_counts_s cn68xx; 191 struct cvmx_dpi_dmax_counts_s cn68xxp1; 192 struct cvmx_dpi_dmax_counts_s cn70xx; 193 struct cvmx_dpi_dmax_counts_s cn70xxp1; 194 struct cvmx_dpi_dmax_counts_s cn73xx; 195 struct cvmx_dpi_dmax_counts_s cn78xx; 196 struct cvmx_dpi_dmax_counts_s cn78xxp1; 197 struct cvmx_dpi_dmax_counts_s cnf71xx; 198 struct cvmx_dpi_dmax_counts_s cnf75xx; 199}; 200 201typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t; 202 203/** 204 * cvmx_dpi_dma#_dbell 205 * 206 * This is the door bell register for the eight DMA instruction queues. 207 * 208 */ 209union cvmx_dpi_dmax_dbell { 210 u64 u64; 211 struct cvmx_dpi_dmax_dbell_s { 212 u64 reserved_16_63 : 48; 213 u64 dbell : 16; 214 } s; 215 struct cvmx_dpi_dmax_dbell_s cn61xx; 216 struct cvmx_dpi_dmax_dbell_s cn63xx; 217 struct cvmx_dpi_dmax_dbell_s cn63xxp1; 218 struct cvmx_dpi_dmax_dbell_s cn66xx; 219 struct cvmx_dpi_dmax_dbell_s cn68xx; 220 struct cvmx_dpi_dmax_dbell_s cn68xxp1; 221 struct cvmx_dpi_dmax_dbell_s cn70xx; 222 struct cvmx_dpi_dmax_dbell_s cn70xxp1; 223 struct cvmx_dpi_dmax_dbell_s cn73xx; 224 struct cvmx_dpi_dmax_dbell_s cn78xx; 225 struct cvmx_dpi_dmax_dbell_s cn78xxp1; 226 struct cvmx_dpi_dmax_dbell_s cnf71xx; 227 struct cvmx_dpi_dmax_dbell_s cnf75xx; 228}; 229 230typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t; 231 232/** 233 * cvmx_dpi_dma#_err_rsp_status 234 */ 235union cvmx_dpi_dmax_err_rsp_status { 236 u64 u64; 237 struct cvmx_dpi_dmax_err_rsp_status_s { 238 u64 reserved_6_63 : 58; 239 u64 status : 6; 240 } s; 241 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; 242 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; 243 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; 244 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; 245 struct cvmx_dpi_dmax_err_rsp_status_s cn70xx; 246 struct cvmx_dpi_dmax_err_rsp_status_s cn70xxp1; 247 struct cvmx_dpi_dmax_err_rsp_status_s cn73xx; 248 struct cvmx_dpi_dmax_err_rsp_status_s cn78xx; 249 struct cvmx_dpi_dmax_err_rsp_status_s cn78xxp1; 250 struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; 251 struct cvmx_dpi_dmax_err_rsp_status_s cnf75xx; 252}; 253 254typedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t; 255 256/** 257 * cvmx_dpi_dma#_ibuff_saddr 258 * 259 * These registers provide the address to start reading instructions for the eight DMA 260 * instruction queues. 261 */ 262union cvmx_dpi_dmax_ibuff_saddr { 263 u64 u64; 264 struct cvmx_dpi_dmax_ibuff_saddr_s { 265 u64 reserved_62_63 : 2; 266 u64 csize : 14; 267 u64 reserved_0_47 : 48; 268 } s; 269 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { 270 u64 reserved_62_63 : 2; 271 u64 csize : 14; 272 u64 reserved_41_47 : 7; 273 u64 idle : 1; 274 u64 reserved_36_39 : 4; 275 u64 saddr : 29; 276 u64 reserved_0_6 : 7; 277 } cn61xx; 278 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; 279 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; 280 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; 281 struct cvmx_dpi_dmax_ibuff_saddr_cn68xx { 282 u64 reserved_62_63 : 2; 283 u64 csize : 14; 284 u64 reserved_41_47 : 7; 285 u64 idle : 1; 286 u64 saddr : 33; 287 u64 reserved_0_6 : 7; 288 } cn68xx; 289 struct cvmx_dpi_dmax_ibuff_saddr_cn68xx cn68xxp1; 290 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn70xx; 291 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn70xxp1; 292 struct cvmx_dpi_dmax_ibuff_saddr_cn73xx { 293 u64 idle : 1; 294 u64 reserved_62_62 : 1; 295 u64 csize : 14; 296 u64 reserved_42_47 : 6; 297 u64 saddr : 35; 298 u64 reserved_0_6 : 7; 299 } cn73xx; 300 struct cvmx_dpi_dmax_ibuff_saddr_cn73xx cn78xx; 301 struct cvmx_dpi_dmax_ibuff_saddr_cn73xx cn78xxp1; 302 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; 303 struct cvmx_dpi_dmax_ibuff_saddr_cn73xx cnf75xx; 304}; 305 306typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t; 307 308/** 309 * cvmx_dpi_dma#_iflight 310 */ 311union cvmx_dpi_dmax_iflight { 312 u64 u64; 313 struct cvmx_dpi_dmax_iflight_s { 314 u64 reserved_3_63 : 61; 315 u64 cnt : 3; 316 } s; 317 struct cvmx_dpi_dmax_iflight_s cn61xx; 318 struct cvmx_dpi_dmax_iflight_s cn66xx; 319 struct cvmx_dpi_dmax_iflight_s cn68xx; 320 struct cvmx_dpi_dmax_iflight_s cn68xxp1; 321 struct cvmx_dpi_dmax_iflight_s cn70xx; 322 struct cvmx_dpi_dmax_iflight_s cn70xxp1; 323 struct cvmx_dpi_dmax_iflight_s cn73xx; 324 struct cvmx_dpi_dmax_iflight_s cn78xx; 325 struct cvmx_dpi_dmax_iflight_s cn78xxp1; 326 struct cvmx_dpi_dmax_iflight_s cnf71xx; 327 struct cvmx_dpi_dmax_iflight_s cnf75xx; 328}; 329 330typedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t; 331 332/** 333 * cvmx_dpi_dma#_naddr 334 * 335 * These registers provide the L2C addresses to read the next Ichunk data. 336 * 337 */ 338union cvmx_dpi_dmax_naddr { 339 u64 u64; 340 struct cvmx_dpi_dmax_naddr_s { 341 u64 reserved_42_63 : 22; 342 u64 addr : 42; 343 } s; 344 struct cvmx_dpi_dmax_naddr_cn61xx { 345 u64 reserved_36_63 : 28; 346 u64 addr : 36; 347 } cn61xx; 348 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; 349 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; 350 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; 351 struct cvmx_dpi_dmax_naddr_cn68xx { 352 u64 reserved_40_63 : 24; 353 u64 addr : 40; 354 } cn68xx; 355 struct cvmx_dpi_dmax_naddr_cn68xx cn68xxp1; 356 struct cvmx_dpi_dmax_naddr_cn61xx cn70xx; 357 struct cvmx_dpi_dmax_naddr_cn61xx cn70xxp1; 358 struct cvmx_dpi_dmax_naddr_s cn73xx; 359 struct cvmx_dpi_dmax_naddr_s cn78xx; 360 struct cvmx_dpi_dmax_naddr_s cn78xxp1; 361 struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; 362 struct cvmx_dpi_dmax_naddr_s cnf75xx; 363}; 364 365typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t; 366 367/** 368 * cvmx_dpi_dma#_reqbnk0 369 * 370 * These registers provide the current contents of the request state machine, bank 0. 371 * 372 */ 373union cvmx_dpi_dmax_reqbnk0 { 374 u64 u64; 375 struct cvmx_dpi_dmax_reqbnk0_s { 376 u64 state : 64; 377 } s; 378 struct cvmx_dpi_dmax_reqbnk0_s cn61xx; 379 struct cvmx_dpi_dmax_reqbnk0_s cn63xx; 380 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; 381 struct cvmx_dpi_dmax_reqbnk0_s cn66xx; 382 struct cvmx_dpi_dmax_reqbnk0_s cn68xx; 383 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; 384 struct cvmx_dpi_dmax_reqbnk0_s cn70xx; 385 struct cvmx_dpi_dmax_reqbnk0_s cn70xxp1; 386 struct cvmx_dpi_dmax_reqbnk0_s cn73xx; 387 struct cvmx_dpi_dmax_reqbnk0_s cn78xx; 388 struct cvmx_dpi_dmax_reqbnk0_s cn78xxp1; 389 struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; 390 struct cvmx_dpi_dmax_reqbnk0_s cnf75xx; 391}; 392 393typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t; 394 395/** 396 * cvmx_dpi_dma#_reqbnk1 397 * 398 * These registers provide the current contents of the request state machine, bank 1. 399 * 400 */ 401union cvmx_dpi_dmax_reqbnk1 { 402 u64 u64; 403 struct cvmx_dpi_dmax_reqbnk1_s { 404 u64 state : 64; 405 } s; 406 struct cvmx_dpi_dmax_reqbnk1_s cn61xx; 407 struct cvmx_dpi_dmax_reqbnk1_s cn63xx; 408 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; 409 struct cvmx_dpi_dmax_reqbnk1_s cn66xx; 410 struct cvmx_dpi_dmax_reqbnk1_s cn68xx; 411 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; 412 struct cvmx_dpi_dmax_reqbnk1_s cn70xx; 413 struct cvmx_dpi_dmax_reqbnk1_s cn70xxp1; 414 struct cvmx_dpi_dmax_reqbnk1_s cn73xx; 415 struct cvmx_dpi_dmax_reqbnk1_s cn78xx; 416 struct cvmx_dpi_dmax_reqbnk1_s cn78xxp1; 417 struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; 418 struct cvmx_dpi_dmax_reqbnk1_s cnf75xx; 419}; 420 421typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t; 422 423/** 424 * cvmx_dpi_dma#_reqq_ctl 425 * 426 * This register contains the control bits for transactions on the eight request queues. 427 * 428 */ 429union cvmx_dpi_dmax_reqq_ctl { 430 u64 u64; 431 struct cvmx_dpi_dmax_reqq_ctl_s { 432 u64 reserved_9_63 : 55; 433 u64 st_cmd : 1; 434 u64 reserved_2_7 : 6; 435 u64 ld_cmd : 2; 436 } s; 437 struct cvmx_dpi_dmax_reqq_ctl_s cn73xx; 438 struct cvmx_dpi_dmax_reqq_ctl_s cn78xx; 439 struct cvmx_dpi_dmax_reqq_ctl_s cn78xxp1; 440 struct cvmx_dpi_dmax_reqq_ctl_s cnf75xx; 441}; 442 443typedef union cvmx_dpi_dmax_reqq_ctl cvmx_dpi_dmax_reqq_ctl_t; 444 445/** 446 * cvmx_dpi_dma_control 447 * 448 * This register controls the operation of DMA input and output. 449 * 450 */ 451union cvmx_dpi_dma_control { 452 u64 u64; 453 struct cvmx_dpi_dma_control_s { 454 u64 reserved_62_63 : 2; 455 u64 dici_mode : 1; 456 u64 pkt_en1 : 1; 457 u64 ffp_dis : 1; 458 u64 commit_mode : 1; 459 u64 pkt_hp : 1; 460 u64 pkt_en : 1; 461 u64 reserved_54_55 : 2; 462 u64 dma_enb : 6; 463 u64 wqecsdis : 1; 464 u64 wqecsoff : 7; 465 u64 zbwcsen : 1; 466 u64 wqecsmode : 2; 467 u64 reserved_35_36 : 2; 468 u64 ncb_tag : 1; 469 u64 b0_lend : 1; 470 u64 reserved_20_32 : 13; 471 u64 o_add1 : 1; 472 u64 o_ro : 1; 473 u64 o_ns : 1; 474 u64 o_es : 2; 475 u64 o_mode : 1; 476 u64 reserved_0_13 : 14; 477 } s; 478 struct cvmx_dpi_dma_control_cn61xx { 479 u64 reserved_62_63 : 2; 480 u64 dici_mode : 1; 481 u64 pkt_en1 : 1; 482 u64 ffp_dis : 1; 483 u64 commit_mode : 1; 484 u64 pkt_hp : 1; 485 u64 pkt_en : 1; 486 u64 reserved_54_55 : 2; 487 u64 dma_enb : 6; 488 u64 reserved_34_47 : 14; 489 u64 b0_lend : 1; 490 u64 dwb_denb : 1; 491 u64 dwb_ichk : 9; 492 u64 fpa_que : 3; 493 u64 o_add1 : 1; 494 u64 o_ro : 1; 495 u64 o_ns : 1; 496 u64 o_es : 2; 497 u64 o_mode : 1; 498 u64 reserved_0_13 : 14; 499 } cn61xx; 500 struct cvmx_dpi_dma_control_cn63xx { 501 u64 reserved_61_63 : 3; 502 u64 pkt_en1 : 1; 503 u64 ffp_dis : 1; 504 u64 commit_mode : 1; 505 u64 pkt_hp : 1; 506 u64 pkt_en : 1; 507 u64 reserved_54_55 : 2; 508 u64 dma_enb : 6; 509 u64 reserved_34_47 : 14; 510 u64 b0_lend : 1; 511 u64 dwb_denb : 1; 512 u64 dwb_ichk : 9; 513 u64 fpa_que : 3; 514 u64 o_add1 : 1; 515 u64 o_ro : 1; 516 u64 o_ns : 1; 517 u64 o_es : 2; 518 u64 o_mode : 1; 519 u64 reserved_0_13 : 14; 520 } cn63xx; 521 struct cvmx_dpi_dma_control_cn63xxp1 { 522 u64 reserved_59_63 : 5; 523 u64 commit_mode : 1; 524 u64 pkt_hp : 1; 525 u64 pkt_en : 1; 526 u64 reserved_54_55 : 2; 527 u64 dma_enb : 6; 528 u64 reserved_34_47 : 14; 529 u64 b0_lend : 1; 530 u64 dwb_denb : 1; 531 u64 dwb_ichk : 9; 532 u64 fpa_que : 3; 533 u64 o_add1 : 1; 534 u64 o_ro : 1; 535 u64 o_ns : 1; 536 u64 o_es : 2; 537 u64 o_mode : 1; 538 u64 reserved_0_13 : 14; 539 } cn63xxp1; 540 struct cvmx_dpi_dma_control_cn63xx cn66xx; 541 struct cvmx_dpi_dma_control_cn61xx cn68xx; 542 struct cvmx_dpi_dma_control_cn63xx cn68xxp1; 543 struct cvmx_dpi_dma_control_cn61xx cn70xx; 544 struct cvmx_dpi_dma_control_cn61xx cn70xxp1; 545 struct cvmx_dpi_dma_control_cn73xx { 546 u64 reserved_60_63 : 4; 547 u64 ffp_dis : 1; 548 u64 commit_mode : 1; 549 u64 reserved_57_57 : 1; 550 u64 pkt_en : 1; 551 u64 reserved_54_55 : 2; 552 u64 dma_enb : 6; 553 u64 wqecsdis : 1; 554 u64 wqecsoff : 7; 555 u64 zbwcsen : 1; 556 u64 wqecsmode : 2; 557 u64 reserved_35_36 : 2; 558 u64 ncb_tag : 1; 559 u64 b0_lend : 1; 560 u64 ldwb : 1; 561 u64 aura_ichk : 12; 562 u64 o_add1 : 1; 563 u64 o_ro : 1; 564 u64 o_ns : 1; 565 u64 o_es : 2; 566 u64 o_mode : 1; 567 u64 reserved_0_13 : 14; 568 } cn73xx; 569 struct cvmx_dpi_dma_control_cn73xx cn78xx; 570 struct cvmx_dpi_dma_control_cn73xx cn78xxp1; 571 struct cvmx_dpi_dma_control_cn61xx cnf71xx; 572 struct cvmx_dpi_dma_control_cn73xx cnf75xx; 573}; 574 575typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t; 576 577/** 578 * cvmx_dpi_dma_eng#_en 579 * 580 * These registers provide control for the DMA engines. 581 * 582 */ 583union cvmx_dpi_dma_engx_en { 584 u64 u64; 585 struct cvmx_dpi_dma_engx_en_s { 586 u64 reserved_39_63 : 25; 587 u64 eng_molr : 7; 588 u64 reserved_8_31 : 24; 589 u64 qen : 8; 590 } s; 591 struct cvmx_dpi_dma_engx_en_cn61xx { 592 u64 reserved_8_63 : 56; 593 u64 qen : 8; 594 } cn61xx; 595 struct cvmx_dpi_dma_engx_en_cn61xx cn63xx; 596 struct cvmx_dpi_dma_engx_en_cn61xx cn63xxp1; 597 struct cvmx_dpi_dma_engx_en_cn61xx cn66xx; 598 struct cvmx_dpi_dma_engx_en_cn61xx cn68xx; 599 struct cvmx_dpi_dma_engx_en_cn61xx cn68xxp1; 600 struct cvmx_dpi_dma_engx_en_cn61xx cn70xx; 601 struct cvmx_dpi_dma_engx_en_cn61xx cn70xxp1; 602 struct cvmx_dpi_dma_engx_en_s cn73xx; 603 struct cvmx_dpi_dma_engx_en_s cn78xx; 604 struct cvmx_dpi_dma_engx_en_s cn78xxp1; 605 struct cvmx_dpi_dma_engx_en_cn61xx cnf71xx; 606 struct cvmx_dpi_dma_engx_en_s cnf75xx; 607}; 608 609typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t; 610 611/** 612 * cvmx_dpi_dma_pp#_cnt 613 * 614 * DPI_DMA_PP[0..3]_CNT = DMA per PP Instr Done Counter 615 * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma 616 * instruction 617 * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter. 618 * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write. 619 * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do 620 * nothing. 621 */ 622union cvmx_dpi_dma_ppx_cnt { 623 u64 u64; 624 struct cvmx_dpi_dma_ppx_cnt_s { 625 u64 reserved_16_63 : 48; 626 u64 cnt : 16; 627 } s; 628 struct cvmx_dpi_dma_ppx_cnt_s cn61xx; 629 struct cvmx_dpi_dma_ppx_cnt_s cn68xx; 630 struct cvmx_dpi_dma_ppx_cnt_s cn70xx; 631 struct cvmx_dpi_dma_ppx_cnt_s cn70xxp1; 632 struct cvmx_dpi_dma_ppx_cnt_s cn73xx; 633 struct cvmx_dpi_dma_ppx_cnt_s cn78xx; 634 struct cvmx_dpi_dma_ppx_cnt_s cn78xxp1; 635 struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; 636 struct cvmx_dpi_dma_ppx_cnt_s cnf75xx; 637}; 638 639typedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t; 640 641/** 642 * cvmx_dpi_dma_pp_int 643 */ 644union cvmx_dpi_dma_pp_int { 645 u64 u64; 646 struct cvmx_dpi_dma_pp_int_s { 647 u64 reserved_48_63 : 16; 648 u64 complete : 48; 649 } s; 650 struct cvmx_dpi_dma_pp_int_cn73xx { 651 u64 reserved_16_63 : 48; 652 u64 complete : 16; 653 } cn73xx; 654 struct cvmx_dpi_dma_pp_int_s cn78xx; 655 struct cvmx_dpi_dma_pp_int_s cn78xxp1; 656 struct cvmx_dpi_dma_pp_int_cn73xx cnf75xx; 657}; 658 659typedef union cvmx_dpi_dma_pp_int cvmx_dpi_dma_pp_int_t; 660 661/** 662 * cvmx_dpi_ecc_ctl 663 * 664 * This register allows inserting ECC errors for testing. 665 * 666 */ 667union cvmx_dpi_ecc_ctl { 668 u64 u64; 669 struct cvmx_dpi_ecc_ctl_s { 670 u64 reserved_33_63 : 31; 671 u64 ram_cdis : 1; 672 u64 reserved_17_31 : 15; 673 u64 ram_flip1 : 1; 674 u64 reserved_1_15 : 15; 675 u64 ram_flip0 : 1; 676 } s; 677 struct cvmx_dpi_ecc_ctl_s cn73xx; 678 struct cvmx_dpi_ecc_ctl_s cn78xx; 679 struct cvmx_dpi_ecc_ctl_s cn78xxp1; 680 struct cvmx_dpi_ecc_ctl_s cnf75xx; 681}; 682 683typedef union cvmx_dpi_ecc_ctl cvmx_dpi_ecc_ctl_t; 684 685/** 686 * cvmx_dpi_ecc_int 687 * 688 * This register contains ECC error interrupt summary bits. 689 * 690 */ 691union cvmx_dpi_ecc_int { 692 u64 u64; 693 struct cvmx_dpi_ecc_int_s { 694 u64 reserved_47_63 : 17; 695 u64 ram_sbe : 15; 696 u64 reserved_15_31 : 17; 697 u64 ram_dbe : 15; 698 } s; 699 struct cvmx_dpi_ecc_int_s cn73xx; 700 struct cvmx_dpi_ecc_int_s cn78xx; 701 struct cvmx_dpi_ecc_int_s cn78xxp1; 702 struct cvmx_dpi_ecc_int_s cnf75xx; 703}; 704 705typedef union cvmx_dpi_ecc_int cvmx_dpi_ecc_int_t; 706 707/** 708 * cvmx_dpi_eng#_buf 709 * 710 * Notes: 711 * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB. 712 * 713 */ 714union cvmx_dpi_engx_buf { 715 u64 u64; 716 struct cvmx_dpi_engx_buf_s { 717 u64 reserved_38_63 : 26; 718 u64 compblks : 6; 719 u64 reserved_10_31 : 22; 720 u64 base : 6; 721 u64 blks : 4; 722 } s; 723 struct cvmx_dpi_engx_buf_cn61xx { 724 u64 reserved_37_63 : 27; 725 u64 compblks : 5; 726 u64 reserved_9_31 : 23; 727 u64 base : 5; 728 u64 blks : 4; 729 } cn61xx; 730 struct cvmx_dpi_engx_buf_cn63xx { 731 u64 reserved_8_63 : 56; 732 u64 base : 4; 733 u64 blks : 4; 734 } cn63xx; 735 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; 736 struct cvmx_dpi_engx_buf_cn61xx cn66xx; 737 struct cvmx_dpi_engx_buf_cn61xx cn68xx; 738 struct cvmx_dpi_engx_buf_cn61xx cn68xxp1; 739 struct cvmx_dpi_engx_buf_cn61xx cn70xx; 740 struct cvmx_dpi_engx_buf_cn61xx cn70xxp1; 741 struct cvmx_dpi_engx_buf_s cn73xx; 742 struct cvmx_dpi_engx_buf_s cn78xx; 743 struct cvmx_dpi_engx_buf_s cn78xxp1; 744 struct cvmx_dpi_engx_buf_cn61xx cnf71xx; 745 struct cvmx_dpi_engx_buf_s cnf75xx; 746}; 747 748typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t; 749 750/** 751 * cvmx_dpi_info_reg 752 */ 753union cvmx_dpi_info_reg { 754 u64 u64; 755 struct cvmx_dpi_info_reg_s { 756 u64 reserved_8_63 : 56; 757 u64 ffp : 4; 758 u64 reserved_2_3 : 2; 759 u64 ncb : 1; 760 u64 rsl : 1; 761 } s; 762 struct cvmx_dpi_info_reg_s cn61xx; 763 struct cvmx_dpi_info_reg_s cn63xx; 764 struct cvmx_dpi_info_reg_cn63xxp1 { 765 u64 reserved_2_63 : 62; 766 u64 ncb : 1; 767 u64 rsl : 1; 768 } cn63xxp1; 769 struct cvmx_dpi_info_reg_s cn66xx; 770 struct cvmx_dpi_info_reg_s cn68xx; 771 struct cvmx_dpi_info_reg_s cn68xxp1; 772 struct cvmx_dpi_info_reg_s cn70xx; 773 struct cvmx_dpi_info_reg_s cn70xxp1; 774 struct cvmx_dpi_info_reg_s cn73xx; 775 struct cvmx_dpi_info_reg_s cn78xx; 776 struct cvmx_dpi_info_reg_s cn78xxp1; 777 struct cvmx_dpi_info_reg_s cnf71xx; 778 struct cvmx_dpi_info_reg_s cnf75xx; 779}; 780 781typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t; 782 783/** 784 * cvmx_dpi_int_en 785 */ 786union cvmx_dpi_int_en { 787 u64 u64; 788 struct cvmx_dpi_int_en_s { 789 u64 reserved_28_63 : 36; 790 u64 sprt3_rst : 1; 791 u64 sprt2_rst : 1; 792 u64 sprt1_rst : 1; 793 u64 sprt0_rst : 1; 794 u64 reserved_23_23 : 1; 795 u64 req_badfil : 1; 796 u64 req_inull : 1; 797 u64 req_anull : 1; 798 u64 req_undflw : 1; 799 u64 req_ovrflw : 1; 800 u64 req_badlen : 1; 801 u64 req_badadr : 1; 802 u64 dmadbo : 8; 803 u64 reserved_2_7 : 6; 804 u64 nfovr : 1; 805 u64 nderr : 1; 806 } s; 807 struct cvmx_dpi_int_en_s cn61xx; 808 struct cvmx_dpi_int_en_cn63xx { 809 u64 reserved_26_63 : 38; 810 u64 sprt1_rst : 1; 811 u64 sprt0_rst : 1; 812 u64 reserved_23_23 : 1; 813 u64 req_badfil : 1; 814 u64 req_inull : 1; 815 u64 req_anull : 1; 816 u64 req_undflw : 1; 817 u64 req_ovrflw : 1; 818 u64 req_badlen : 1; 819 u64 req_badadr : 1; 820 u64 dmadbo : 8; 821 u64 reserved_2_7 : 6; 822 u64 nfovr : 1; 823 u64 nderr : 1; 824 } cn63xx; 825 struct cvmx_dpi_int_en_cn63xx cn63xxp1; 826 struct cvmx_dpi_int_en_s cn66xx; 827 struct cvmx_dpi_int_en_cn63xx cn68xx; 828 struct cvmx_dpi_int_en_cn63xx cn68xxp1; 829 struct cvmx_dpi_int_en_cn70xx { 830 u64 reserved_28_63 : 36; 831 u64 sprt3_rst : 1; 832 u64 sprt2_rst : 1; 833 u64 sprt1_rst : 1; 834 u64 sprt0_rst : 1; 835 u64 reserved_23_23 : 1; 836 u64 req_badfil : 1; 837 u64 req_inull : 1; 838 u64 req_anull : 1; 839 u64 req_undflw : 1; 840 u64 req_ovrflw : 1; 841 u64 req_badlen : 1; 842 u64 req_badadr : 1; 843 u64 dmadbo : 8; 844 u64 reserved_7_2 : 6; 845 u64 nfovr : 1; 846 u64 nderr : 1; 847 } cn70xx; 848 struct cvmx_dpi_int_en_cn70xx cn70xxp1; 849 struct cvmx_dpi_int_en_s cnf71xx; 850}; 851 852typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t; 853 854/** 855 * cvmx_dpi_int_reg 856 * 857 * This register contains error flags for DPI. 858 * 859 */ 860union cvmx_dpi_int_reg { 861 u64 u64; 862 struct cvmx_dpi_int_reg_s { 863 u64 reserved_28_63 : 36; 864 u64 sprt3_rst : 1; 865 u64 sprt2_rst : 1; 866 u64 sprt1_rst : 1; 867 u64 sprt0_rst : 1; 868 u64 reserved_23_23 : 1; 869 u64 req_badfil : 1; 870 u64 req_inull : 1; 871 u64 req_anull : 1; 872 u64 req_undflw : 1; 873 u64 req_ovrflw : 1; 874 u64 req_badlen : 1; 875 u64 req_badadr : 1; 876 u64 dmadbo : 8; 877 u64 reserved_2_7 : 6; 878 u64 nfovr : 1; 879 u64 nderr : 1; 880 } s; 881 struct cvmx_dpi_int_reg_s cn61xx; 882 struct cvmx_dpi_int_reg_cn63xx { 883 u64 reserved_26_63 : 38; 884 u64 sprt1_rst : 1; 885 u64 sprt0_rst : 1; 886 u64 reserved_23_23 : 1; 887 u64 req_badfil : 1; 888 u64 req_inull : 1; 889 u64 req_anull : 1; 890 u64 req_undflw : 1; 891 u64 req_ovrflw : 1; 892 u64 req_badlen : 1; 893 u64 req_badadr : 1; 894 u64 dmadbo : 8; 895 u64 reserved_2_7 : 6; 896 u64 nfovr : 1; 897 u64 nderr : 1; 898 } cn63xx; 899 struct cvmx_dpi_int_reg_cn63xx cn63xxp1; 900 struct cvmx_dpi_int_reg_s cn66xx; 901 struct cvmx_dpi_int_reg_cn63xx cn68xx; 902 struct cvmx_dpi_int_reg_cn63xx cn68xxp1; 903 struct cvmx_dpi_int_reg_s cn70xx; 904 struct cvmx_dpi_int_reg_s cn70xxp1; 905 struct cvmx_dpi_int_reg_cn73xx { 906 u64 reserved_23_63 : 41; 907 u64 req_badfil : 1; 908 u64 req_inull : 1; 909 u64 req_anull : 1; 910 u64 req_undflw : 1; 911 u64 req_ovrflw : 1; 912 u64 req_badlen : 1; 913 u64 req_badadr : 1; 914 u64 dmadbo : 8; 915 u64 reserved_2_7 : 6; 916 u64 nfovr : 1; 917 u64 nderr : 1; 918 } cn73xx; 919 struct cvmx_dpi_int_reg_cn73xx cn78xx; 920 struct cvmx_dpi_int_reg_s cn78xxp1; 921 struct cvmx_dpi_int_reg_s cnf71xx; 922 struct cvmx_dpi_int_reg_cn73xx cnf75xx; 923}; 924 925typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t; 926 927/** 928 * cvmx_dpi_ncb#_cfg 929 */ 930union cvmx_dpi_ncbx_cfg { 931 u64 u64; 932 struct cvmx_dpi_ncbx_cfg_s { 933 u64 reserved_6_63 : 58; 934 u64 molr : 6; 935 } s; 936 struct cvmx_dpi_ncbx_cfg_s cn61xx; 937 struct cvmx_dpi_ncbx_cfg_s cn66xx; 938 struct cvmx_dpi_ncbx_cfg_s cn68xx; 939 struct cvmx_dpi_ncbx_cfg_s cn70xx; 940 struct cvmx_dpi_ncbx_cfg_s cn70xxp1; 941 struct cvmx_dpi_ncbx_cfg_s cn73xx; 942 struct cvmx_dpi_ncbx_cfg_s cn78xx; 943 struct cvmx_dpi_ncbx_cfg_s cn78xxp1; 944 struct cvmx_dpi_ncbx_cfg_s cnf71xx; 945 struct cvmx_dpi_ncbx_cfg_s cnf75xx; 946}; 947 948typedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t; 949 950/** 951 * cvmx_dpi_ncb_ctl 952 * 953 * This register chooses which NCB interface DPI uses for L2/DRAM reads/writes. 954 * 955 */ 956union cvmx_dpi_ncb_ctl { 957 u64 u64; 958 struct cvmx_dpi_ncb_ctl_s { 959 u64 reserved_25_63 : 39; 960 u64 ncbsel_prt_xor_dis : 1; 961 u64 reserved_21_23 : 3; 962 u64 ncbsel_zbw : 1; 963 u64 reserved_17_19 : 3; 964 u64 ncbsel_req : 1; 965 u64 reserved_13_15 : 3; 966 u64 ncbsel_dst : 1; 967 u64 reserved_9_11 : 3; 968 u64 ncbsel_src : 1; 969 u64 reserved_1_7 : 7; 970 u64 prt : 1; 971 } s; 972 struct cvmx_dpi_ncb_ctl_cn73xx { 973 u64 reserved_25_63 : 39; 974 u64 ncbsel_prt_xor_dis : 1; 975 u64 reserved_21_23 : 3; 976 u64 ncbsel_zbw : 1; 977 u64 reserved_17_19 : 3; 978 u64 ncbsel_req : 1; 979 u64 reserved_13_15 : 3; 980 u64 ncbsel_dst : 1; 981 u64 reserved_9_11 : 3; 982 u64 ncbsel_src : 1; 983 u64 reserved_0_7 : 8; 984 } cn73xx; 985 struct cvmx_dpi_ncb_ctl_s cn78xx; 986 struct cvmx_dpi_ncb_ctl_s cn78xxp1; 987 struct cvmx_dpi_ncb_ctl_cn73xx cnf75xx; 988}; 989 990typedef union cvmx_dpi_ncb_ctl cvmx_dpi_ncb_ctl_t; 991 992/** 993 * cvmx_dpi_pint_info 994 * 995 * This register provides DPI packet interrupt information. 996 * 997 */ 998union cvmx_dpi_pint_info { 999 u64 u64; 1000 struct cvmx_dpi_pint_info_s {
1001 u64 reserved_14_63 : 50; 1002 u64 iinfo : 6; 1003 u64 reserved_6_7 : 2; 1004 u64 sinfo : 6; 1005 } s; 1006 struct cvmx_dpi_pint_info_s cn61xx; 1007 struct cvmx_dpi_pint_info_s cn63xx; 1008 struct cvmx_dpi_pint_info_s cn63xxp1; 1009 struct cvmx_dpi_pint_info_s cn66xx; 1010 struct cvmx_dpi_pint_info_s cn68xx; 1011 struct cvmx_dpi_pint_info_s cn68xxp1; 1012 struct cvmx_dpi_pint_info_s cn70xx; 1013 struct cvmx_dpi_pint_info_s cn70xxp1; 1014 struct cvmx_dpi_pint_info_s cn73xx; 1015 struct cvmx_dpi_pint_info_s cn78xx; 1016 struct cvmx_dpi_pint_info_s cn78xxp1; 1017 struct cvmx_dpi_pint_info_s cnf71xx; 1018 struct cvmx_dpi_pint_info_s cnf75xx; 1019}; 1020 1021typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t; 1022 1023/** 1024 * cvmx_dpi_pkt_err_rsp 1025 */ 1026union cvmx_dpi_pkt_err_rsp { 1027 u64 u64; 1028 struct cvmx_dpi_pkt_err_rsp_s { 1029 u64 reserved_1_63 : 63; 1030 u64 pkterr : 1; 1031 } s; 1032 struct cvmx_dpi_pkt_err_rsp_s cn61xx; 1033 struct cvmx_dpi_pkt_err_rsp_s cn63xx; 1034 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; 1035 struct cvmx_dpi_pkt_err_rsp_s cn66xx; 1036 struct cvmx_dpi_pkt_err_rsp_s cn68xx; 1037 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; 1038 struct cvmx_dpi_pkt_err_rsp_s cn70xx; 1039 struct cvmx_dpi_pkt_err_rsp_s cn70xxp1; 1040 struct cvmx_dpi_pkt_err_rsp_s cn73xx; 1041 struct cvmx_dpi_pkt_err_rsp_s cn78xx; 1042 struct cvmx_dpi_pkt_err_rsp_s cn78xxp1; 1043 struct cvmx_dpi_pkt_err_rsp_s cnf71xx; 1044 struct cvmx_dpi_pkt_err_rsp_s cnf75xx; 1045}; 1046 1047typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t; 1048 1049/** 1050 * cvmx_dpi_req_err_rsp 1051 */ 1052union cvmx_dpi_req_err_rsp { 1053 u64 u64; 1054 struct cvmx_dpi_req_err_rsp_s { 1055 u64 reserved_8_63 : 56; 1056 u64 qerr : 8; 1057 } s; 1058 struct cvmx_dpi_req_err_rsp_s cn61xx; 1059 struct cvmx_dpi_req_err_rsp_s cn63xx; 1060 struct cvmx_dpi_req_err_rsp_s cn63xxp1; 1061 struct cvmx_dpi_req_err_rsp_s cn66xx; 1062 struct cvmx_dpi_req_err_rsp_s cn68xx; 1063 struct cvmx_dpi_req_err_rsp_s cn68xxp1; 1064 struct cvmx_dpi_req_err_rsp_s cn70xx; 1065 struct cvmx_dpi_req_err_rsp_s cn70xxp1; 1066 struct cvmx_dpi_req_err_rsp_s cn73xx; 1067 struct cvmx_dpi_req_err_rsp_s cn78xx; 1068 struct cvmx_dpi_req_err_rsp_s cn78xxp1; 1069 struct cvmx_dpi_req_err_rsp_s cnf71xx; 1070 struct cvmx_dpi_req_err_rsp_s cnf75xx; 1071}; 1072 1073typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t; 1074 1075/** 1076 * cvmx_dpi_req_err_rsp_en 1077 */ 1078union cvmx_dpi_req_err_rsp_en { 1079 u64 u64; 1080 struct cvmx_dpi_req_err_rsp_en_s { 1081 u64 reserved_8_63 : 56; 1082 u64 en : 8; 1083 } s; 1084 struct cvmx_dpi_req_err_rsp_en_s cn61xx; 1085 struct cvmx_dpi_req_err_rsp_en_s cn63xx; 1086 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; 1087 struct cvmx_dpi_req_err_rsp_en_s cn66xx; 1088 struct cvmx_dpi_req_err_rsp_en_s cn68xx; 1089 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; 1090 struct cvmx_dpi_req_err_rsp_en_s cn70xx; 1091 struct cvmx_dpi_req_err_rsp_en_s cn70xxp1; 1092 struct cvmx_dpi_req_err_rsp_en_s cn73xx; 1093 struct cvmx_dpi_req_err_rsp_en_s cn78xx; 1094 struct cvmx_dpi_req_err_rsp_en_s cn78xxp1; 1095 struct cvmx_dpi_req_err_rsp_en_s cnf71xx; 1096 struct cvmx_dpi_req_err_rsp_en_s cnf75xx; 1097}; 1098 1099typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t; 1100 1101/** 1102 * cvmx_dpi_req_err_rst 1103 */ 1104union cvmx_dpi_req_err_rst { 1105 u64 u64; 1106 struct cvmx_dpi_req_err_rst_s { 1107 u64 reserved_8_63 : 56; 1108 u64 qerr : 8; 1109 } s; 1110 struct cvmx_dpi_req_err_rst_s cn61xx; 1111 struct cvmx_dpi_req_err_rst_s cn63xx; 1112 struct cvmx_dpi_req_err_rst_s cn63xxp1; 1113 struct cvmx_dpi_req_err_rst_s cn66xx; 1114 struct cvmx_dpi_req_err_rst_s cn68xx; 1115 struct cvmx_dpi_req_err_rst_s cn68xxp1; 1116 struct cvmx_dpi_req_err_rst_s cn70xx; 1117 struct cvmx_dpi_req_err_rst_s cn70xxp1; 1118 struct cvmx_dpi_req_err_rst_s cn73xx; 1119 struct cvmx_dpi_req_err_rst_s cn78xx; 1120 struct cvmx_dpi_req_err_rst_s cn78xxp1; 1121 struct cvmx_dpi_req_err_rst_s cnf71xx; 1122 struct cvmx_dpi_req_err_rst_s cnf75xx; 1123}; 1124 1125typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t; 1126 1127/** 1128 * cvmx_dpi_req_err_rst_en 1129 */ 1130union cvmx_dpi_req_err_rst_en { 1131 u64 u64; 1132 struct cvmx_dpi_req_err_rst_en_s { 1133 u64 reserved_8_63 : 56; 1134 u64 en : 8; 1135 } s; 1136 struct cvmx_dpi_req_err_rst_en_s cn61xx; 1137 struct cvmx_dpi_req_err_rst_en_s cn63xx; 1138 struct cvmx_dpi_req_err_rst_en_s cn63xxp1; 1139 struct cvmx_dpi_req_err_rst_en_s cn66xx; 1140 struct cvmx_dpi_req_err_rst_en_s cn68xx; 1141 struct cvmx_dpi_req_err_rst_en_s cn68xxp1; 1142 struct cvmx_dpi_req_err_rst_en_s cn70xx; 1143 struct cvmx_dpi_req_err_rst_en_s cn70xxp1; 1144 struct cvmx_dpi_req_err_rst_en_s cn73xx; 1145 struct cvmx_dpi_req_err_rst_en_s cn78xx; 1146 struct cvmx_dpi_req_err_rst_en_s cn78xxp1; 1147 struct cvmx_dpi_req_err_rst_en_s cnf71xx; 1148 struct cvmx_dpi_req_err_rst_en_s cnf75xx; 1149}; 1150 1151typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t; 1152 1153/** 1154 * cvmx_dpi_req_err_skip_comp 1155 */ 1156union cvmx_dpi_req_err_skip_comp { 1157 u64 u64; 1158 struct cvmx_dpi_req_err_skip_comp_s { 1159 u64 reserved_24_63 : 40; 1160 u64 en_rst : 8; 1161 u64 reserved_8_15 : 8; 1162 u64 en_rsp : 8; 1163 } s; 1164 struct cvmx_dpi_req_err_skip_comp_s cn61xx; 1165 struct cvmx_dpi_req_err_skip_comp_s cn66xx; 1166 struct cvmx_dpi_req_err_skip_comp_s cn68xx; 1167 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; 1168 struct cvmx_dpi_req_err_skip_comp_s cn70xx; 1169 struct cvmx_dpi_req_err_skip_comp_s cn70xxp1; 1170 struct cvmx_dpi_req_err_skip_comp_s cn73xx; 1171 struct cvmx_dpi_req_err_skip_comp_s cn78xx; 1172 struct cvmx_dpi_req_err_skip_comp_s cn78xxp1; 1173 struct cvmx_dpi_req_err_skip_comp_s cnf71xx; 1174 struct cvmx_dpi_req_err_skip_comp_s cnf75xx; 1175}; 1176 1177typedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t; 1178 1179/** 1180 * cvmx_dpi_req_gbl_en 1181 */ 1182union cvmx_dpi_req_gbl_en { 1183 u64 u64; 1184 struct cvmx_dpi_req_gbl_en_s { 1185 u64 reserved_8_63 : 56; 1186 u64 qen : 8; 1187 } s; 1188 struct cvmx_dpi_req_gbl_en_s cn61xx; 1189 struct cvmx_dpi_req_gbl_en_s cn63xx; 1190 struct cvmx_dpi_req_gbl_en_s cn63xxp1; 1191 struct cvmx_dpi_req_gbl_en_s cn66xx; 1192 struct cvmx_dpi_req_gbl_en_s cn68xx; 1193 struct cvmx_dpi_req_gbl_en_s cn68xxp1; 1194 struct cvmx_dpi_req_gbl_en_s cn70xx; 1195 struct cvmx_dpi_req_gbl_en_s cn70xxp1; 1196 struct cvmx_dpi_req_gbl_en_s cn73xx; 1197 struct cvmx_dpi_req_gbl_en_s cn78xx; 1198 struct cvmx_dpi_req_gbl_en_s cn78xxp1; 1199 struct cvmx_dpi_req_gbl_en_s cnf71xx; 1200 struct cvmx_dpi_req_gbl_en_s cnf75xx; 1201}; 1202 1203typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t; 1204 1205/** 1206 * cvmx_dpi_sli_prt#_cfg 1207 * 1208 * This register configures the max read request size, max payload size, and max number of SLI 1209 * tags in use. Indexed by SLI_PORT_E. 1210 */ 1211union cvmx_dpi_sli_prtx_cfg { 1212 u64 u64; 1213 struct cvmx_dpi_sli_prtx_cfg_s { 1214 u64 reserved_29_63 : 35; 1215 u64 ncbsel : 1; 1216 u64 reserved_25_27 : 3; 1217 u64 halt : 1; 1218 u64 qlm_cfg : 4; 1219 u64 reserved_17_19 : 3; 1220 u64 rd_mode : 1; 1221 u64 reserved_15_15 : 1; 1222 u64 molr : 7; 1223 u64 mps_lim : 1; 1224 u64 reserved_5_6 : 2; 1225 u64 mps : 1; 1226 u64 mrrs_lim : 1; 1227 u64 reserved_2_2 : 1; 1228 u64 mrrs : 2; 1229 } s; 1230 struct cvmx_dpi_sli_prtx_cfg_cn61xx { 1231 u64 reserved_25_63 : 39; 1232 u64 halt : 1; 1233 u64 qlm_cfg : 4; 1234 u64 reserved_17_19 : 3; 1235 u64 rd_mode : 1; 1236 u64 reserved_14_15 : 2; 1237 u64 molr : 6; 1238 u64 mps_lim : 1; 1239 u64 reserved_5_6 : 2; 1240 u64 mps : 1; 1241 u64 mrrs_lim : 1; 1242 u64 reserved_2_2 : 1; 1243 u64 mrrs : 2; 1244 } cn61xx; 1245 struct cvmx_dpi_sli_prtx_cfg_cn63xx { 1246 u64 reserved_25_63 : 39; 1247 u64 halt : 1; 1248 u64 reserved_21_23 : 3; 1249 u64 qlm_cfg : 1; 1250 u64 reserved_17_19 : 3; 1251 u64 rd_mode : 1; 1252 u64 reserved_14_15 : 2; 1253 u64 molr : 6; 1254 u64 mps_lim : 1; 1255 u64 reserved_5_6 : 2; 1256 u64 mps : 1; 1257 u64 mrrs_lim : 1; 1258 u64 reserved_2_2 : 1; 1259 u64 mrrs : 2; 1260 } cn63xx; 1261 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; 1262 struct cvmx_dpi_sli_prtx_cfg_cn61xx cn66xx; 1263 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; 1264 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; 1265 struct cvmx_dpi_sli_prtx_cfg_cn70xx { 1266 u64 reserved_25_63 : 39; 1267 u64 halt : 1; 1268 u64 reserved_17_23 : 7; 1269 u64 rd_mode : 1; 1270 u64 reserved_14_15 : 2; 1271 u64 molr : 6; 1272 u64 mps_lim : 1; 1273 u64 reserved_5_6 : 2; 1274 u64 mps : 1; 1275 u64 mrrs_lim : 1; 1276 u64 reserved_2_2 : 1; 1277 u64 mrrs : 2; 1278 } cn70xx; 1279 struct cvmx_dpi_sli_prtx_cfg_cn70xx cn70xxp1; 1280 struct cvmx_dpi_sli_prtx_cfg_cn73xx { 1281 u64 reserved_29_63 : 35; 1282 u64 ncbsel : 1; 1283 u64 reserved_25_27 : 3; 1284 u64 halt : 1; 1285 u64 reserved_21_23 : 3; 1286 u64 qlm_cfg : 1; 1287 u64 reserved_17_19 : 3; 1288 u64 rd_mode : 1; 1289 u64 reserved_15_15 : 1; 1290 u64 molr : 7; 1291 u64 mps_lim : 1; 1292 u64 reserved_5_6 : 2; 1293 u64 mps : 1; 1294 u64 mrrs_lim : 1; 1295 u64 reserved_2_2 : 1; 1296 u64 mrrs : 2; 1297 } cn73xx; 1298 struct cvmx_dpi_sli_prtx_cfg_cn73xx cn78xx; 1299 struct cvmx_dpi_sli_prtx_cfg_cn73xx cn78xxp1; 1300 struct cvmx_dpi_sli_prtx_cfg_cn61xx cnf71xx; 1301 struct cvmx_dpi_sli_prtx_cfg_cn73xx cnf75xx; 1302}; 1303 1304typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t; 1305 1306/** 1307 * cvmx_dpi_sli_prt#_err 1308 * 1309 * This register logs the address associated with the reported SLI error response. 1310 * Indexed by SLI_PORT_E. 1311 */ 1312union cvmx_dpi_sli_prtx_err { 1313 u64 u64; 1314 struct cvmx_dpi_sli_prtx_err_s { 1315 u64 addr : 61; 1316 u64 reserved_0_2 : 3; 1317 } s; 1318 struct cvmx_dpi_sli_prtx_err_s cn61xx; 1319 struct cvmx_dpi_sli_prtx_err_s cn63xx; 1320 struct cvmx_dpi_sli_prtx_err_s cn63xxp1; 1321 struct cvmx_dpi_sli_prtx_err_s cn66xx; 1322 struct cvmx_dpi_sli_prtx_err_s cn68xx; 1323 struct cvmx_dpi_sli_prtx_err_s cn68xxp1; 1324 struct cvmx_dpi_sli_prtx_err_s cn70xx; 1325 struct cvmx_dpi_sli_prtx_err_s cn70xxp1; 1326 struct cvmx_dpi_sli_prtx_err_s cn73xx; 1327 struct cvmx_dpi_sli_prtx_err_s cn78xx; 1328 struct cvmx_dpi_sli_prtx_err_s cn78xxp1; 1329 struct cvmx_dpi_sli_prtx_err_s cnf71xx; 1330 struct cvmx_dpi_sli_prtx_err_s cnf75xx; 1331}; 1332 1333typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t; 1334 1335/** 1336 * cvmx_dpi_sli_prt#_err_info 1337 * 1338 * This register logs information associated with the reported SLI error response. 1339 * Indexed by SLI_PORT_E. 1340 */ 1341union cvmx_dpi_sli_prtx_err_info { 1342 u64 u64; 1343 struct cvmx_dpi_sli_prtx_err_info_s { 1344 u64 reserved_9_63 : 55; 1345 u64 lock : 1; 1346 u64 reserved_5_7 : 3; 1347 u64 type : 1; 1348 u64 reserved_3_3 : 1; 1349 u64 reqq : 3; 1350 } s; 1351 struct cvmx_dpi_sli_prtx_err_info_s cn61xx; 1352 struct cvmx_dpi_sli_prtx_err_info_s cn63xx; 1353 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; 1354 struct cvmx_dpi_sli_prtx_err_info_s cn66xx; 1355 struct cvmx_dpi_sli_prtx_err_info_s cn68xx; 1356 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; 1357 struct cvmx_dpi_sli_prtx_err_info_s cn70xx; 1358 struct cvmx_dpi_sli_prtx_err_info_s cn70xxp1; 1359 struct cvmx_dpi_sli_prtx_err_info_cn73xx { 1360 u64 reserved_32_63 : 32; 1361 u64 pvf : 16; 1362 u64 reserved_9_15 : 7; 1363 u64 lock : 1; 1364 u64 reserved_5_7 : 3; 1365 u64 type : 1; 1366 u64 reserved_3_3 : 1; 1367 u64 reqq : 3; 1368 } cn73xx; 1369 struct cvmx_dpi_sli_prtx_err_info_cn73xx cn78xx; 1370 struct cvmx_dpi_sli_prtx_err_info_cn78xxp1 { 1371 u64 reserved_23_63 : 41; 1372 u64 vf : 7; 1373 u64 reserved_9_15 : 7; 1374 u64 lock : 1; 1375 u64 reserved_5_7 : 3; 1376 u64 type : 1; 1377 u64 reserved_3_3 : 1; 1378 u64 reqq : 3; 1379 } cn78xxp1; 1380 struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; 1381 struct cvmx_dpi_sli_prtx_err_info_cn73xx cnf75xx; 1382}; 1383 1384typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t; 1385 1386/** 1387 * cvmx_dpi_srio_rx_bell# 1388 * 1389 * Reading this register pops an entry off the corresponding SRIO RX doorbell FIFO. 1390 * The chip supports 16 FIFOs per SRIO interface for a total of 32 FIFOs/Registers. 1391 * The MSB of the registers indicates the MAC while the 4 LSBs indicate the FIFO. 1392 * Information on the doorbell allocation can be found in SRIO()_RX_BELL_CTRL. 1393 */ 1394union cvmx_dpi_srio_rx_bellx { 1395 u64 u64; 1396 struct cvmx_dpi_srio_rx_bellx_s { 1397 u64 reserved_48_63 : 16; 1398 u64 data : 16; 1399 u64 sid : 16; 1400 u64 count : 8; 1401 u64 reserved_5_7 : 3; 1402 u64 dest_id : 1; 1403 u64 id16 : 1; 1404 u64 reserved_2_2 : 1; 1405 u64 dpriority : 2; 1406 } s; 1407 struct cvmx_dpi_srio_rx_bellx_s cnf75xx; 1408}; 1409 1410typedef union cvmx_dpi_srio_rx_bellx cvmx_dpi_srio_rx_bellx_t; 1411 1412/** 1413 * cvmx_dpi_srio_rx_bell_seq# 1414 * 1415 * This register contains the value of the sequence counter when the doorbell 1416 * was received and a shadow copy of the Bell FIFO Count that can be read without 1417 * emptying the FIFO. This register must be read prior to corresponding 1418 * DPI_SRIO_RX_BELL register to link the doorbell and sequence number. 1419 * 1420 * Information on the Doorbell Allocation can be found in SRIO()_RX_BELL_CTRL. 1421 */ 1422union cvmx_dpi_srio_rx_bell_seqx { 1423 u64 u64; 1424 struct cvmx_dpi_srio_rx_bell_seqx_s { 1425 u64 reserved_40_63 : 24; 1426 u64 count : 8; 1427 u64 sid : 32; 1428 } s; 1429 struct cvmx_dpi_srio_rx_bell_seqx_s cnf75xx; 1430}; 1431 1432typedef union cvmx_dpi_srio_rx_bell_seqx cvmx_dpi_srio_rx_bell_seqx_t; 1433 1434/** 1435 * cvmx_dpi_swa_q_vmid 1436 * 1437 * Not used. 1438 * 1439 */ 1440union cvmx_dpi_swa_q_vmid { 1441 u64 u64; 1442 struct cvmx_dpi_swa_q_vmid_s { 1443 u64 vmid7 : 8; 1444 u64 vmid6 : 8; 1445 u64 vmid5 : 8; 1446 u64 vmid4 : 8; 1447 u64 vmid3 : 8; 1448 u64 vmid2 : 8; 1449 u64 vmid1 : 8; 1450 u64 vmid0 : 8; 1451 } s; 1452 struct cvmx_dpi_swa_q_vmid_s cn73xx; 1453 struct cvmx_dpi_swa_q_vmid_s cn78xx; 1454 struct cvmx_dpi_swa_q_vmid_s cn78xxp1; 1455 struct cvmx_dpi_swa_q_vmid_s cnf75xx; 1456}; 1457 1458typedef union cvmx_dpi_swa_q_vmid cvmx_dpi_swa_q_vmid_t; 1459 1460#endif 1461