LXR uboot/board/freescale/imx93

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2022 NXP
   4 */
   5
   6#include <common.h>
   7#include <command.h>
   8#include <cpu_func.h>
   9#include <hang.h>
  10#include <image.h>
  11#include <init.h>
  12#include <log.h>
  13#include <spl.h>
  14#include <asm/global_data.h>
  15#include <asm/io.h>
  16#include <asm/arch/imx93_pins.h>
  17#include <asm/arch/clock.h>
  18#include <asm/arch/sys_proto.h>
  19#include <asm/mach-imx/boot_mode.h>
  20#include <asm/mach-imx/mxc_i2c.h>
  21#include <asm/arch-mx7ulp/gpio.h>
  22#include <asm/mach-imx/syscounter.h>
  23#include <asm/mach-imx/s400_api.h>
  24#include <dm/uclass.h>
  25#include <dm/device.h>
  26#include <dm/uclass-internal.h>
  27#include <dm/device-internal.h>
  28#include <linux/delay.h>
  29#include <asm/arch/clock.h>
  30#include <asm/arch/ccm_regs.h>
  31#include <asm/arch/ddr.h>
  32#include <power/pmic.h>
  33#include <power/pca9450.h>
  34#include <asm/arch/trdc.h>
  35
  36DECLARE_GLOBAL_DATA_PTR;
  37
  38int spl_board_boot_device(enum boot_device boot_dev_spl)
  39{
  40        return BOOT_DEVICE_BOOTROM;
  41}
  42
  43void spl_board_init(void)
  44{
  45        puts("Normal Boot\n");
  46}
  47
  48void spl_dram_init(void)
  49{
  50        ddr_init(&dram_timing);
  51}
  52
  53#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
  54int power_init_board(void)
  55{
  56        struct udevice *dev;
  57        int ret;
  58
  59        ret = pmic_get("pmic@25", &dev);
  60        if (ret == -ENODEV) {
  61                puts("No pca9450@25\n");
  62                return 0;
  63        }
  64        if (ret != 0)
  65                return ret;
  66
  67        /* BUCKxOUT_DVS0/1 control BUCK123 output */
  68        pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
  69
  70        /* enable DVS control through PMIC_STBY_REQ */
  71        pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
  72
  73        if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
  74                /* 0.75v for Low drive mode
  75                 */
  76                pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
  77                pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
  78        } else {
  79                /* 0.9v for Over drive mode
  80                 */
  81                pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
  82                pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
  83        }
  84
  85        /* set standby voltage to 0.65v */
  86        pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
  87
  88        /* I2C_LT_EN*/
  89        pmic_reg_write(dev, 0xa, 0x3);
  90        return 0;
  91}
  92#endif
  93
  94extern int imx9_probe_mu(void *ctx, struct event *event);
  95void board_init_f(ulong dummy)
  96{
  97        int ret;
  98
  99        /* Clear the BSS. */
 100        memset(__bss_start, 0, __bss_end - __bss_start);
 101
 102        timer_init();
 103
 104        arch_cpu_init();
 105
 106        board_early_init_f();
 107
 108        spl_early_init();
 109
 110        preloader_console_init();
 111
 112        ret = imx9_probe_mu(NULL, NULL);
 113        if (ret) {
 114                printf("Fail to init Sentinel API\n");
 115        } else {
 116                printf("SOC: 0x%x\n", gd->arch.soc_rev);
 117                printf("LC: 0x%x\n", gd->arch.lifecycle);
 118        }
 119
 120        power_init_board();
 121
 122        if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
 123                set_arm_clk(get_cpu_speed_grade_hz());
 124
 125        /* Init power of mix */
 126        soc_power_init();
 127
 128        /* Setup TRDC for DDR access */
 129        trdc_init();
 130
 131        /* DDR initialization */
 132        spl_dram_init();
 133
 134        /* Put M33 into CPUWAIT for following kick */
 135        ret = m33_prepare();
 136        if (!ret)
 137                printf("M33 prepare ok\n");
 138
 139        board_init_r(NULL, 0);
 140}
 141