LXR uboot/board/freescale/ls1043ardb/cpld.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2015 Freescale Semiconductor
   4 *
   5 * Freescale LS1043ARDB board-specific CPLD controlling supports.
   6 */
   7
   8#include <common.h>
   9#include <command.h>
  10#include <asm/io.h>
  11#include "cpld.h"
  12
  13u8 cpld_read(unsigned int reg)
  14{
  15        void *p = (void *)CFG_SYS_CPLD_BASE;
  16
  17        return in_8(p + reg);
  18}
  19
  20void cpld_write(unsigned int reg, u8 value)
  21{
  22        void *p = (void *)CFG_SYS_CPLD_BASE;
  23
  24        out_8(p + reg, value);
  25}
  26
  27/* Set the boot bank to the alternate bank */
  28void cpld_set_altbank(void)
  29{
  30        u16 reg = CPLD_CFG_RCW_SRC_NOR;
  31        u8 reg4 = CPLD_READ(soft_mux_on);
  32        u8 reg5 = (u8)(reg >> 1);
  33        u8 reg6 = (u8)(reg & 1);
  34        u8 reg7 = CPLD_READ(vbank);
  35
  36        cpld_rev_bit(&reg5);
  37
  38        CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
  39
  40        CPLD_WRITE(cfg_rcw_src1, reg5);
  41        CPLD_WRITE(cfg_rcw_src2, reg6);
  42
  43        reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
  44        CPLD_WRITE(vbank, reg7);
  45
  46        CPLD_WRITE(system_rst, 1);
  47}
  48
  49/* Set the boot bank to the default bank */
  50void cpld_set_defbank(void)
  51{
  52        u16 reg = CPLD_CFG_RCW_SRC_NOR;
  53        u8 reg4 = CPLD_READ(soft_mux_on);
  54        u8 reg5 = (u8)(reg >> 1);
  55        u8 reg6 = (u8)(reg & 1);
  56
  57        cpld_rev_bit(&reg5);
  58
  59        CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
  60
  61        CPLD_WRITE(cfg_rcw_src1, reg5);
  62        CPLD_WRITE(cfg_rcw_src2, reg6);
  63
  64        CPLD_WRITE(vbank, 0);
  65
  66        CPLD_WRITE(system_rst, 1);
  67}
  68
  69void cpld_set_nand(void)
  70{
  71        u16 reg = CPLD_CFG_RCW_SRC_NAND;
  72
  73        if (CPLD_READ(cpld_ver) > 0x2)
  74                reg = CPLD_CFG_RCW_SRC_NAND_4K;
  75
  76        u8 reg5 = (u8)(reg >> 1);
  77        u8 reg6 = (u8)(reg & 1);
  78
  79        cpld_rev_bit(&reg5);
  80
  81        CPLD_WRITE(soft_mux_on, 1);
  82
  83        CPLD_WRITE(cfg_rcw_src1, reg5);
  84        CPLD_WRITE(cfg_rcw_src2, reg6);
  85
  86        CPLD_WRITE(system_rst, 1);
  87}
  88
  89void cpld_set_sd(void)
  90{
  91        u16 reg = CPLD_CFG_RCW_SRC_SD;
  92        u8 reg5 = (u8)(reg >> 1);
  93        u8 reg6 = (u8)(reg & 1);
  94
  95        cpld_rev_bit(&reg5);
  96
  97        CPLD_WRITE(soft_mux_on, 1);
  98
  99        CPLD_WRITE(cfg_rcw_src1, reg5);
 100        CPLD_WRITE(cfg_rcw_src2, reg6);
 101
 102        CPLD_WRITE(system_rst, 1);
 103}
 104#ifdef DEBUG
 105static void cpld_dump_regs(void)
 106{
 107        printf("cpld_ver        = %x\n", CPLD_READ(cpld_ver));
 108        printf("cpld_ver_sub    = %x\n", CPLD_READ(cpld_ver_sub));
 109        printf("pcba_ver        = %x\n", CPLD_READ(pcba_ver));
 110        printf("soft_mux_on     = %x\n", CPLD_READ(soft_mux_on));
 111        printf("cfg_rcw_src1    = %x\n", CPLD_READ(cfg_rcw_src1));
 112        printf("cfg_rcw_src2    = %x\n", CPLD_READ(cfg_rcw_src2));
 113        printf("vbank           = %x\n", CPLD_READ(vbank));
 114        printf("sysclk_sel      = %x\n", CPLD_READ(sysclk_sel));
 115        printf("uart_sel        = %x\n", CPLD_READ(uart_sel));
 116        printf("sd1refclk_sel   = %x\n", CPLD_READ(sd1refclk_sel));
 117        printf("tdmclk_mux_sel  = %x\n", CPLD_READ(tdmclk_mux_sel));
 118        printf("sdhc_spics_sel  = %x\n", CPLD_READ(sdhc_spics_sel));
 119        printf("status_led      = %x\n", CPLD_READ(status_led));
 120        putc('\n');
 121}
 122#endif
 123
 124void cpld_rev_bit(unsigned char *value)
 125{
 126        u8 rev_val, val;
 127        int i;
 128
 129        val = *value;
 130        rev_val = val & 1;
 131        for (i = 1; i <= 7; i++) {
 132                val >>= 1;
 133                rev_val <<= 1;
 134                rev_val |= val & 1;
 135        }
 136
 137        *value = rev_val;
 138}
 139
 140int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 141{
 142        int rc = 0;
 143
 144        if (argc <= 1)
 145                return cmd_usage(cmdtp);
 146
 147        if (strcmp(argv[1], "reset") == 0) {
 148                if (strcmp(argv[2], "altbank") == 0)
 149                        cpld_set_altbank();
 150                else if (strcmp(argv[2], "nand") == 0)
 151                        cpld_set_nand();
 152                else if (strcmp(argv[2], "sd") == 0)
 153                        cpld_set_sd();
 154                else
 155                        cpld_set_defbank();
 156#ifdef DEBUG
 157        } else if (strcmp(argv[1], "dump") == 0) {
 158                cpld_dump_regs();
 159#endif
 160        } else {
 161                rc = cmd_usage(cmdtp);
 162        }
 163
 164        return rc;
 165}
 166
 167U_BOOT_CMD(
 168        cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
 169        "Reset the board or alternate bank",
 170        "reset: reset to default bank\n"
 171        "cpld reset altbank: reset to alternate bank\n"
 172        "cpld reset nand: reset to boot from NAND flash\n"
 173        "cpld reset sd: reset to boot from SD card\n"
 174#ifdef DEBUG
 175        "cpld dump - display the CPLD registers\n"
 176#endif
 177);
 178