1
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4
5
6#include <common.h>
7#include <clock_legacy.h>
8#include <display_options.h>
9#include <dm.h>
10#include <init.h>
11#include <asm/global_data.h>
12#include <dm/platform_data/serial_pl01x.h>
13#include <i2c.h>
14#include <malloc.h>
15#include <errno.h>
16#include <netdev.h>
17#include <fsl_ddr.h>
18#include <asm/io.h>
19#include <fdt_support.h>
20#include <linux/bitops.h>
21#include <linux/libfdt.h>
22#include <linux/delay.h>
23#include <fsl-mc/fsl_mc.h>
24#include <env_internal.h>
25#include <efi_loader.h>
26#include <asm/arch/mmu.h>
27#include <hwconfig.h>
28#include <asm/arch/clock.h>
29#include <asm/arch/config.h>
30#include <asm/arch/fsl_serdes.h>
31#include <asm/arch/soc.h>
32#include "../common/i2c_mux.h"
33
34#include "../common/qixis.h"
35#include "../common/vid.h"
36#include <fsl_immap.h>
37#include <asm/arch-fsl-layerscape/fsl_icid.h>
38#include "lx2160a.h"
39
40#ifdef CONFIG_EMC2305
41#include "../common/emc2305.h"
42#endif
43
44#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
45#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
46#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
47#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
48#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
49#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
50#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
51#define SDHC1_BASE_PMUX_DSPI 2
52#define SDHC2_BASE_PMUX_DSPI 2
53#define IIC5_PMUX_SPI3 3
54#endif
55
56DECLARE_GLOBAL_DATA_PTR;
57
58int board_early_init_f(void)
59{
60#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
61 i2c_early_init_f();
62#endif
63
64#ifdef CONFIG_EMC2305
65 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
66 emc2305_init(I2C_EMC2305_ADDR);
67 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
68 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
69#endif
70
71 fsl_lsch3_early_init_f();
72 return 0;
73}
74
75#ifdef CONFIG_OF_BOARD_FIXUP
76int board_fix_fdt(void *fdt)
77{
78 char *reg_names, *reg_name;
79 int names_len, old_name_len, new_name_len, remaining_names_len;
80 struct str_map {
81 char *old_str;
82 char *new_str;
83 } reg_names_map[] = {
84 { "ccsr", "dbi" },
85 { "pf_ctrl", "ctrl" }
86 };
87 int off = -1, i = 0;
88
89 if (IS_SVR_REV(get_svr(), 1, 0))
90 return 0;
91
92 fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") {
93 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
94 strlen("fsl,ls-pcie") + 1);
95
96 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
97 &names_len);
98 if (!reg_names)
99 continue;
100
101 reg_name = reg_names;
102 remaining_names_len = names_len - (reg_name - reg_names);
103 i = 0;
104 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
105 old_name_len = strlen(reg_names_map[i].old_str);
106 new_name_len = strlen(reg_names_map[i].new_str);
107 if (memcmp(reg_name, reg_names_map[i].old_str,
108 old_name_len) == 0) {
109
110
111
112 memcpy(reg_name + new_name_len,
113 reg_name + old_name_len,
114 remaining_names_len - old_name_len);
115
116 memcpy(reg_name, reg_names_map[i].new_str,
117 new_name_len);
118 names_len -= old_name_len;
119 names_len += new_name_len;
120 i++;
121 }
122
123 reg_name = memchr(reg_name, '\0', remaining_names_len);
124 if (!reg_name)
125 break;
126
127 reg_name += 1;
128
129 remaining_names_len = names_len -
130 (reg_name - reg_names);
131 }
132
133 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
134 }
135
136 return 0;
137}
138#endif
139
140#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
141void esdhc_dspi_status_fixup(void *blob)
142{
143 const char esdhc0_path[] = "/soc/esdhc@2140000";
144 const char esdhc1_path[] = "/soc/esdhc@2150000";
145 const char dspi0_path[] = "/soc/spi@2100000";
146 const char dspi1_path[] = "/soc/spi@2110000";
147 const char dspi2_path[] = "/soc/spi@2120000";
148
149 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
150 u32 sdhc1_base_pmux;
151 u32 sdhc2_base_pmux;
152 u32 iic5_pmux;
153
154
155
156
157 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
158 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
159 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
160
161 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
162 do_fixup_by_path(blob, dspi0_path, "status", "okay",
163 sizeof("okay"), 1);
164 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
165 sizeof("disabled"), 1);
166 } else {
167 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
168 sizeof("okay"), 1);
169 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
170 sizeof("disabled"), 1);
171 }
172
173
174
175
176 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
177 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
178 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
179
180 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
181 do_fixup_by_path(blob, dspi1_path, "status", "okay",
182 sizeof("okay"), 1);
183 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
184 sizeof("disabled"), 1);
185 } else {
186 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
187 sizeof("okay"), 1);
188 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
189 sizeof("disabled"), 1);
190 }
191
192
193 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
194 & FSL_CHASSIS3_IIC5_PMUX_MASK;
195 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
196
197 if (iic5_pmux == IIC5_PMUX_SPI3)
198 do_fixup_by_path(blob, dspi2_path, "status", "okay",
199 sizeof("okay"), 1);
200 else
201 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
202 sizeof("disabled"), 1);
203}
204#endif
205
206int esdhc_status_fixup(void *blob, const char *compat)
207{
208#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
209
210 esdhc_dspi_status_fixup(blob);
211#else
212
213 do_fixup_by_compat(blob, compat, "status", "okay",
214 sizeof("okay"), 1);
215#endif
216 return 0;
217}
218
219#if defined(CONFIG_VID)
220int i2c_multiplexer_select_vid_channel(u8 channel)
221{
222 return select_i2c_ch_pca9547(channel, 0);
223}
224
225int init_func_vid(void)
226{
227 int set_vid;
228
229 if (IS_SVR_REV(get_svr(), 1, 0))
230 set_vid = adjust_vdd(800);
231 else
232 set_vid = adjust_vdd(0);
233
234 if (set_vid < 0)
235 printf("core voltage not adjusted\n");
236
237 return 0;
238}
239#endif
240
241int checkboard(void)
242{
243 enum boot_src src = get_boot_src();
244 char buf[64];
245 u8 sw;
246#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
247 int clock;
248 static const char *const freq[] = {"100", "125", "156.25",
249 "161.13", "322.26", "", "", "",
250 "", "", "", "", "", "", "",
251 "100 separate SSCG"};
252#endif
253
254 cpu_name(buf);
255#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
256 printf("Board: %s-QDS, ", buf);
257#else
258 printf("Board: %s-RDB, ", buf);
259#endif
260
261 sw = QIXIS_READ(arch);
262 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
263
264 if (src == BOOT_SOURCE_SD_MMC) {
265 puts("SD\n");
266 } else if (src == BOOT_SOURCE_SD_MMC2) {
267 puts("eMMC\n");
268 } else {
269 sw = QIXIS_READ(brdcfg[0]);
270 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
271 switch (sw) {
272 case 0:
273 case 4:
274 puts("FlexSPI DEV#0\n");
275 break;
276 case 1:
277 puts("FlexSPI DEV#1\n");
278 break;
279 case 2:
280 case 3:
281 puts("FlexSPI EMU\n");
282 break;
283 default:
284 printf("invalid setting, xmap: %d\n", sw);
285 break;
286 }
287 }
288#if defined(CONFIG_TARGET_LX2160ARDB)
289 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
290
291 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
292 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
293 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
294#else
295 printf("FPGA: v%d (%s), build %d",
296 (int)QIXIS_READ(scver), qixis_read_tag(buf),
297 (int)qixis_read_minor());
298
299 printf(" on %s", qixis_read_time(buf));
300
301 puts("SERDES1 Reference : ");
302 sw = QIXIS_READ(brdcfg[2]);
303 clock = sw >> 4;
304 printf("Clock1 = %sMHz ", freq[clock]);
305#if defined(CONFIG_TARGET_LX2160AQDS)
306 clock = sw & 0x0f;
307 printf("Clock2 = %sMHz", freq[clock]);
308#endif
309 sw = QIXIS_READ(brdcfg[3]);
310 puts("\nSERDES2 Reference : ");
311 clock = sw >> 4;
312 printf("Clock1 = %sMHz ", freq[clock]);
313 clock = sw & 0x0f;
314 printf("Clock2 = %sMHz\n", freq[clock]);
315#if defined(CONFIG_TARGET_LX2160AQDS)
316 sw = QIXIS_READ(brdcfg[12]);
317 puts("SERDES3 Reference : ");
318 clock = sw >> 4;
319 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
320#endif
321#endif
322 return 0;
323}
324
325#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
326static void esdhc_adapter_card_ident(void)
327{
328 u8 card_id, val;
329
330 val = QIXIS_READ(sdhc1);
331 card_id = val & QIXIS_SDID_MASK;
332
333 switch (card_id) {
334 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
335
336 val &= ~QIXIS_SDHC1_S1V3;
337 QIXIS_WRITE(sdhc1, val);
338 mdelay(1);
339 val |= QIXIS_SDHC1_S1V3;
340 QIXIS_WRITE(sdhc1, val);
341
342 val = QIXIS_READ(brdcfg[11]);
343 val |= QIXIS_SDHC1_VS;
344 QIXIS_WRITE(brdcfg[11], val);
345 break;
346 default:
347 break;
348 }
349}
350
351int config_board_mux(void)
352{
353 u8 reg11, reg5, reg13;
354 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
355 u32 sdhc1_base_pmux;
356 u32 sdhc2_base_pmux;
357 u32 iic5_pmux;
358
359
360
361
362
363
364
365
366
367
368
369
370 reg5 = QIXIS_READ(brdcfg[5]);
371 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
372 QIXIS_WRITE(brdcfg[5], reg5);
373
374
375
376
377
378 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
379 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
380 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
381
382 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
383 reg11 = QIXIS_READ(brdcfg[11]);
384 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
385 QIXIS_WRITE(brdcfg[11], reg11);
386 } else {
387
388
389
390
391 reg11 = QIXIS_READ(brdcfg[11]);
392 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
393 QIXIS_WRITE(brdcfg[11], reg11);
394 }
395
396
397
398
399
400 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
401 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
402 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
403
404 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
405 reg13 = QIXIS_READ(brdcfg[13]);
406 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
407 QIXIS_WRITE(brdcfg[13], reg13);
408 } else {
409 reg13 = QIXIS_READ(brdcfg[13]);
410 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
411 QIXIS_WRITE(brdcfg[13], reg13);
412 }
413
414
415
416
417 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
418 & FSL_CHASSIS3_IIC5_PMUX_MASK;
419 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
420
421 if (iic5_pmux == IIC5_PMUX_SPI3) {
422
423 reg11 = QIXIS_READ(brdcfg[11]);
424 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
425 QIXIS_WRITE(brdcfg[11], reg11);
426
427
428
429
430
431 reg11 = QIXIS_READ(brdcfg[11]);
432 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
433 QIXIS_WRITE(brdcfg[11], reg11);
434 } else {
435
436
437
438
439
440 reg11 = QIXIS_READ(brdcfg[11]);
441 if ((reg11 & 0x30) != 0x30) {
442 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
443 QIXIS_WRITE(brdcfg[11], reg11);
444 }
445
446
447
448
449
450 reg11 = QIXIS_READ(brdcfg[11]);
451 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
452 QIXIS_WRITE(brdcfg[11], reg11);
453 }
454
455 return 0;
456}
457
458int board_early_init_r(void)
459{
460 esdhc_adapter_card_ident();
461 return 0;
462}
463#elif defined(CONFIG_TARGET_LX2160ARDB)
464int config_board_mux(void)
465{
466 u8 brdcfg;
467
468 brdcfg = QIXIS_READ(brdcfg[4]);
469
470
471
472
473
474
475
476
477
478 brdcfg |= BIT_MASK(5);
479 QIXIS_WRITE(brdcfg[4], brdcfg);
480
481 return 0;
482}
483#else
484int config_board_mux(void)
485{
486 return 0;
487}
488#endif
489
490unsigned long get_board_sys_clk(void)
491{
492#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
493 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
494
495 switch (sysclk_conf & 0x03) {
496 case QIXIS_SYSCLK_100:
497 return 100000000;
498 case QIXIS_SYSCLK_125:
499 return 125000000;
500 case QIXIS_SYSCLK_133:
501 return 133333333;
502 }
503 return 100000000;
504#else
505 return 100000000;
506#endif
507}
508
509unsigned long get_board_ddr_clk(void)
510{
511#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
512 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
513
514 switch ((ddrclk_conf & 0x30) >> 4) {
515 case QIXIS_DDRCLK_100:
516 return 100000000;
517 case QIXIS_DDRCLK_125:
518 return 125000000;
519 case QIXIS_DDRCLK_133:
520 return 133333333;
521 }
522 return 100000000;
523#else
524 return 100000000;
525#endif
526}
527
528int board_init(void)
529{
530#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
531 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
532#endif
533
534 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
535
536#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
537
538 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
539#endif
540
541#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
542 pci_init();
543#endif
544 return 0;
545}
546
547void detail_board_ddr_info(void)
548{
549 int i;
550 u64 ddr_size = 0;
551
552 puts("\nDDR ");
553 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
554 ddr_size += gd->bd->bi_dram[i].size;
555 print_size(ddr_size, "");
556 print_ddr_info(0);
557}
558
559#ifdef CONFIG_MISC_INIT_R
560int misc_init_r(void)
561{
562 config_board_mux();
563
564 return 0;
565}
566#endif
567
568#ifdef CONFIG_VID
569u16 soc_get_fuse_vid(int vid_index)
570{
571 static const u16 vdd[32] = {
572 8250,
573 7875,
574 7750,
575 0,
576 0,
577 0,
578 0,
579 0,
580 0,
581 0,
582 0,
583 0,
584 0,
585 0,
586 0,
587 0,
588 8000,
589 8125,
590 8250,
591 0,
592 8500,
593 0,
594 0,
595 0,
596 0,
597 0,
598 0,
599 0,
600 0,
601 0,
602 0,
603 0,
604 };
605
606 return vdd[vid_index];
607};
608#endif
609
610#ifdef CONFIG_FSL_MC_ENET
611
612void fdt_fixup_board_enet(void *fdt)
613{
614 int offset;
615
616 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
617
618 if (offset < 0)
619 offset = fdt_path_offset(fdt, "/fsl-mc");
620
621 if (offset < 0) {
622 printf("%s: fsl-mc node not found in device tree (error %d)\n",
623 __func__, offset);
624 return;
625 }
626
627 if (get_mc_boot_status() == 0 &&
628 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
629 fdt_status_okay(fdt, offset);
630 } else {
631 fdt_status_fail(fdt, offset);
632 }
633}
634
635void board_quiesce_devices(void)
636{
637 fsl_mc_ldpaa_exit(gd->bd);
638}
639#endif
640
641#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
642int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
643{
644 int err;
645 int noff;
646 int offset;
647 char channel_node_name[50];
648 char thermal_node_name[50];
649 u32 phandle;
650
651 snprintf(channel_node_name, sizeof(channel_node_name),
652 "i2c@%x", channel);
653 debug("channel_node_name = %s\n", channel_node_name);
654
655 snprintf(thermal_node_name, sizeof(thermal_node_name),
656 "temperature-sensor@%x", reg);
657 debug("thermal_node_name = %s\n", thermal_node_name);
658
659 err = fdt_increase_size(blob, 200);
660 if (err) {
661 printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
662 return err;
663 }
664
665 noff = fdt_subnode_offset(blob, mux_node, (const char *)
666 channel_node_name);
667 if (noff < 0) {
668
669 noff = fdt_add_subnode(blob, mux_node, channel_node_name);
670 if (noff < 0) {
671 printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
672 return err;
673 }
674 fdt_setprop_u32 (blob, noff, "#address-cells", 1);
675 fdt_setprop_u32 (blob, noff, "#size-cells", 0);
676 fdt_setprop_u32 (blob, noff, "reg", channel);
677 }
678
679
680 offset = fdt_add_subnode(blob, noff, thermal_node_name);
681 fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
682 strlen("nxp,sa56004") + 1);
683 fdt_setprop_u32 (blob, offset, "reg", reg);
684
685
686 noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
687 if (noff < 0) {
688 printf("%s : failed to get phandle\n", __func__);
689 return noff;
690 }
691 phandle = fdt_get_phandle(blob, noff);
692 fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
693
694 return 0;
695}
696
697void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
698{
699 int node;
700 int value;
701 int err;
702 int subnode;
703
704 fdt_for_each_subnode(subnode, blob, mux_node) {
705 value = fdtdec_get_uint(blob, subnode, "reg", -1);
706 if (value == channel) {
707
708 fdt_for_each_subnode(node, blob, subnode) {
709 value = fdtdec_get_uint(blob, node, "reg", -1);
710 err = fdt_node_check_compatible(blob, node,
711 "nxp,sa56004");
712 if (!err && value == reg) {
713 fdt_del_node(blob, node);
714 break;
715 }
716 }
717 }
718 }
719}
720
721void fdt_fixup_i2c_thermal_node(void *blob)
722{
723 int i2coffset;
724 int mux_node;
725 int reg;
726 int err;
727
728 i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
729 0x2000000);
730 if (i2coffset != -FDT_ERR_NOTFOUND) {
731 fdt_for_each_subnode(mux_node, blob, i2coffset) {
732 reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
733 err = fdt_node_check_compatible(blob, mux_node,
734 "nxp,pca9547");
735 if (!err && reg == 0x77) {
736 fdt_fixup_delete_thermal(blob, mux_node,
737 0x3, 0x4d);
738 err = fdt_fixup_add_thermal(blob, mux_node,
739 0x3, 0x48);
740 if (err)
741 printf("%s: Add thermal node failed\n",
742 __func__);
743 }
744 }
745 } else {
746 printf("%s: i2c node not found\n", __func__);
747 }
748}
749#endif
750
751#ifdef CONFIG_OF_BOARD_SETUP
752int ft_board_setup(void *blob, struct bd_info *bd)
753{
754 int i;
755 u16 mc_memory_bank = 0;
756
757 u64 *base;
758 u64 *size;
759 u64 mc_memory_base = 0;
760 u64 mc_memory_size = 0;
761 u16 total_memory_banks;
762 int err;
763#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
764 u8 board_rev;
765#endif
766
767 err = fdt_increase_size(blob, 512);
768 if (err) {
769 printf("%s fdt_increase_size: err=%s\n", __func__,
770 fdt_strerror(err));
771 return err;
772 }
773
774 ft_cpu_setup(blob, bd);
775
776 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
777
778 if (mc_memory_base != 0)
779 mc_memory_bank++;
780
781 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
782
783 base = calloc(total_memory_banks, sizeof(u64));
784 size = calloc(total_memory_banks, sizeof(u64));
785
786
787 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
788 base[i] = gd->bd->bi_dram[i].start;
789 size[i] = gd->bd->bi_dram[i].size;
790 }
791
792#ifdef CONFIG_RESV_RAM
793
794 if (gd->arch.resv_ram >= base[0] &&
795 gd->arch.resv_ram < base[0] + size[0])
796 size[0] = gd->arch.resv_ram - base[0];
797 else if (gd->arch.resv_ram >= base[1] &&
798 gd->arch.resv_ram < base[1] + size[1])
799 size[1] = gd->arch.resv_ram - base[1];
800 else if (gd->arch.resv_ram >= base[2] &&
801 gd->arch.resv_ram < base[2] + size[2])
802 size[2] = gd->arch.resv_ram - base[2];
803#endif
804
805 if (mc_memory_base != 0) {
806 for (i = 0; i <= total_memory_banks; i++) {
807 if (base[i] == 0 && size[i] == 0) {
808 base[i] = mc_memory_base;
809 size[i] = mc_memory_size;
810 break;
811 }
812 }
813 }
814
815 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
816
817#ifdef CONFIG_USB_HOST
818 fsl_fdt_fixup_dr_usb(blob, bd);
819#endif
820
821#ifdef CONFIG_FSL_MC_ENET
822 fdt_fsl_mc_fixup_iommu_map_entry(blob);
823 fdt_fixup_board_enet(blob);
824#endif
825 fdt_fixup_icid(blob);
826
827#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
828 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
829 if (board_rev == 'C')
830 fdt_fixup_i2c_thermal_node(blob);
831#endif
832
833 return 0;
834}
835#endif
836
837void qixis_dump_switch(void)
838{
839 int i, nr_of_cfgsw;
840
841 QIXIS_WRITE(cms[0], 0x00);
842 nr_of_cfgsw = QIXIS_READ(cms[1]);
843
844 puts("DIP switch settings dump:\n");
845 for (i = 1; i <= nr_of_cfgsw; i++) {
846 QIXIS_WRITE(cms[0], i);
847 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
848 }
849}
850
