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7#include <common.h>
8#include <command.h>
9#include <dm.h>
10#include <init.h>
11#include <miiphy.h>
12#include <net.h>
13#include <tpm-v1.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <asm/arch/cpu.h>
17#include <asm-generic/gpio.h>
18#include <linux/delay.h>
19
20#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
21#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
22
23#include "keyprogram.h"
24#include "dt_helpers.h"
25#include "hydra.h"
26#include "ihs_phys.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
31#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
32
33#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
34#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
35#define DB_GP_88F68XX_GPP_POL_LOW 0x0
36#define DB_GP_88F68XX_GPP_POL_MID 0x0
37
38static int get_tpm(struct udevice **devp)
39{
40 int rc;
41
42 rc = uclass_first_device_err(UCLASS_TPM, devp);
43 if (rc) {
44 printf("Could not find TPM (ret=%d)\n", rc);
45 return CMD_RET_FAILURE;
46 }
47
48 return 0;
49}
50
51
52
53
54
55
56static struct mv_ddr_topology_map ddr_topology_map = {
57 DEBUG_LEVEL_ERROR,
58 0x1,
59
60 { { { {0x1, 0, 0, 0},
61 {0x1, 0, 0, 0},
62 {0x1, 0, 0, 0},
63 {0x1, 0, 0, 0},
64 {0x1, 0, 0, 0} },
65 SPEED_BIN_DDR_1600K,
66 MV_DDR_DEV_WIDTH_16BIT,
67 MV_DDR_DIE_CAP_4GBIT,
68 MV_DDR_FREQ_533,
69 0, 0,
70 MV_DDR_TEMP_LOW,
71 MV_DDR_TIM_DEFAULT} },
72 BUS_MASK_32BIT,
73 MV_DDR_CFG_DEFAULT,
74 NOT_COMBINED,
75 { {0} },
76 {0}
77
78};
79
80static struct serdes_map serdes_topology_map[] = {
81 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
82 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
83
84 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
85 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
87 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
88};
89
90int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
91{
92 *serdes_map_array = serdes_topology_map;
93 *count = ARRAY_SIZE(serdes_topology_map);
94 return 0;
95}
96
97void spl_board_init(void)
98{
99#ifdef CONFIG_SPL_BUILD
100 uint k;
101 struct gpio_desc gpio = {};
102
103
104 setbits_32(MVEBU_REGISTER(0x18204), BIT(2));
105 mdelay(10);
106
107 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
108
109 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
110 dm_gpio_set_value(&gpio, 0);
111
112
113 mdelay(500);
114
115
116 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
117 }
118
119
120 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
121 for (k = 0; k < 20; ++k) {
122 if (dm_gpio_get_value(&gpio)) {
123 printf("FPGA done after %u rounds\n", k);
124 break;
125 }
126 mdelay(100);
127 }
128 }
129
130
131 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
132 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
133 dm_gpio_set_value(&gpio, 1);
134 }
135
136
137 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
138 for (k = 0; k < 2; ++k) {
139 if (!dm_gpio_get_value(&gpio))
140 break;
141 mdelay(100);
142 }
143 }
144#endif
145}
146
147struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
148{
149 return &ddr_topology_map;
150}
151
152int board_early_init_f(void)
153{
154#ifdef CONFIG_SPL_BUILD
155
156 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
157 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
158 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
159 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
160 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
161 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
162 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
163 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
164
165
166 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
167 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
168
169
170 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
171 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
172
173
174 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
175 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
176#endif
177
178 return 0;
179}
180
181int board_init(void)
182{
183
184 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
185
186 return 0;
187}
188
189#ifndef CONFIG_SPL_BUILD
190void init_host_phys(struct mii_dev *bus)
191{
192 uint k;
193
194 for (k = 0; k < 2; ++k) {
195 struct phy_device *phydev;
196
197 phydev = phy_find_by_mask(bus, 1 << k);
198
199 if (phydev) {
200 phydev->interface = PHY_INTERFACE_MODE_SGMII;
201 phy_config(phydev);
202 }
203 }
204}
205
206int ccdc_eth_init(void)
207{
208 uint k;
209 uint octo_phy_mask = 0;
210 int ret;
211 struct mii_dev *bus;
212
213
214 bus = miiphy_get_dev_by_name("ethernet@34000");
215
216 if (bus)
217 init_host_phys(bus);
218
219 bus = miiphy_get_dev_by_name("ethernet@70000");
220
221 if (bus)
222 init_host_phys(bus);
223
224
225 octo_phy_mask = calculate_octo_phy_mask();
226
227 printf("IHS PHYS: %08x", octo_phy_mask);
228
229 ret = init_octo_phys(octo_phy_mask);
230
231 if (ret)
232 return ret;
233
234 printf("\n");
235
236 if (!get_fpga()) {
237 puts("fpga was NULL\n");
238 return 1;
239 }
240
241
242 for (k = 0; k < 80; ++k)
243 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
244
245 udelay(100);
246
247 for (k = 0; k < 80; ++k)
248 writel(0, get_fpga()->qsgmii_port_state[k]);
249 return 0;
250}
251
252#endif
253
254int board_late_init(void)
255{
256#ifndef CONFIG_SPL_BUILD
257 hydra_initialize();
258#endif
259 return 0;
260}
261
262int board_fix_fdt(void *rw_fdt_blob)
263{
264 struct udevice *bus = NULL;
265 uint k;
266 char name[64];
267 int err;
268
269 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
270
271 if (err) {
272 printf("Could not get I2C bus.\n");
273 return err;
274 }
275
276 for (k = 0x21; k <= 0x26; k++) {
277 snprintf(name, 64,
278 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
279
280 if (!dm_i2c_simple_probe(bus, k))
281 fdt_disable_by_ofname(rw_fdt_blob, name);
282 }
283
284 return 0;
285}
286
287int last_stage_init(void)
288{
289 struct udevice *tpm;
290 int ret;
291
292#ifndef CONFIG_SPL_BUILD
293 ccdc_eth_init();
294#endif
295 ret = get_tpm(&tpm);
296 if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) ||
297 tpm1_continue_self_test(tpm)) {
298 return 1;
299 }
300
301 mdelay(37);
302
303 flush_keys(tpm);
304 load_and_run_keyprog(tpm);
305
306 return 0;
307}
308