LXR uboot/board/synopsys/axs10x/axs10x.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   4 */
   5
   6#include <common.h>
   7#include <cpu_func.h>
   8#include <dwmmc.h>
   9#include <init.h>
  10#include <malloc.h>
  11#include <asm/arcregs.h>
  12#include <asm/global_data.h>
  13#include "axs10x.h"
  14#include <asm/cache.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18#define AXS_MB_CREG     0xE0011000
  19
  20int board_early_init_f(void)
  21{
  22        if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
  23                gd->board_type = AXS_MB_V3;
  24        else
  25                gd->board_type = AXS_MB_V2;
  26
  27        return 0;
  28}
  29
  30#ifdef CONFIG_ISA_ARCV2
  31
  32void board_jump_and_run(ulong entry, int zero, int arch, uint params)
  33{
  34        void (*kernel_entry)(int zero, int arch, uint params);
  35
  36        kernel_entry = (void (*)(int, int, uint))entry;
  37
  38        smp_set_core_boot_addr(entry, -1);
  39        smp_kick_all_cpus();
  40        kernel_entry(zero, arch, params);
  41}
  42
  43#define RESET_VECTOR_ADDR       0x0
  44
  45void smp_set_core_boot_addr(unsigned long addr, int corenr)
  46{
  47        /* All cores have reset vector pointing to 0 */
  48        writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
  49
  50        /* Make sure other cores see written value in memory */
  51        flush_dcache_all();
  52}
  53
  54void smp_kick_all_cpus(void)
  55{
  56/* CPU start CREG */
  57#define AXC003_CREG_CPU_START   0xF0001400
  58/* Bits positions in CPU start CREG */
  59#define BITS_START      0
  60#define BITS_START_MODE 4
  61#define BITS_CORE_SEL   9
  62
  63/*
  64 * In axs103 v1.1 START bits semantics has changed quite a bit.
  65 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
  66 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
  67 * for each core:
  68 *     bit 0: Core 0 (master)
  69 *     bit 1: Core 1 (slave)
  70 */
  71#define BITS_START_CORE1        1
  72
  73#define ARCVER_HS38_3_0 0x53
  74
  75        int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
  76        int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
  77
  78        if (core_family < ARCVER_HS38_3_0) {
  79                cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
  80                cmd &= ~(1 << BITS_START_MODE);
  81        } else {
  82                cmd |= (1 << BITS_START_CORE1);
  83        }
  84        writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
  85}
  86#endif
  87
  88int checkboard(void)
  89{
  90        printf("Board: ARC Software Development Platform AXS%s\n",
  91             is_isa_arcv2() ? "103" : "101");
  92
  93        return 0;
  94};
  95