LXR uboot/board/ti/ti816x/evm.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * evm.c
   4 *
   5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   6 * Antoine Tenart, <atenart@adeneo-embedded.com>
   7 */
   8
   9#include <common.h>
  10#include <env.h>
  11#include <init.h>
  12#include <net.h>
  13#include <spl.h>
  14#include <asm/cache.h>
  15#include <asm/global_data.h>
  16#include <asm/io.h>
  17#include <asm/arch/clock.h>
  18#include <asm/arch/cpu.h>
  19#include <asm/arch/ddr_defs.h>
  20#include <asm/arch/hardware.h>
  21#include <asm/arch/sys_proto.h>
  22#include <asm/arch/mmc_host_def.h>
  23#include <asm/arch/mem.h>
  24#include <asm/arch/mux.h>
  25
  26DECLARE_GLOBAL_DATA_PTR;
  27
  28int board_init(void)
  29{
  30        gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
  31#if defined(CONFIG_MTD_RAW_NAND)
  32        gpmc_init();
  33#endif
  34        return 0;
  35}
  36
  37int board_eth_init(struct bd_info *bis)
  38{
  39        uint8_t mac_addr[6];
  40        uint32_t mac_hi, mac_lo;
  41        struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42
  43        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  44                printf("<ethaddr> not set. Reading from E-fuse\n");
  45                /* try reading mac address from efuse */
  46                mac_lo = readl(&cdev->macid0l);
  47                mac_hi = readl(&cdev->macid0h);
  48                mac_addr[0] = mac_hi & 0xFF;
  49                mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  50                mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  51                mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  52                mac_addr[4] = mac_lo & 0xFF;
  53                mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  54
  55                if (is_valid_ethaddr(mac_addr))
  56                        eth_env_set_enetaddr("ethaddr", mac_addr);
  57                else
  58                        printf("Unable to read MAC address. Set <ethaddr>\n");
  59        }
  60
  61        return 0;
  62}
  63
  64#ifdef CONFIG_SPL_BUILD
  65static struct module_pin_mux mmc_pin_mux[] = {
  66        { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  67        { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  68        { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  69        { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  70        { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  71        { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  72        { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  73        { -1 },
  74};
  75
  76void set_uart_mux_conf(void) {}
  77
  78void set_mux_conf_regs(void)
  79{
  80        configure_module_pin_mux(mmc_pin_mux);
  81}
  82
  83/*
  84 * EMIF Paramters.  Refer the EMIF register documentation and the
  85 * memory datasheet for details.  This is for 796 MHz.
  86 */
  87#define EMIF_TIM1   0x1779C9FE
  88#define EMIF_TIM2   0x50608074
  89#define EMIF_TIM3   0x009F857F
  90#define EMIF_SDREF  0x10001841
  91#define EMIF_SDCFG  0x62A73832
  92#define EMIF_PHYCFG 0x00000110
  93static const struct emif_regs ddr3_emif_regs = {
  94        .sdram_config           = EMIF_SDCFG,
  95        .ref_ctrl               = EMIF_SDREF,
  96        .sdram_tim1             = EMIF_TIM1,
  97        .sdram_tim2             = EMIF_TIM2,
  98        .sdram_tim3             = EMIF_TIM3,
  99        .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 100};
 101
 102static const struct cmd_control ddr3_ctrl = {
 103        .cmd0csratio    = 0x100,
 104        .cmd0iclkout    = 0x001,
 105        .cmd1csratio    = 0x100,
 106        .cmd1iclkout    = 0x001,
 107        .cmd2csratio    = 0x100,
 108        .cmd2iclkout    = 0x001,
 109};
 110
 111/* These values are obtained from the CCS app */
 112#define RD_DQS_GATE     (0x1B3)
 113#define RD_DQS          (0x35)
 114#define WR_DQS          (0x93)
 115static struct ddr_data ddr3_data = {
 116        .datardsratio0          = ((RD_DQS<<10) | (RD_DQS<<0)),
 117        .datawdsratio0          = ((WR_DQS<<10) | (WR_DQS<<0)),
 118        .datawiratio0           = ((0x20<<10) | 0x20<<0),
 119        .datagiratio0           = ((0x20<<10) | 0x20<<0),
 120        .datafwsratio0          = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 121        .datawrsratio0          = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 122};
 123
 124static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
 125        .dmm_lisa_map_0 = 0x00000000,
 126        .dmm_lisa_map_1 = 0x00000000,
 127        .dmm_lisa_map_2 = 0x80640300,
 128        .dmm_lisa_map_3 = 0xC0640320,
 129};
 130
 131void sdram_init(void)
 132{
 133        /*
 134         * Pass in our DDR3 config information and that we have 2 EMIFs to
 135         * configure.
 136         */
 137        config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
 138                        &evm_lisa_map_regs, 2);
 139}
 140#endif /* CONFIG_SPL_BUILD */
 141