LXR uboot/drivers/ata/sata

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4 * Copyright 2019 NXP
   5 * Author: Tang Yuantian <b29983@freescale.com>
   6 */
   7
   8#ifndef SATA_SIL3132_H
   9#define SATA_SIL3132_H
  10
  11#define READ_CMD        0
  12#define WRITE_CMD       1
  13
  14/*
  15 * SATA device driver struct for each dev
  16 */
  17struct sil_sata {
  18        char    name[12];
  19        void    *port;  /* the port base address */
  20        int             lba48;
  21        u16             pio;
  22        u16             mwdma;
  23        u16             udma;
  24        struct udevice  *devno;
  25        int             wcache;
  26        int             flush;
  27        int             flush_ext;
  28        int             id;
  29};
  30
  31/* sata info for each controller */
  32struct sata_info {
  33        ulong iobase[3];
  34        pci_dev_t devno;
  35        int portbase;
  36        int maxport;
  37};
  38
  39/*
  40 * Scatter gather entry (SGE),MUST 8 bytes aligned
  41 */
  42struct sil_sge {
  43        __le64 addr;
  44        __le32 cnt;
  45        __le32 flags;
  46} __attribute__ ((aligned(8), packed));
  47
  48/*
  49 * Port request block, MUST 8 bytes aligned
  50 */
  51struct sil_prb {
  52        __le16 ctrl;
  53        __le16 prot;
  54        __le32 rx_cnt;
  55        struct sata_fis_h2d fis;
  56} __attribute__ ((aligned(8), packed));
  57
  58struct sil_cmd_block {
  59        struct sil_prb prb;
  60        struct sil_sge sge;
  61};
  62
  63enum {
  64        HOST_SLOT_STAT          = 0x00, /* 32 bit slot stat * 4 */
  65        HOST_CTRL               = 0x40,
  66        HOST_IRQ_STAT           = 0x44,
  67        HOST_PHY_CFG            = 0x48,
  68        HOST_BIST_CTRL          = 0x50,
  69        HOST_BIST_PTRN          = 0x54,
  70        HOST_BIST_STAT          = 0x58,
  71        HOST_MEM_BIST_STAT      = 0x5c,
  72        HOST_FLASH_CMD          = 0x70,
  73                /* 8 bit regs */
  74        HOST_FLASH_DATA         = 0x74,
  75        HOST_TRANSITION_DETECT  = 0x75,
  76        HOST_GPIO_CTRL          = 0x76,
  77        HOST_I2C_ADDR           = 0x78, /* 32 bit */
  78        HOST_I2C_DATA           = 0x7c,
  79        HOST_I2C_XFER_CNT       = 0x7e,
  80        HOST_I2C_CTRL           = 0x7f,
  81
  82        /* HOST_SLOT_STAT bits */
  83        HOST_SSTAT_ATTN         = (1 << 31),
  84
  85        /* HOST_CTRL bits */
  86        HOST_CTRL_M66EN         = (1 << 16), /* M66EN PCI bus signal */
  87        HOST_CTRL_TRDY          = (1 << 17), /* latched PCI TRDY */
  88        HOST_CTRL_STOP          = (1 << 18), /* latched PCI STOP */
  89        HOST_CTRL_DEVSEL        = (1 << 19), /* latched PCI DEVSEL */
  90        HOST_CTRL_REQ64         = (1 << 20), /* latched PCI REQ64 */
  91        HOST_CTRL_GLOBAL_RST    = (1 << 31), /* global reset */
  92
  93        /*
  94         * Port registers
  95         * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
  96         */
  97        PORT_REGS_SIZE          = 0x2000,
  98
  99        PORT_LRAM               = 0x0000, /* 31 LRAM slots and PMP regs */
 100        PORT_LRAM_SLOT_SZ       = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
 101
 102        PORT_PMP                = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
 103        PORT_PMP_STATUS         = 0x0000, /* port device status offset */
 104        PORT_PMP_QACTIVE        = 0x0004, /* port device QActive offset */
 105        PORT_PMP_SIZE           = 0x0008, /* 8 bytes per PMP */
 106
 107        /* 32 bit regs */
 108        PORT_CTRL_STAT          = 0x1000, /* write: ctrl-set, read: stat */
 109        PORT_CTRL_CLR           = 0x1004, /* write: ctrl-clear */
 110        PORT_IRQ_STAT           = 0x1008, /* high: status, low: interrupt */
 111        PORT_IRQ_ENABLE_SET     = 0x1010, /* write: enable-set */
 112        PORT_IRQ_ENABLE_CLR     = 0x1014, /* write: enable-clear */
 113        PORT_ACTIVATE_UPPER_ADDR = 0x101c,
 114        PORT_EXEC_FIFO          = 0x1020, /* command execution fifo */
 115        PORT_CMD_ERR            = 0x1024, /* command error number */
 116        PORT_FIS_CFG            = 0x1028,
 117        PORT_FIFO_THRES         = 0x102c,
 118
 119        /* 16 bit regs */
 120        PORT_DECODE_ERR_CNT     = 0x1040,
 121        PORT_DECODE_ERR_THRESH  = 0x1042,
 122        PORT_CRC_ERR_CNT        = 0x1044,
 123        PORT_CRC_ERR_THRESH     = 0x1046,
 124        PORT_HSHK_ERR_CNT       = 0x1048,
 125        PORT_HSHK_ERR_THRESH    = 0x104a,
 126
 127        /* 32 bit regs */
 128        PORT_PHY_CFG            = 0x1050,
 129        PORT_SLOT_STAT          = 0x1800,
 130        PORT_CMD_ACTIVATE       = 0x1c00, /* 64 bit cmd activate * 31 */
 131        PORT_CONTEXT            = 0x1e04,
 132        PORT_EXEC_DIAG          = 0x1e00, /* 32bit exec diag * 16 */
 133        PORT_PSD_DIAG           = 0x1e40, /* 32bit psd diag * 16 */
 134        PORT_SCONTROL           = 0x1f00,
 135        PORT_SSTATUS            = 0x1f04,
 136        PORT_SERROR             = 0x1f08,
 137        PORT_SACTIVE            = 0x1f0c,
 138
 139        /* PORT_CTRL_STAT bits */
 140        PORT_CS_PORT_RST        = (1 << 0), /* port reset */
 141        PORT_CS_DEV_RST         = (1 << 1), /* device reset */
 142        PORT_CS_INIT            = (1 << 2), /* port initialize */
 143        PORT_CS_IRQ_WOC         = (1 << 3), /* interrupt write one to clear */
 144        PORT_CS_CDB16           = (1 << 5), /* 0=12b cdb, 1=16b cdb */
 145        PORT_CS_PMP_RESUME      = (1 << 6), /* PMP resume */
 146        PORT_CS_32BIT_ACTV      = (1 << 10), /* 32-bit activation */
 147        PORT_CS_PMP_EN          = (1 << 13), /* port multiplier enable */
 148        PORT_CS_RDY             = (1 << 31), /* port ready to accept commands */
 149
 150        /* PORT_IRQ_STAT/ENABLE_SET/CLR */
 151        /* bits[11:0] are masked */
 152        PORT_IRQ_COMPLETE       = (1 << 0), /* command(s) completed */
 153        PORT_IRQ_ERROR          = (1 << 1), /* command execution error */
 154        PORT_IRQ_PORTRDY_CHG    = (1 << 2), /* port ready change */
 155        PORT_IRQ_PWR_CHG        = (1 << 3), /* power management change */
 156        PORT_IRQ_PHYRDY_CHG     = (1 << 4), /* PHY ready change */
 157        PORT_IRQ_COMWAKE        = (1 << 5), /* COMWAKE received */
 158        PORT_IRQ_UNK_FIS        = (1 << 6), /* unknown FIS received */
 159        PORT_IRQ_DEV_XCHG       = (1 << 7), /* device exchanged */
 160        PORT_IRQ_8B10B          = (1 << 8), /* 8b/10b decode error threshold */
 161        PORT_IRQ_CRC            = (1 << 9), /* CRC error threshold */
 162        PORT_IRQ_HANDSHAKE      = (1 << 10), /* handshake error threshold */
 163        PORT_IRQ_SDB_NOTIFY     = (1 << 11), /* SDB notify received */
 164
 165        DEF_PORT_IRQ            = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
 166                                  PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
 167                                  PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
 168
 169        /* bits[27:16] are unmasked (raw) */
 170        PORT_IRQ_RAW_SHIFT      = 16,
 171        PORT_IRQ_MASKED_MASK    = 0x7ff,
 172        PORT_IRQ_RAW_MASK       = (0x7ff << PORT_IRQ_RAW_SHIFT),
 173
 174        /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
 175        PORT_IRQ_STEER_SHIFT    = 30,
 176        PORT_IRQ_STEER_MASK     = (3 << PORT_IRQ_STEER_SHIFT),
 177
 178        /* PORT_CMD_ERR constants */
 179        PORT_CERR_DEV           = 1, /* Error bit in D2H Register FIS */
 180        PORT_CERR_SDB           = 2, /* Error bit in SDB FIS */
 181        PORT_CERR_DATA          = 3, /* Error in data FIS not detected by dev */
 182        PORT_CERR_SEND          = 4, /* Initial cmd FIS transmission failure */
 183        PORT_CERR_INCONSISTENT  = 5, /* Protocol mismatch */
 184        PORT_CERR_DIRECTION     = 6, /* Data direction mismatch */
 185        PORT_CERR_UNDERRUN      = 7, /* Ran out of SGEs while writing */
 186        PORT_CERR_OVERRUN       = 8, /* Ran out of SGEs while reading */
 187
 188        /* bits of PRB control field */
 189        PRB_CTRL_PROTOCOL       = (1 << 0), /* override def. ATA protocol */
 190        PRB_CTRL_PACKET_READ    = (1 << 4), /* PACKET cmd read */
 191        PRB_CTRL_PACKET_WRITE   = (1 << 5), /* PACKET cmd write */
 192        PRB_CTRL_NIEN           = (1 << 6), /* Mask completion irq */
 193        PRB_CTRL_SRST           = (1 << 7), /* Soft reset request (ign BSY?) */
 194
 195        /* PRB protocol field */
 196        PRB_PROT_PACKET         = (1 << 0),
 197        PRB_PROT_TCQ            = (1 << 1),
 198        PRB_PROT_NCQ            = (1 << 2),
 199        PRB_PROT_READ           = (1 << 3),
 200        PRB_PROT_WRITE          = (1 << 4),
 201        PRB_PROT_TRANSPARENT    = (1 << 5),
 202
 203        /*
 204         * Other constants
 205         */
 206        SGE_TRM                 = (1 << 31), /* Last SGE in chain */
 207        SGE_LNK                 = (1 << 30), /* linked list
 208                                                Points to SGT, not SGE */
 209        SGE_DRD                 = (1 << 29), /* discard data read (/dev/null)
 210                                                data address ignored */
 211
 212        CMD_ERR         = 0x21,
 213};
 214
 215#define ATA_MAX_PORTS           32
 216struct sil_sata_priv {
 217        int             port_num;
 218        struct sil_sata *sil_sata_desc[ATA_MAX_PORTS];
 219};
 220
 221#endif
 222