LXR uboot/drivers/ddr/fsl/mpc85xx_ddr

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <asm/io.h>
   8#include <asm/processor.h>
   9#include <fsl_ddr_sdram.h>
  10#include <linux/delay.h>
  11
  12#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  13#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  14#endif
  15
  16void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  17                             unsigned int ctrl_num, int step)
  18{
  19        unsigned int i;
  20        struct ccsr_ddr __iomem *ddr =
  21                (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
  22
  23#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
  24        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  25        uint svr;
  26#endif
  27
  28        if (ctrl_num) {
  29                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  30                return;
  31        }
  32
  33#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  34        /*
  35         * Set the DDR IO receiver to an acceptable bias point.
  36         * Fixed in Rev 2.1.
  37         */
  38        svr = get_svr();
  39        if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
  40                if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
  41                   SDRAM_CFG_SDRAM_TYPE_DDR2)
  42                        out_be32(&gur->ddrioovcr, 0x90000000);
  43                else
  44                        out_be32(&gur->ddrioovcr, 0xA8000000);
  45        }
  46#endif
  47
  48        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  49                if (i == 0) {
  50                        out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  51                        out_be32(&ddr->cs0_config, regs->cs[i].config);
  52
  53                } else if (i == 1) {
  54                        out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  55                        out_be32(&ddr->cs1_config, regs->cs[i].config);
  56
  57                } else if (i == 2) {
  58                        out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  59                        out_be32(&ddr->cs2_config, regs->cs[i].config);
  60
  61                } else if (i == 3) {
  62                        out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  63                        out_be32(&ddr->cs3_config, regs->cs[i].config);
  64                }
  65        }
  66
  67        out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  68        out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  69        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  70        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  71        out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  72        out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  73        out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  74        out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  75        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  76        out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  77        out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  78        out_be32(&ddr->init_addr, regs->ddr_init_addr);
  79        out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  80
  81        /*
  82         * 200 painful micro-seconds must elapse between
  83         * the DDR clock setup and the DDR config enable.
  84         */
  85        udelay(200);
  86        asm volatile("sync;isync");
  87
  88        out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  89
  90        /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
  91        while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
  92                udelay(10000);          /* throttle polling rate */
  93        }
  94}
  95