LXR uboot/drivers/ddr/marvell/axp/ddr3_axp

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) Marvell International Ltd. and its affiliates
   4 */
   5
   6#ifndef __AXP_VARS_H
   7#define __AXP_VARS_H
   8
   9#include "ddr3_axp_config.h"
  10#include "ddr3_axp_mc_static.h"
  11#include "ddr3_axp_training_static.h"
  12
  13MV_DRAM_MODES ddr_modes[MV_DDR3_MODES_NUMBER] = {
  14        /*      Conf name               CPUFreq         FabFreq         Chip ID Chip/Board      MC regs                 Training Values */
  15        /* db board values: */
  16        {"db_800-400", 0xA, 0x5, 0x0, A0, ddr3_A0_db_400, NULL},
  17        {"db_1200-300", 0x2, 0xC, 0x0, A0, ddr3_A0_db_400, NULL},
  18        {"db_1200-600", 0x2, 0x5, 0x0, A0, NULL, NULL},
  19        {"db_1333-667", 0x3, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_667},
  20        {"db_1600-800", 0xB, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_800},
  21        {"amc_1333-667", 0x3, 0x5, 0x0, A0_AMC, ddr3_A0_AMC_667, NULL},
  22        {"db_667-667", 0x9, 0x13, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
  23        {"db_800-400", 0xA, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
  24        {"db_1066-533", 0x1, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_533},
  25        {"db_1200-300", 0x2, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_667},
  26        {"db_1200-600", 0x2, 0x5, 0x0, Z1, ddr3_Z1_db_600, NULL},
  27        {"db_1333-333", 0x3, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
  28        {"db_1333-667", 0x3, 0x5, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
  29        /* pcac board values (Z1 device): */
  30        {"pcac_1200-600", 0x2, 0x5, 0x0, Z1_PCAC, ddr3_Z1_db_600,
  31         ddr3_pcac_600},
  32        /* rd board values (Z1 device): */
  33        {"rd_667_0", 0x3, 0x5, 0x0, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_0},
  34        {"rd_667_1", 0x3, 0x5, 0x1, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_1},
  35        {"rd_667_2", 0x3, 0x5, 0x2, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_2},
  36        {"rd_667_3", 0x3, 0x5, 0x3, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_3}
  37};
  38
  39/* ODT settings - if needed update the following tables: (ODT_OPT - represents the CS configuration bitmap) */
  40
  41u16 odt_static[ODT_OPT][MAX_CS] = {     /*        NearEnd/FarEnd */
  42        {0, 0, 0, 0},           /* 0000         0/0 - Not supported */
  43        {ODT40, 0, 0, 0},       /* 0001         0/1 */
  44        {0, 0, 0, 0},           /* 0010         0/0 - Not supported */
  45        {ODT40, ODT40, 0, 0},   /* 0011         0/2 */
  46        {0, 0, ODT40, 0},       /* 0100         1/0 */
  47        {ODT30, 0, ODT30, 0},   /* 0101         1/1 */
  48        {0, 0, 0, 0},           /* 0110         0/0 - Not supported */
  49        {ODT120, ODT20, ODT20, 0},      /* 0111         1/2 */
  50        {0, 0, 0, 0},           /* 1000         0/0 - Not supported */
  51        {0, 0, 0, 0},           /* 1001         0/0 - Not supported */
  52        {0, 0, 0, 0},           /* 1010         0/0 - Not supported */
  53        {0, 0, 0, 0},           /* 1011         0/0 - Not supported */
  54        {0, 0, ODT40, 0},       /* 1100         2/0 */
  55        {ODT20, 0, ODT120, ODT20},      /* 1101         2/1 */
  56        {0, 0, 0, 0},           /* 1110         0/0 - Not supported */
  57        {ODT120, ODT30, ODT120, ODT30}  /* 1111         2/2 */
  58};
  59
  60u16 odt_dynamic[ODT_OPT][MAX_CS] = {    /*        NearEnd/FarEnd */
  61        {0, 0, 0, 0},           /* 0000         0/0 */
  62        {0, 0, 0, 0},           /* 0001         0/1 */
  63        {0, 0, 0, 0},           /* 0010         0/0 - Not supported */
  64        {0, 0, 0, 0},           /* 0011         0/2 */
  65        {0, 0, 0, 0},           /* 0100         1/0 */
  66        {ODT120D, 0, ODT120D, 0},       /* 0101         1/1 */
  67        {0, 0, 0, 0},           /* 0110         0/0 - Not supported */
  68        {0, 0, ODT120D, 0},     /* 0111         1/2 */
  69        {0, 0, 0, 0},           /* 1000         0/0 - Not supported */
  70        {0, 0, 0, 0},           /* 1001         0/0 - Not supported */
  71        {0, 0, 0, 0},           /* 1010         0/0 - Not supported */
  72        {0, 0, 0, 0},           /* 1011         0/0 - Not supported */
  73        {0, 0, 0, 0},           /* 1100         2/0 */
  74        {ODT120D, 0, 0, 0},     /* 1101         2/1 */
  75        {0, 0, 0, 0},           /* 1110         0/0 - Not supported */
  76        {0, 0, 0, 0}            /* 1111         2/2 */
  77};
  78
  79u32 odt_config[ODT_OPT] = {
  80        0, 0x00010000, 0, 0x00030000, 0x04000000, 0x05050104, 0, 0x07430340, 0,
  81            0, 0, 0,
  82        0x30000, 0x1C0D100C, 0, 0x3CC330C0
  83};
  84
  85/*
  86 * User can manually set SPD values (in case SPD is not available on
  87 * DIMM/System).
  88 * SPD Values can simplify calculating the DUNIT registers values
  89 */
  90u8 spd_data[SPD_SIZE] = {
  91        /* AXP DB Board DIMM SPD Values - manually set */
  92        0x92, 0x10, 0x0B, 0x2, 0x3, 0x19, 0x0, 0x9, 0x09, 0x52, 0x1, 0x8, 0x0C,
  93        0x0, 0x7E, 0x0, 0x69, 0x78,
  94        0x69, 0x30, 0x69, 0x11, 0x20, 0x89, 0x0, 0x5, 0x3C, 0x3C, 0x0, 0xF0,
  95        0x82, 0x5, 0x80, 0x0, 0x0, 0x0,
  96        0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
  97        0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
  98        0x0, 0x0, 0x0, 0x0, 0x0F, 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
  99        0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 100        0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 101        0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 102        0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 103        0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 104        0x0, 0x80, 0x2C, 0x1, 0x10, 0x23, 0x35, 0x28, 0xEB, 0xCA, 0x19, 0x8F
 105};
 106
 107/*
 108 * Controller Specific configurations Starts Here - DO NOT MODIFY
 109 */
 110
 111/* Frequency - values are 1/HCLK in ps */
 112u32 cpu_fab_clk_to_hclk[FAB_OPT][CLK_CPU] =
 113/* CPU Frequency:
 114        1000    1066    1200    1333    1500    1666    1800    2000    600             667             800             1600    Fabric */
 115{
 116        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 117        {0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
 118        {0, 0, 0, 0, 0, 0, 0, 0, 0, 4500, 3750, 0},
 119        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 120        {0, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 121        {4000, 3750, 3333, 3000, 2666, 2400, 0, 0, 0, 0, 5000, 2500},
 122        {0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 0, 0},
 123        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 124        {2500, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 125        {0, 0, 5000, 0, 4000, 0, 0, 0, 0, 0, 0, 3750},
 126        {5000, 0, 0, 3750, 3333, 0, 0, 0, 0, 0, 0, 3125},
 127        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 128        {0, 0, 3330, 3000, 0, 0, 0, 0, 0, 0, 0, 2500},
 129        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3750},
 130        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 131        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 132        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 133        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 134        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 135        {0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
 136        {3000, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 3750, 0}
 137};
 138
 139u32 cpu_ddr_ratios[FAB_OPT][CLK_CPU] =
 140/* CPU Frequency:
 141        1000    1066    1200    1333    1500    1666    1800    2000    600             667             800             1600    Fabric */
 142{
 143        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 144        {0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, DDR_400, 0},
 145        {0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_444, DDR_533, 0},
 146        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 147        {0, 0, DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 148        {DDR_500, DDR_533, DDR_600, DDR_666, DDR_750, DDR_833, 0, 0, 0, 0,
 149         DDR_400, DDR_800},
 150        {0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, 0, 0},
 151        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 152        {DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 153        {0, 0, DDR_400, 0, DDR_500, 0, 0, 0, 0, 0, 0, DDR_533},
 154        {DDR_400, 0, 0, DDR_533, DDR_600, 0, 0, 0, 0, 0, 0, DDR_640},
 155        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 156        {0, 0, DDR_300, DDR_333, 0, 0, 0, 0, 0, 0, 0, DDR_400},
 157        {0, 0, 0, 0, 0, 0, DDR_600, DDR_666, 0, 0, 0, DDR_533},
 158        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 159        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 160        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 161        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 162        {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 163        {0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_666, DDR_800, 0},
 164        {DDR_666, 0, DDR_800, 0, 0, 0, 0, 0, 0, 0, DDR_533, 0}
 165};
 166
 167u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
 168/* DDR Frequency:
 169        100             300     360     400     444     500     533     600     666     750     800     833  */
 170{ {0xA, 3, 0, 3, 0, 2, 0, 0, 0, 0, 0, 0},       /*  1:1     CLK_CPU_1000  */
 171{0xB, 3, 0, 3, 0, 0, 2, 0, 0, 0, 0, 0}, /*  1:1     CLK_CPU_1066  */
 172{0xC, 4, 0, 3, 0, 0, 0, 2, 0, 0, 0, 0}, /*  1:1     CLK_CPU_1200  */
 173{0xD, 4, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0}, /*      1:1     CLK_CPU_1333  */
 174{0xF, 5, 0, 4, 0, 3, 0, 0, 0, 0, 0, 0}, /*      1:1     CLK_CPU_1500  */
 175{0x11, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1666  */
 176{0x12, 6, 5, 4, 0, 0, 0, 3, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1800  */
 177{0x14, 7, 0, 5, 0, 4, 0, 0, 3, 0, 0, 0},        /*      1:1     CLK_CPU_2000  */
 178{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /*      1:1 CLK_CPU_600   */
 179{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /*      1:1     CLK_CPU_667   */
 180{0x8, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /*      1:1 CLK_CPU_800   */
 181{0x10, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1 CLK_CPU_1600   */
 182{0x14, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0},        /*  1:1     CLK_CPU_1000 VCO_2000 */
 183{0x15, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0},        /*  1:1     CLK_CPU_1066 VCO_2133 */
 184{0x18, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0},        /*  1:1     CLK_CPU_1200 VCO_2400 */
 185{0x1A, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1333 VCO_2666 */
 186{0x1E, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1500 VCO_3000 */
 187{0x21, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1666 VCO_3333 */
 188{0x24, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0},        /*      1:1     CLK_CPU_1800 VCO_3600 */
 189{0x28, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0},       /*      1:1     CLK_CPU_2000 VCO_4000 */
 190{0xC, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0}, /*      1:1 CLK_CPU_600 VCO_1200 */
 191{0xD, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /*      1:1     CLK_CPU_667 VCO_1333 */
 192{0x10, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0},        /*  1:1 CLK_CPU_800 VCO_1600 */
 193{0x20, 10, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0}        /*      1:1 CLK_CPU_1600 VCO_3200 */
 194};
 195
 196u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
 197/* DDR Frequency:
 198                100     300     360     400     444     500     533     600     666     750     800     833  */
 199{ {0, 0, 0, 0, 0, 2, 0, 0, 3, 0, 0, 0}, /*      2:1     CLK_CPU_1000  */
 200{0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1066  */
 201{0, 0, 0, 3, 5, 0, 0, 2, 0, 0, 3, 3},   /*      2:1     CLK_CPU_1200  */
 202{0, 0, 0, 0, 0, 0, 5, 0, 2, 0, 3, 0},   /*      2:1     CLK_CPU_1333  */
 203{0, 0, 0, 0, 0, 3, 0, 5, 0, 2, 0, 0},   /*      2:1     CLK_CPU_1500  */
 204{0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 2},   /*      2:1     CLK_CPU_1666  */
 205{0, 0, 0, 0, 0, 0, 0, 3, 0, 5, 0, 0},   /*      2:1     CLK_CPU_1800  */
 206{0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 5},   /*      2:1     CLK_CPU_2000  */
 207{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_600   */
 208{0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0},   /*  2:1 CLK_CPU_667   */
 209{0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 1, 0},   /*      2:1 CLK_CPU_800   */
 210{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 2, 0},   /*      2:1 CLK_CPU_1600   */
 211{0, 0, 0, 5, 0, 0, 0, 0, 3, 0, 0, 0},   /*      2:1     CLK_CPU_1000 VCO_2000 */
 212{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1066 VCO_2133 */
 213{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0},   /*      2:1     CLK_CPU_1200 VCO_2400 */
 214{0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1333 VCO_2666 */
 215{0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1500 VCO_3000 */
 216{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1666 VCO_3333 */
 217{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_1800 VCO_3600 */
 218{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_2000 VCO_4000 */
 219{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},   /*      2:1     CLK_CPU_600 VCO_1200 */
 220{0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0},   /*  2:1 CLK_CPU_667 VCO_1333 */
 221{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0},   /*      2:1 CLK_CPU_800 VCO_1600 */
 222{0, 0, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0}    /*      2:1 CLK_CPU_1600 VCO_3200 */
 223};
 224
 225#endif /* __AXP_VARS_H */
 226