LXR uboot/drivers/gpio/at91

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
   4 *
   5 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
   6 *
   7 *  Copyright (C) 2005 HP Labs
   8 */
   9
  10#include <config.h>
  11#include <common.h>
  12#include <clk.h>
  13#include <dm.h>
  14#include <malloc.h>
  15#include <asm/io.h>
  16#include <linux/sizes.h>
  17#include <asm/gpio.h>
  18#include <asm/arch/hardware.h>
  19#include <asm/arch/at91_pio.h>
  20
  21#define GPIO_PER_BANK   32
  22
  23static struct at91_port *at91_pio_get_port(unsigned port)
  24{
  25        switch (port) {
  26        case AT91_PIO_PORTA:
  27                return (struct at91_port *)ATMEL_BASE_PIOA;
  28        case AT91_PIO_PORTB:
  29                return (struct at91_port *)ATMEL_BASE_PIOB;
  30        case AT91_PIO_PORTC:
  31                return (struct at91_port *)ATMEL_BASE_PIOC;
  32#if (ATMEL_PIO_PORTS > 3)
  33        case AT91_PIO_PORTD:
  34                return (struct at91_port *)ATMEL_BASE_PIOD;
  35#if (ATMEL_PIO_PORTS > 4)
  36        case AT91_PIO_PORTE:
  37                return (struct at91_port *)ATMEL_BASE_PIOE;
  38#endif
  39#endif
  40        default:
  41                printf("Error: at91_gpio: Fail to get PIO base!\n");
  42                return NULL;
  43        }
  44}
  45
  46static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
  47                                 int use_pullup)
  48{
  49        u32 mask;
  50
  51        mask = 1 << offset;
  52        if (use_pullup)
  53                writel(mask, &at91_port->puer);
  54        else
  55                writel(mask, &at91_port->pudr);
  56        writel(mask, &at91_port->per);
  57}
  58
  59int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  60{
  61        struct at91_port *at91_port = at91_pio_get_port(port);
  62
  63        if (at91_port && (pin < GPIO_PER_BANK))
  64                at91_set_port_pullup(at91_port, pin, use_pullup);
  65
  66        return 0;
  67}
  68
  69/*
  70 * mux the pin to the "GPIO" peripheral role.
  71 */
  72int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
  73{
  74        struct at91_port *at91_port = at91_pio_get_port(port);
  75        u32 mask;
  76
  77        if (at91_port && (pin < GPIO_PER_BANK)) {
  78                mask = 1 << pin;
  79                writel(mask, &at91_port->idr);
  80                at91_set_pio_pullup(port, pin, use_pullup);
  81                writel(mask, &at91_port->per);
  82        }
  83
  84        return 0;
  85}
  86
  87/*
  88 * mux the pin to the "A" internal peripheral role.
  89 */
  90int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  91{
  92        struct at91_port *at91_port = at91_pio_get_port(port);
  93        u32 mask;
  94
  95        if (at91_port && (pin < GPIO_PER_BANK)) {
  96                mask = 1 << pin;
  97                writel(mask, &at91_port->idr);
  98                at91_set_pio_pullup(port, pin, use_pullup);
  99                writel(mask, &at91_port->mux.pio2.asr);
 100                writel(mask, &at91_port->pdr);
 101        }
 102
 103        return 0;
 104}
 105
 106/*
 107 * mux the pin to the "B" internal peripheral role.
 108 */
 109int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
 110{
 111        struct at91_port *at91_port = at91_pio_get_port(port);
 112        u32 mask;
 113
 114        if (at91_port && (pin < GPIO_PER_BANK)) {
 115                mask = 1 << pin;
 116                writel(mask, &at91_port->idr);
 117                at91_set_pio_pullup(port, pin, use_pullup);
 118                writel(mask, &at91_port->mux.pio2.bsr);
 119                writel(mask, &at91_port->pdr);
 120        }
 121
 122        return 0;
 123}
 124
 125/*
 126 * mux the pin to the "A" internal peripheral role.
 127 */
 128int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
 129{
 130        struct at91_port *at91_port = at91_pio_get_port(port);
 131        u32 mask;
 132
 133        if (at91_port && (pin < GPIO_PER_BANK)) {
 134                mask = 1 << pin;
 135                writel(mask, &at91_port->idr);
 136                at91_set_pio_pullup(port, pin, use_pullup);
 137                writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
 138                       &at91_port->mux.pio3.abcdsr1);
 139                writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
 140                       &at91_port->mux.pio3.abcdsr2);
 141
 142                writel(mask, &at91_port->pdr);
 143        }
 144
 145        return 0;
 146}
 147
 148/*
 149 * mux the pin to the "B" internal peripheral role.
 150 */
 151int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
 152{
 153        struct at91_port *at91_port = at91_pio_get_port(port);
 154        u32 mask;
 155
 156        if (at91_port && (pin < GPIO_PER_BANK)) {
 157                mask = 1 << pin;
 158                writel(mask, &at91_port->idr);
 159                at91_set_pio_pullup(port, pin, use_pullup);
 160                writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
 161                       &at91_port->mux.pio3.abcdsr1);
 162                writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
 163                       &at91_port->mux.pio3.abcdsr2);
 164
 165                writel(mask, &at91_port->pdr);
 166        }
 167
 168        return 0;
 169}
 170/*
 171 * mux the pin to the "C" internal peripheral role.
 172 */
 173int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
 174{
 175        struct at91_port *at91_port = at91_pio_get_port(port);
 176        u32 mask;
 177
 178        if (at91_port && (pin < GPIO_PER_BANK)) {
 179                mask = 1 << pin;
 180                writel(mask, &at91_port->idr);
 181                at91_set_pio_pullup(port, pin, use_pullup);
 182                writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
 183                       &at91_port->mux.pio3.abcdsr1);
 184                writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
 185                       &at91_port->mux.pio3.abcdsr2);
 186                writel(mask, &at91_port->pdr);
 187        }
 188
 189        return 0;
 190}
 191
 192/*
 193 * mux the pin to the "D" internal peripheral role.
 194 */
 195int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
 196{
 197        struct at91_port *at91_port = at91_pio_get_port(port);
 198        u32 mask;
 199
 200        if (at91_port && (pin < GPIO_PER_BANK)) {
 201                mask = 1 << pin;
 202                writel(mask, &at91_port->idr);
 203                at91_set_pio_pullup(port, pin, use_pullup);
 204                writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
 205                       &at91_port->mux.pio3.abcdsr1);
 206                writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
 207                       &at91_port->mux.pio3.abcdsr2);
 208                writel(mask, &at91_port->pdr);
 209        }
 210
 211        return 0;
 212}
 213
 214#if CONFIG_IS_ENABLED(DM_GPIO)
 215static bool at91_get_port_output(struct at91_port *at91_port, int offset)
 216{
 217        u32 mask, val;
 218
 219        mask = 1 << offset;
 220        val = readl(&at91_port->osr);
 221        return val & mask;
 222}
 223#endif
 224
 225static void at91_set_port_input(struct at91_port *at91_port, int offset,
 226                                int use_pullup)
 227{
 228        u32 mask;
 229
 230        mask = 1 << offset;
 231        writel(mask, &at91_port->idr);
 232        at91_set_port_pullup(at91_port, offset, use_pullup);
 233        writel(mask, &at91_port->odr);
 234        writel(mask, &at91_port->per);
 235}
 236
 237/*
 238 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 239 * configure it for an input.
 240 */
 241int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
 242{
 243        struct at91_port *at91_port = at91_pio_get_port(port);
 244
 245        if (at91_port && (pin < GPIO_PER_BANK))
 246                at91_set_port_input(at91_port, pin, use_pullup);
 247
 248        return 0;
 249}
 250
 251static void at91_set_port_output(struct at91_port *at91_port, int offset,
 252                                 int value)
 253{
 254        u32 mask;
 255
 256        mask = 1 << offset;
 257        writel(mask, &at91_port->idr);
 258        writel(mask, &at91_port->pudr);
 259        if (value)
 260                writel(mask, &at91_port->sodr);
 261        else
 262                writel(mask, &at91_port->codr);
 263        writel(mask, &at91_port->oer);
 264        writel(mask, &at91_port->per);
 265}
 266
 267/*
 268 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 269 * and configure it for an output.
 270 */
 271int at91_set_pio_output(unsigned port, u32 pin, int value)
 272{
 273        struct at91_port *at91_port = at91_pio_get_port(port);
 274
 275        if (at91_port && (pin < GPIO_PER_BANK))
 276                at91_set_port_output(at91_port, pin, value);
 277
 278        return 0;
 279}
 280
 281/*
 282 * enable/disable the glitch filter. mostly used with IRQ handling.
 283 */
 284int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
 285{
 286        struct at91_port *at91_port = at91_pio_get_port(port);
 287        u32 mask;
 288
 289        if (at91_port && (pin < GPIO_PER_BANK)) {
 290                mask = 1 << pin;
 291                if (is_on)
 292                        writel(mask, &at91_port->ifer);
 293                else
 294                        writel(mask, &at91_port->ifdr);
 295        }
 296
 297        return 0;
 298}
 299
 300/*
 301 * enable/disable the glitch filter. mostly used with IRQ handling.
 302 */
 303int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
 304{
 305        struct at91_port *at91_port = at91_pio_get_port(port);
 306        u32 mask;
 307
 308        if (at91_port && (pin < GPIO_PER_BANK)) {
 309                mask = 1 << pin;
 310                if (is_on) {
 311                        writel(mask, &at91_port->mux.pio3.ifscdr);
 312                        writel(mask, &at91_port->ifer);
 313                } else {
 314                        writel(mask, &at91_port->ifdr);
 315                }
 316        }
 317
 318        return 0;
 319}
 320
 321/*
 322 * enable/disable the debounce filter.
 323 */
 324int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
 325{
 326        struct at91_port *at91_port = at91_pio_get_port(port);
 327        u32 mask;
 328
 329        if (at91_port && (pin < GPIO_PER_BANK)) {
 330                mask = 1 << pin;
 331                if (is_on) {
 332                        writel(mask, &at91_port->mux.pio3.ifscer);
 333                        writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
 334                        writel(mask, &at91_port->ifer);
 335                } else {
 336                        writel(mask, &at91_port->ifdr);
 337                }
 338        }
 339
 340        return 0;
 341}
 342
 343/*
 344 * enable/disable the pull-down.
 345 * If pull-up already enabled while calling the function, we disable it.
 346 */
 347int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
 348{
 349        struct at91_port *at91_port = at91_pio_get_port(port);
 350        u32 mask;
 351
 352        if (at91_port && (pin < GPIO_PER_BANK)) {
 353                mask = 1 << pin;
 354                if (is_on) {
 355                        at91_set_pio_pullup(port, pin, 0);
 356                        writel(mask, &at91_port->mux.pio3.ppder);
 357                } else
 358                        writel(mask, &at91_port->mux.pio3.ppddr);
 359        }
 360
 361        return 0;
 362}
 363
 364int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
 365{
 366        struct at91_port *at91_port = at91_pio_get_port(port);
 367
 368        if (use_pullup)
 369                at91_pio3_set_pio_pulldown(port, pin, 0);
 370
 371        if (at91_port && (pin < GPIO_PER_BANK))
 372                at91_set_port_pullup(at91_port, pin, use_pullup);
 373
 374        return 0;
 375}
 376
 377/*
 378 * disable Schmitt trigger
 379 */
 380int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
 381{
 382        struct at91_port *at91_port = at91_pio_get_port(port);
 383        u32 mask;
 384
 385        if (at91_port && (pin < GPIO_PER_BANK)) {
 386                mask = 1 << pin;
 387                writel(readl(&at91_port->schmitt) | mask,
 388                       &at91_port->schmitt);
 389        }
 390
 391        return 0;
 392}
 393
 394/*
 395 * enable/disable the multi-driver. This is only valid for output and
 396 * allows the output pin to run as an open collector output.
 397 */
 398int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
 399{
 400        struct at91_port *at91_port = at91_pio_get_port(port);
 401        u32 mask;
 402
 403        if (at91_port && (pin < GPIO_PER_BANK)) {
 404                mask = 1 << pin;
 405                if (is_on)
 406                        writel(mask, &at91_port->mder);
 407                else
 408                        writel(mask, &at91_port->mddr);
 409        }
 410
 411        return 0;
 412}
 413
 414static void at91_set_port_value(struct at91_port *at91_port, int offset,
 415                                int value)
 416{
 417        u32 mask;
 418
 419        mask = 1 << offset;
 420        if (value)
 421                writel(mask, &at91_port->sodr);
 422        else
 423                writel(mask, &at91_port->codr);
 424}
 425
 426/*
 427 * assuming the pin is muxed as a gpio output, set its value.
 428 */
 429int at91_set_pio_value(unsigned port, unsigned pin, int value)
 430{
 431        struct at91_port *at91_port = at91_pio_get_port(port);
 432
 433        if (at91_port && (pin < GPIO_PER_BANK))
 434                at91_set_port_value(at91_port, pin, value);
 435
 436        return 0;
 437}
 438
 439static int at91_get_port_value(struct at91_port *at91_port, int offset)
 440{
 441        u32 pdsr = 0, mask;
 442
 443        mask = 1 << offset;
 444        pdsr = readl(&at91_port->pdsr) & mask;
 445
 446        return pdsr != 0;
 447}
 448/*
 449 * read the pin's value (works even if it's not muxed as a gpio).
 450 */
 451int at91_get_pio_value(unsigned port, unsigned pin)
 452{
 453        struct at91_port *at91_port = at91_pio_get_port(port);
 454
 455        if (at91_port && (pin < GPIO_PER_BANK))
 456                return at91_get_port_value(at91_port, pin);
 457
 458        return 0;
 459}
 460
 461#if !CONFIG_IS_ENABLED(DM_GPIO)
 462/* Common GPIO API */
 463
 464int gpio_request(unsigned gpio, const char *label)
 465{
 466        return 0;
 467}
 468
 469int gpio_free(unsigned gpio)
 470{
 471        return 0;
 472}
 473
 474int gpio_direction_input(unsigned gpio)
 475{
 476        at91_set_pio_input(at91_gpio_to_port(gpio),
 477                           at91_gpio_to_pin(gpio), 0);
 478        return 0;
 479}
 480
 481int gpio_direction_output(unsigned gpio, int value)
 482{
 483        at91_set_pio_output(at91_gpio_to_port(gpio),
 484                            at91_gpio_to_pin(gpio), value);
 485        return 0;
 486}
 487
 488int gpio_get_value(unsigned gpio)
 489{
 490        return at91_get_pio_value(at91_gpio_to_port(gpio),
 491                                  at91_gpio_to_pin(gpio));
 492}
 493
 494int gpio_set_value(unsigned gpio, int value)
 495{
 496        at91_set_pio_value(at91_gpio_to_port(gpio),
 497                           at91_gpio_to_pin(gpio), value);
 498
 499        return 0;
 500}
 501#endif
 502
 503#if CONFIG_IS_ENABLED(DM_GPIO)
 504
 505struct at91_port_priv {
 506        struct at91_port *regs;
 507};
 508
 509/* set GPIO pin 'gpio' as an input */
 510static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
 511{
 512        struct at91_port_priv *port = dev_get_priv(dev);
 513
 514        at91_set_port_input(port->regs, offset, 0);
 515
 516        return 0;
 517}
 518
 519/* set GPIO pin 'gpio' as an output, with polarity 'value' */
 520static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
 521                                       int value)
 522{
 523        struct at91_port_priv *port = dev_get_priv(dev);
 524
 525        at91_set_port_output(port->regs, offset, value);
 526
 527        return 0;
 528}
 529
 530/* read GPIO IN value of pin 'gpio' */
 531static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
 532{
 533        struct at91_port_priv *port = dev_get_priv(dev);
 534
 535        return at91_get_port_value(port->regs, offset);
 536}
 537
 538/* write GPIO OUT value to pin 'gpio' */
 539static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
 540                               int value)
 541{
 542        struct at91_port_priv *port = dev_get_priv(dev);
 543
 544        at91_set_port_value(port->regs, offset, value);
 545
 546        return 0;
 547}
 548
 549static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
 550{
 551        struct at91_port_priv *port = dev_get_priv(dev);
 552
 553        /* GPIOF_FUNC is not implemented yet */
 554        if (at91_get_port_output(port->regs, offset))
 555                return GPIOF_OUTPUT;
 556        else
 557                return GPIOF_INPUT;
 558}
 559
 560static const char *at91_get_bank_name(uint32_t base_addr)
 561{
 562        switch (base_addr) {
 563        case ATMEL_BASE_PIOA:
 564                return "PIOA";
 565        case ATMEL_BASE_PIOB:
 566                return "PIOB";
 567        case ATMEL_BASE_PIOC:
 568                return "PIOC";
 569#if (ATMEL_PIO_PORTS > 3)
 570        case ATMEL_BASE_PIOD:
 571                return "PIOD";
 572#if (ATMEL_PIO_PORTS > 4)
 573        case ATMEL_BASE_PIOE:
 574                return "PIOE";
 575#endif
 576#endif
 577        }
 578
 579        return "undefined";
 580}
 581
 582static const struct dm_gpio_ops gpio_at91_ops = {
 583        .direction_input        = at91_gpio_direction_input,
 584        .direction_output       = at91_gpio_direction_output,
 585        .get_value              = at91_gpio_get_value,
 586        .set_value              = at91_gpio_set_value,
 587        .get_function           = at91_gpio_get_function,
 588};
 589
 590static int at91_gpio_probe(struct udevice *dev)
 591{
 592        struct at91_port_priv *port = dev_get_priv(dev);
 593        struct at91_port_plat *plat = dev_get_plat(dev);
 594        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 595        struct clk clk;
 596        int ret;
 597
 598        ret = clk_get_by_index(dev, 0, &clk);
 599        if (ret)
 600                return ret;
 601
 602        ret = clk_enable(&clk);
 603        if (ret)
 604                return ret;
 605
 606        clk_free(&clk);
 607
 608#if CONFIG_IS_ENABLED(OF_CONTROL)
 609        plat->base_addr = dev_read_addr(dev);
 610#endif
 611        plat->bank_name = at91_get_bank_name(plat->base_addr);
 612        port->regs = (struct at91_port *)plat->base_addr;
 613
 614        uc_priv->bank_name = plat->bank_name;
 615        uc_priv->gpio_count = GPIO_PER_BANK;
 616
 617        return 0;
 618}
 619
 620#if CONFIG_IS_ENABLED(OF_CONTROL)
 621static const struct udevice_id at91_gpio_ids[] = {
 622        { .compatible = "atmel,at91rm9200-gpio" },
 623        { }
 624};
 625#endif
 626
 627U_BOOT_DRIVER(atmel_at91rm9200_gpio) = {
 628        .name   = "atmel_at91rm9200_gpio",
 629        .id     = UCLASS_GPIO,
 630#if CONFIG_IS_ENABLED(OF_CONTROL)
 631        .of_match = at91_gpio_ids,
 632        .plat_auto      = sizeof(struct at91_port_plat),
 633#endif
 634        .ops    = &gpio_at91_ops,
 635        .probe  = at91_gpio_probe,
 636        .priv_auto      = sizeof(struct at91_port_priv),
 637};
 638#endif
 639