LXR uboot/drivers/gpio/tegra

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * NVIDIA Tegra20 GPIO handling.
   4 *  (C) Copyright 2010-2012,2015
   5 *  NVIDIA Corporation <www.nvidia.com>
   6 */
   7
   8/*
   9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
  10 * Tom Warren (twarren@nvidia.com)
  11 */
  12
  13#include <common.h>
  14#include <dm.h>
  15#include <log.h>
  16#include <malloc.h>
  17#include <errno.h>
  18#include <fdtdec.h>
  19#include <asm/io.h>
  20#include <asm/bitops.h>
  21#include <asm/arch/tegra.h>
  22#include <asm/gpio.h>
  23#include <dm/device-internal.h>
  24#include <dt-bindings/gpio/gpio.h>
  25
  26static const int CFG_SFIO = 0;
  27static const int CFG_GPIO = 1;
  28static const int DIRECTION_INPUT = 0;
  29static const int DIRECTION_OUTPUT = 1;
  30
  31struct tegra_gpio_plat {
  32        struct gpio_ctlr_bank *bank;
  33        const char *port_name;  /* Name of port, e.g. "B" */
  34        int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  35};
  36
  37/* Information about each port at run-time */
  38struct tegra_port_info {
  39        struct gpio_ctlr_bank *bank;
  40        int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  41};
  42
  43/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
  44static int get_config(unsigned gpio)
  45{
  46        struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  47        struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  48        u32 u;
  49        int type;
  50
  51        u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  52        type = (u >> GPIO_BIT(gpio)) & 1;
  53
  54        debug("get_config: port = %d, bit = %d is %s\n",
  55                GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  56
  57        return type ? CFG_GPIO : CFG_SFIO;
  58}
  59
  60/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
  61static void set_config(unsigned gpio, int type)
  62{
  63        struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  64        struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  65        u32 u;
  66
  67        debug("set_config: port = %d, bit = %d, %s\n",
  68                GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  69
  70        u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  71        if (type != CFG_SFIO)
  72                u |= 1 << GPIO_BIT(gpio);
  73        else
  74                u &= ~(1 << GPIO_BIT(gpio));
  75        writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
  76}
  77
  78/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
  79static int get_direction(unsigned gpio)
  80{
  81        struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  82        struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  83        u32 u;
  84        int dir;
  85
  86        u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
  87        dir =  (u >> GPIO_BIT(gpio)) & 1;
  88
  89        debug("get_direction: port = %d, bit = %d, %s\n",
  90                GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
  91
  92        return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
  93}
  94
  95/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
  96static void set_direction(unsigned gpio, int output)
  97{
  98        struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  99        struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 100        u32 u;
 101
 102        debug("set_direction: port = %d, bit = %d, %s\n",
 103                GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
 104
 105        u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
 106        if (output != DIRECTION_INPUT)
 107                u |= 1 << GPIO_BIT(gpio);
 108        else
 109                u &= ~(1 << GPIO_BIT(gpio));
 110        writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
 111}
 112
 113/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
 114static void set_level(unsigned gpio, int high)
 115{
 116        struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 117        struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 118        u32 u;
 119
 120        debug("set_level: port = %d, bit %d == %d\n",
 121                GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
 122
 123        u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
 124        if (high)
 125                u |= 1 << GPIO_BIT(gpio);
 126        else
 127                u &= ~(1 << GPIO_BIT(gpio));
 128        writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
 129}
 130
 131/*
 132 * Generic_GPIO primitives.
 133 */
 134
 135/* set GPIO pin 'gpio' as an input */
 136static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
 137{
 138        struct tegra_port_info *state = dev_get_priv(dev);
 139
 140        /* Configure GPIO direction as input. */
 141        set_direction(state->base_gpio + offset, DIRECTION_INPUT);
 142
 143        /* Enable the pin as a GPIO */
 144        set_config(state->base_gpio + offset, 1);
 145
 146        return 0;
 147}
 148
 149/* set GPIO pin 'gpio' as an output, with polarity 'value' */
 150static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
 151                                       int value)
 152{
 153        struct tegra_port_info *state = dev_get_priv(dev);
 154        int gpio = state->base_gpio + offset;
 155
 156        /* Configure GPIO output value. */
 157        set_level(gpio, value);
 158
 159        /* Configure GPIO direction as output. */
 160        set_direction(gpio, DIRECTION_OUTPUT);
 161
 162        /* Enable the pin as a GPIO */
 163        set_config(state->base_gpio + offset, 1);
 164
 165        return 0;
 166}
 167
 168/* read GPIO IN value of pin 'gpio' */
 169static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
 170{
 171        struct tegra_port_info *state = dev_get_priv(dev);
 172        int gpio = state->base_gpio + offset;
 173        int val;
 174
 175        debug("%s: pin = %d (port %d:bit %d)\n", __func__,
 176              gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
 177
 178        if (get_direction(gpio) == DIRECTION_INPUT)
 179                val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
 180        else
 181                val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
 182
 183        return (val >> GPIO_BIT(gpio)) & 1;
 184}
 185
 186/* write GPIO OUT value to pin 'gpio' */
 187static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 188{
 189        struct tegra_port_info *state = dev_get_priv(dev);
 190        int gpio = state->base_gpio + offset;
 191
 192        debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
 193              gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
 194
 195        /* Configure GPIO output value. */
 196        set_level(gpio, value);
 197
 198        return 0;
 199}
 200
 201void gpio_config_table(const struct tegra_gpio_config *config, int len)
 202{
 203        int i;
 204
 205        for (i = 0; i < len; i++) {
 206                switch (config[i].init) {
 207                case TEGRA_GPIO_INIT_IN:
 208                        set_direction(config[i].gpio, DIRECTION_INPUT);
 209                        break;
 210                case TEGRA_GPIO_INIT_OUT0:
 211                        set_level(config[i].gpio, 0);
 212                        set_direction(config[i].gpio, DIRECTION_OUTPUT);
 213                        break;
 214                case TEGRA_GPIO_INIT_OUT1:
 215                        set_level(config[i].gpio, 1);
 216                        set_direction(config[i].gpio, DIRECTION_OUTPUT);
 217                        break;
 218                }
 219                set_config(config[i].gpio, CFG_GPIO);
 220        }
 221}
 222
 223static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
 224{
 225        struct tegra_port_info *state = dev_get_priv(dev);
 226        int gpio = state->base_gpio + offset;
 227
 228        if (!get_config(gpio))
 229                return GPIOF_FUNC;
 230        else if (get_direction(gpio))
 231                return GPIOF_OUTPUT;
 232        else
 233                return GPIOF_INPUT;
 234}
 235
 236static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
 237                            struct ofnode_phandle_args *args)
 238{
 239        int gpio, port, ret;
 240
 241        gpio = args->args[0];
 242        port = gpio / TEGRA_GPIOS_PER_PORT;
 243        ret = device_get_child(dev, port, &desc->dev);
 244        if (ret)
 245                return ret;
 246        desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
 247        desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
 248
 249        return 0;
 250}
 251
 252static const struct dm_gpio_ops gpio_tegra_ops = {
 253        .direction_input        = tegra_gpio_direction_input,
 254        .direction_output       = tegra_gpio_direction_output,
 255        .get_value              = tegra_gpio_get_value,
 256        .set_value              = tegra_gpio_set_value,
 257        .get_function           = tegra_gpio_get_function,
 258        .xlate                  = tegra_gpio_xlate,
 259};
 260
 261/**
 262 * Returns the name of a GPIO port
 263 *
 264 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
 265 *
 266 * @base_port: Base port number (0, 1..n-1)
 267 * Return: allocated string containing the name
 268 */
 269static char *gpio_port_name(int base_port)
 270{
 271        char *name, *s;
 272
 273        name = malloc(3);
 274        if (name) {
 275                s = name;
 276                *s++ = 'A' + (base_port % 26);
 277                if (base_port >= 26)
 278                        *s++ = *name;
 279                *s = '\0';
 280        }
 281
 282        return name;
 283}
 284
 285static const struct udevice_id tegra_gpio_ids[] = {
 286        { .compatible = "nvidia,tegra30-gpio" },
 287        { .compatible = "nvidia,tegra20-gpio" },
 288        { }
 289};
 290
 291static int gpio_tegra_probe(struct udevice *dev)
 292{
 293        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 294        struct tegra_port_info *priv = dev_get_priv(dev);
 295        struct tegra_gpio_plat *plat = dev_get_plat(dev);
 296
 297        /* Only child devices have ports */
 298        if (!plat)
 299                return 0;
 300
 301        priv->bank = plat->bank;
 302        priv->base_gpio = plat->base_gpio;
 303
 304        uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
 305        uc_priv->bank_name = plat->port_name;
 306
 307        return 0;
 308}
 309
 310/**
 311 * We have a top-level GPIO device with no actual GPIOs. It has a child
 312 * device for each Tegra port.
 313 */
 314static int gpio_tegra_bind(struct udevice *parent)
 315{
 316        struct tegra_gpio_plat *plat = dev_get_plat(parent);
 317        struct gpio_ctlr *ctlr;
 318        int bank_count;
 319        int bank;
 320        int ret;
 321
 322        /* If this is a child device, there is nothing to do here */
 323        if (plat)
 324                return 0;
 325
 326        /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
 327#ifdef CONFIG_SPL_BUILD
 328        ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 329        bank_count = TEGRA_GPIO_BANKS;
 330#else
 331        {
 332        int len;
 333
 334        /*
 335         * This driver does not make use of interrupts, other than to figure
 336         * out the number of GPIO banks
 337         */
 338        len = dev_read_size(parent, "interrupts");
 339        if (len < 0)
 340                return len;
 341        bank_count = len / 3 / sizeof(u32);
 342        ctlr = dev_read_addr_ptr(parent);
 343        if (!ctlr)
 344                return -EINVAL;
 345        }
 346#endif
 347        for (bank = 0; bank < bank_count; bank++) {
 348                int port;
 349
 350                for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
 351                        struct tegra_gpio_plat *plat;
 352                        struct udevice *dev;
 353                        int base_port;
 354
 355                        plat = calloc(1, sizeof(*plat));
 356                        if (!plat)
 357                                return -ENOMEM;
 358                        plat->bank = &ctlr->gpio_bank[bank];
 359                        base_port = bank * TEGRA_PORTS_PER_BANK + port;
 360                        plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
 361                        plat->port_name = gpio_port_name(base_port);
 362
 363                        ret = device_bind(parent, parent->driver,
 364                                          plat->port_name, plat,
 365                                          dev_ofnode(parent), &dev);
 366                        if (ret)
 367                                return ret;
 368                }
 369        }
 370
 371        return 0;
 372}
 373
 374U_BOOT_DRIVER(gpio_tegra) = {
 375        .name   = "gpio_tegra",
 376        .id     = UCLASS_GPIO,
 377        .of_match = tegra_gpio_ids,
 378        .bind   = gpio_tegra_bind,
 379        .probe = gpio_tegra_probe,
 380        .priv_auto      = sizeof(struct tegra_port_info),
 381        .ops    = &gpio_tegra_ops,
 382};
 383