uboot/drivers/i2c/designware_i2c.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2009
   4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
   5 */
   6
   7#include <common.h>
   8#include <clk.h>
   9#include <dm.h>
  10#include <i2c.h>
  11#include <log.h>
  12#include <malloc.h>
  13#include <pci.h>
  14#include <reset.h>
  15#include <asm/io.h>
  16#include <linux/delay.h>
  17#include "designware_i2c.h"
  18#include <dm/device_compat.h>
  19#include <linux/err.h>
  20
  21/*
  22 * This assigned unique hex value is constant and is derived from the two ASCII
  23 * letters 'DW' followed by a 16-bit unsigned number
  24 */
  25#define DW_I2C_COMP_TYPE        0x44570140
  26
  27static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  28{
  29        u32 ena = enable ? IC_ENABLE_0B : 0;
  30        int timeout = 100;
  31
  32        do {
  33                writel(ena, &i2c_base->ic_enable);
  34                if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  35                        return 0;
  36
  37                /*
  38                 * Wait 10 times the signaling period of the highest I2C
  39                 * transfer supported by the driver (for 400KHz this is
  40                 * 25us) as described in the DesignWare I2C databook.
  41                 */
  42                udelay(25);
  43        } while (timeout--);
  44        printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  45
  46        return -ETIMEDOUT;
  47}
  48
  49/* High and low times in different speed modes (in ns) */
  50enum {
  51        /* SDA Hold Time */
  52        DEFAULT_SDA_HOLD_TIME           = 300,
  53};
  54
  55/**
  56 * calc_counts() - Convert a period to a number of IC clk cycles
  57 *
  58 * @ic_clk: Input clock in Hz
  59 * @period_ns: Period to represent, in ns
  60 * Return: calculated count
  61 */
  62static uint calc_counts(uint ic_clk, uint period_ns)
  63{
  64        return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  65}
  66
  67/**
  68 * struct i2c_mode_info - Information about an I2C speed mode
  69 *
  70 * Each speed mode has its own characteristics. This struct holds these to aid
  71 * calculations in dw_i2c_calc_timing().
  72 *
  73 * @speed: Speed in Hz
  74 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  75 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  76 * @def_rise_time_ns: Default rise time in ns
  77 * @def_fall_time_ns: Default fall time in ns
  78 */
  79struct i2c_mode_info {
  80        int speed;
  81        int min_scl_hightime_ns;
  82        int min_scl_lowtime_ns;
  83        int def_rise_time_ns;
  84        int def_fall_time_ns;
  85};
  86
  87static const struct i2c_mode_info info_for_mode[] = {
  88        [IC_SPEED_MODE_STANDARD] = {
  89                I2C_SPEED_STANDARD_RATE,
  90                MIN_SS_SCL_HIGHTIME,
  91                MIN_SS_SCL_LOWTIME,
  92                1000,
  93                300,
  94        },
  95        [IC_SPEED_MODE_FAST] = {
  96                I2C_SPEED_FAST_RATE,
  97                MIN_FS_SCL_HIGHTIME,
  98                MIN_FS_SCL_LOWTIME,
  99                300,
 100                300,
 101        },
 102        [IC_SPEED_MODE_FAST_PLUS] = {
 103                I2C_SPEED_FAST_PLUS_RATE,
 104                MIN_FP_SCL_HIGHTIME,
 105                MIN_FP_SCL_LOWTIME,
 106                260,
 107                500,
 108        },
 109        [IC_SPEED_MODE_HIGH] = {
 110                I2C_SPEED_HIGH_RATE,
 111                MIN_HS_SCL_HIGHTIME,
 112                MIN_HS_SCL_LOWTIME,
 113                120,
 114                120,
 115        },
 116};
 117
 118/**
 119 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 120 *
 121 * @priv: Bus private information (NULL if not using driver model)
 122 * @mode: Speed mode to use
 123 * @ic_clk: IC clock speed in Hz
 124 * @spk_cnt: Spike-suppression count
 125 * @config: Returns value to use
 126 * Return: 0 if OK, -EINVAL if the calculation failed due to invalid data
 127 */
 128static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 129                              int ic_clk, int spk_cnt,
 130                              struct dw_i2c_speed_config *config)
 131{
 132        int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 133        int hcnt, lcnt, period_cnt, diff, tot;
 134        int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 135        const struct i2c_mode_info *info;
 136
 137        /*
 138         * Find the period, rise, fall, min tlow, and min thigh in terms of
 139         * counts of the IC clock
 140         */
 141        info = &info_for_mode[mode];
 142        period_cnt = ic_clk / info->speed;
 143        scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 144                 priv->scl_rise_time_ns : info->def_rise_time_ns;
 145        scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 146                 priv->scl_fall_time_ns : info->def_fall_time_ns;
 147        rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 148        fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 149        min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 150        min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 151
 152        debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 153              mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt,
 154              min_tlow_cnt, min_thigh_cnt, spk_cnt);
 155
 156        /*
 157         * Back-solve for hcnt and lcnt according to the following equations:
 158         * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 159         * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 160         */
 161        hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 162        lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 163
 164        if (hcnt < 0 || lcnt < 0) {
 165                debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 166                return log_msg_ret("counts", -EINVAL);
 167        }
 168
 169        /*
 170         * Now add things back up to ensure the period is hit. If it is off,
 171         * split the difference and bias to lcnt for remainder
 172         */
 173        tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 174
 175        if (tot < period_cnt) {
 176                diff = (period_cnt - tot) / 2;
 177                hcnt += diff;
 178                lcnt += diff;
 179                tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 180                lcnt += period_cnt - tot;
 181        }
 182
 183        config->scl_lcnt = lcnt;
 184        config->scl_hcnt = hcnt;
 185
 186        /* Use internal default unless other value is specified */
 187        sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 188                 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 189        config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 190
 191        debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 192              config->sda_hold);
 193
 194        return 0;
 195}
 196
 197/**
 198 * calc_bus_speed() - Calculate the config to use for a particular i2c speed
 199 *
 200 * @priv: Private information for the driver (NULL if not using driver model)
 201 * @i2c_base: Registers for the I2C controller
 202 * @speed: Required i2c speed in Hz
 203 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
 204 * @config: Returns the config to use for this speed
 205 * Return: 0 if OK, -ve on error
 206 */
 207static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
 208                          ulong bus_clk, struct dw_i2c_speed_config *config)
 209{
 210        const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 211        enum i2c_speed_mode i2c_spd;
 212        int spk_cnt;
 213        int ret;
 214
 215        if (priv)
 216                scl_sda_cfg = priv->scl_sda_cfg;
 217        /* Allow high speed if there is no config, or the config allows it */
 218        if (speed >= I2C_SPEED_HIGH_RATE)
 219                i2c_spd = IC_SPEED_MODE_HIGH;
 220        else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 221                i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 222        else if (speed >= I2C_SPEED_FAST_RATE)
 223                i2c_spd = IC_SPEED_MODE_FAST;
 224        else
 225                i2c_spd = IC_SPEED_MODE_STANDARD;
 226
 227        /* Check is high speed possible and fall back to fast mode if not */
 228        if (i2c_spd == IC_SPEED_MODE_HIGH) {
 229                u32 comp_param1;
 230
 231                comp_param1 = readl(&regs->comp_param1);
 232                if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 233                                != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
 234                        i2c_spd = IC_SPEED_MODE_FAST;
 235        }
 236
 237        /* Get the proper spike-suppression count based on target speed */
 238        if (!priv || !priv->has_spk_cnt)
 239                spk_cnt = 0;
 240        else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 241                spk_cnt = readl(&regs->hs_spklen);
 242        else
 243                spk_cnt = readl(&regs->fs_spklen);
 244        if (scl_sda_cfg) {
 245                config->sda_hold = scl_sda_cfg->sda_hold;
 246                if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 247                        config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 248                        config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 249                } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
 250                        config->scl_hcnt = scl_sda_cfg->hs_hcnt;
 251                        config->scl_lcnt = scl_sda_cfg->hs_lcnt;
 252                } else {
 253                        config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 254                        config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 255                }
 256        } else {
 257                ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 258                                         config);
 259                if (ret)
 260                        return log_msg_ret("gen_confg", ret);
 261        }
 262        config->speed_mode = i2c_spd;
 263
 264        return 0;
 265}
 266
 267/**
 268 * _dw_i2c_set_bus_speed() - Set the i2c speed
 269 *
 270 * @priv: Private information for the driver (NULL if not using driver model)
 271 * @i2c_base: Registers for the I2C controller
 272 * @speed: Required i2c speed in Hz
 273 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
 274 * Return: 0 if OK, -ve on error
 275 */
 276static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 277                                 unsigned int speed, unsigned int bus_clk)
 278{
 279        struct dw_i2c_speed_config config;
 280        unsigned int cntl;
 281        unsigned int ena;
 282        int ret;
 283
 284        ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
 285        if (ret)
 286                return ret;
 287
 288        /* Get enable setting for restore later */
 289        ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 290
 291        /* to set speed cltr must be disabled */
 292        dw_i2c_enable(i2c_base, false);
 293
 294        cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 295
 296        switch (config.speed_mode) {
 297        case IC_SPEED_MODE_HIGH:
 298                cntl |= IC_CON_SPD_HS;
 299                writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 300                writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 301                break;
 302        case IC_SPEED_MODE_STANDARD:
 303                cntl |= IC_CON_SPD_SS;
 304                writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 305                writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 306                break;
 307        case IC_SPEED_MODE_FAST_PLUS:
 308        case IC_SPEED_MODE_FAST:
 309        default:
 310                cntl |= IC_CON_SPD_FS;
 311                writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 312                writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 313                break;
 314        }
 315
 316        writel(cntl, &i2c_base->ic_con);
 317
 318        /* Configure SDA Hold Time if required */
 319        if (config.sda_hold)
 320                writel(config.sda_hold, &i2c_base->ic_sda_hold);
 321
 322        /* Restore back i2c now speed set */
 323        if (ena == IC_ENABLE_0B)
 324                dw_i2c_enable(i2c_base, true);
 325        if (priv)
 326                priv->config = config;
 327
 328        return 0;
 329}
 330
 331int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
 332                            struct dw_i2c_speed_config *config)
 333{
 334        struct dw_i2c *priv = dev_get_priv(dev);
 335        ulong rate;
 336        int ret;
 337
 338#if CONFIG_IS_ENABLED(CLK)
 339        rate = clk_get_rate(&priv->clk);
 340        if (IS_ERR_VALUE(rate))
 341                return log_msg_ret("clk", -EINVAL);
 342#else
 343        rate = IC_CLK;
 344#endif
 345
 346        ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
 347        if (ret)
 348                printf("%s: ret=%d\n", __func__, ret);
 349        if (ret)
 350                return log_msg_ret("calc_bus_speed", ret);
 351
 352        return 0;
 353}
 354
 355/*
 356 * i2c_setaddress - Sets the target slave address
 357 * @i2c_addr:   target i2c address
 358 *
 359 * Sets the target slave address.
 360 */
 361static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 362{
 363        /* Disable i2c */
 364        dw_i2c_enable(i2c_base, false);
 365
 366        writel(i2c_addr, &i2c_base->ic_tar);
 367
 368        /* Enable i2c */
 369        dw_i2c_enable(i2c_base, true);
 370}
 371
 372/*
 373 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 374 *
 375 * Flushes the i2c RX FIFO
 376 */
 377static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 378{
 379        while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 380                readl(&i2c_base->ic_cmd_data);
 381}
 382
 383/*
 384 * i2c_wait_for_bb - Waits for bus busy
 385 *
 386 * Waits for bus busy
 387 */
 388static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 389{
 390        unsigned long start_time_bb = get_timer(0);
 391
 392        while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 393               !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 394
 395                /* Evaluate timeout */
 396                if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 397                        return 1;
 398        }
 399
 400        return 0;
 401}
 402
 403static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 404                         int alen)
 405{
 406        if (i2c_wait_for_bb(i2c_base))
 407                return 1;
 408
 409        i2c_setaddress(i2c_base, chip);
 410        while (alen) {
 411                alen--;
 412                /* high byte address going out first */
 413                writel((addr >> (alen * 8)) & 0xff,
 414                       &i2c_base->ic_cmd_data);
 415        }
 416        return 0;
 417}
 418
 419static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 420{
 421        ulong start_stop_det = get_timer(0);
 422
 423        while (1) {
 424                if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 425                        readl(&i2c_base->ic_clr_stop_det);
 426                        break;
 427                } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 428                        break;
 429                }
 430        }
 431
 432        if (i2c_wait_for_bb(i2c_base)) {
 433                printf("Timed out waiting for bus\n");
 434                return 1;
 435        }
 436
 437        i2c_flush_rxfifo(i2c_base);
 438
 439        return 0;
 440}
 441
 442/*
 443 * i2c_read - Read from i2c memory
 444 * @chip:       target i2c address
 445 * @addr:       address to read from
 446 * @alen:
 447 * @buffer:     buffer for read data
 448 * @len:        no of bytes to be read
 449 *
 450 * Read from i2c memory.
 451 */
 452static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 453                         int alen, u8 *buffer, int len)
 454{
 455        unsigned long start_time_rx;
 456        unsigned int active = 0;
 457
 458#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 459        /*
 460         * EEPROM chips that implement "address overflow" are ones
 461         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 462         * address and the extra bits end up in the "chip address"
 463         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 464         * four 256 byte chips.
 465         *
 466         * Note that we consider the length of the address field to
 467         * still be one byte because the extra address bits are
 468         * hidden in the chip address.
 469         */
 470        dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 471        addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 472
 473        debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 474              addr);
 475#endif
 476
 477        if (i2c_xfer_init(i2c_base, dev, addr, alen))
 478                return 1;
 479
 480        start_time_rx = get_timer(0);
 481        while (len) {
 482                if (!active) {
 483                        /*
 484                         * Avoid writing to ic_cmd_data multiple times
 485                         * in case this loop spins too quickly and the
 486                         * ic_status RFNE bit isn't set after the first
 487                         * write. Subsequent writes to ic_cmd_data can
 488                         * trigger spurious i2c transfer.
 489                         */
 490                        if (len == 1)
 491                                writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 492                        else
 493                                writel(IC_CMD, &i2c_base->ic_cmd_data);
 494                        active = 1;
 495                }
 496
 497                if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 498                        *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 499                        len--;
 500                        start_time_rx = get_timer(0);
 501                        active = 0;
 502                } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 503                        return 1;
 504                }
 505        }
 506
 507        return i2c_xfer_finish(i2c_base);
 508}
 509
 510/*
 511 * i2c_write - Write to i2c memory
 512 * @chip:       target i2c address
 513 * @addr:       address to read from
 514 * @alen:
 515 * @buffer:     buffer for read data
 516 * @len:        no of bytes to be read
 517 *
 518 * Write to i2c memory.
 519 */
 520static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 521                          int alen, u8 *buffer, int len)
 522{
 523        int nb = len;
 524        unsigned long start_time_tx;
 525
 526#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 527        /*
 528         * EEPROM chips that implement "address overflow" are ones
 529         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 530         * address and the extra bits end up in the "chip address"
 531         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 532         * four 256 byte chips.
 533         *
 534         * Note that we consider the length of the address field to
 535         * still be one byte because the extra address bits are
 536         * hidden in the chip address.
 537         */
 538        dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 539        addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 540
 541        debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 542              addr);
 543#endif
 544
 545        if (i2c_xfer_init(i2c_base, dev, addr, alen))
 546                return 1;
 547
 548        start_time_tx = get_timer(0);
 549        while (len) {
 550                if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 551                        if (--len == 0) {
 552                                writel(*buffer | IC_STOP,
 553                                       &i2c_base->ic_cmd_data);
 554                        } else {
 555                                writel(*buffer, &i2c_base->ic_cmd_data);
 556                        }
 557                        buffer++;
 558                        start_time_tx = get_timer(0);
 559
 560                } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 561                                printf("Timed out. i2c write Failed\n");
 562                                return 1;
 563                }
 564        }
 565
 566        return i2c_xfer_finish(i2c_base);
 567}
 568
 569/*
 570 * __dw_i2c_init - Init function
 571 * @speed:      required i2c speed
 572 * @slaveaddr:  slave address for the device
 573 *
 574 * Initialization function.
 575 */
 576static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 577{
 578        int ret;
 579
 580        /* Disable i2c */
 581        ret = dw_i2c_enable(i2c_base, false);
 582        if (ret)
 583                return ret;
 584
 585        writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 586               &i2c_base->ic_con);
 587        writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 588        writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 589        writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 590#if !CONFIG_IS_ENABLED(DM_I2C)
 591        _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 592        writel(slaveaddr, &i2c_base->ic_sar);
 593#endif
 594
 595        /* Enable i2c */
 596        ret = dw_i2c_enable(i2c_base, true);
 597        if (ret)
 598                return ret;
 599
 600        return 0;
 601}
 602
 603#if !CONFIG_IS_ENABLED(DM_I2C)
 604/*
 605 * The legacy I2C functions. These need to get removed once
 606 * all users of this driver are converted to DM.
 607 */
 608static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 609{
 610        switch (adap->hwadapnr) {
 611#if CONFIG_SYS_I2C_BUS_MAX >= 4
 612        case 3:
 613                return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 614#endif
 615#if CONFIG_SYS_I2C_BUS_MAX >= 3
 616        case 2:
 617                return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 618#endif
 619#if CONFIG_SYS_I2C_BUS_MAX >= 2
 620        case 1:
 621                return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 622#endif
 623        case 0:
 624                return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 625        default:
 626                printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 627        }
 628
 629        return NULL;
 630}
 631
 632static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 633                                         unsigned int speed)
 634{
 635        adap->speed = speed;
 636        return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 637}
 638
 639static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 640{
 641        __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 642}
 643
 644static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 645                       int alen, u8 *buffer, int len)
 646{
 647        return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 648}
 649
 650static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 651                        int alen, u8 *buffer, int len)
 652{
 653        return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 654}
 655
 656/* dw_i2c_probe - Probe the i2c chip */
 657static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 658{
 659        struct i2c_regs *i2c_base = i2c_get_base(adap);
 660        u32 tmp;
 661        int ret;
 662
 663        /*
 664         * Try to read the first location of the chip.
 665         */
 666        ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 667        if (ret)
 668                dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 669
 670        return ret;
 671}
 672
 673U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 674                         dw_i2c_write, dw_i2c_set_bus_speed,
 675                         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 676
 677#else /* CONFIG_DM_I2C */
 678/* The DM I2C functions */
 679
 680static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 681                               int nmsgs)
 682{
 683        struct dw_i2c *i2c = dev_get_priv(bus);
 684        int ret;
 685
 686        debug("i2c_xfer: %d messages\n", nmsgs);
 687        for (; nmsgs > 0; nmsgs--, msg++) {
 688                debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 689                if (msg->flags & I2C_M_RD) {
 690                        ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 691                                            msg->buf, msg->len);
 692                } else {
 693                        ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 694                                             msg->buf, msg->len);
 695                }
 696                if (ret) {
 697                        debug("i2c_write: error sending\n");
 698                        return -EREMOTEIO;
 699                }
 700        }
 701
 702        return 0;
 703}
 704
 705static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 706{
 707        struct dw_i2c *i2c = dev_get_priv(bus);
 708        ulong rate;
 709
 710#if CONFIG_IS_ENABLED(CLK)
 711        rate = clk_get_rate(&i2c->clk);
 712        if (IS_ERR_VALUE(rate))
 713                return log_ret(-EINVAL);
 714#else
 715        rate = IC_CLK;
 716#endif
 717        return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 718}
 719
 720static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 721                                     uint chip_flags)
 722{
 723        struct dw_i2c *i2c = dev_get_priv(bus);
 724        struct i2c_regs *i2c_base = i2c->regs;
 725        u32 tmp;
 726        int ret;
 727
 728        /* Try to read the first location of the chip */
 729        ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 730        if (ret)
 731                __dw_i2c_init(i2c_base, 0, 0);
 732
 733        return ret;
 734}
 735
 736int designware_i2c_of_to_plat(struct udevice *bus)
 737{
 738        struct dw_i2c *priv = dev_get_priv(bus);
 739        int ret;
 740
 741        if (!priv->regs)
 742                priv->regs = dev_read_addr_ptr(bus);
 743        dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 744        dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 745        dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 746
 747        ret = reset_get_bulk(bus, &priv->resets);
 748        if (ret) {
 749                if (ret != -ENOTSUPP)
 750                        dev_warn(bus, "Can't get reset: %d\n", ret);
 751        } else {
 752                reset_deassert_bulk(&priv->resets);
 753        }
 754
 755#if CONFIG_IS_ENABLED(CLK)
 756        ret = clk_get_by_index(bus, 0, &priv->clk);
 757        if (ret)
 758                return ret;
 759
 760        ret = clk_enable(&priv->clk);
 761        if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 762                clk_free(&priv->clk);
 763                dev_err(bus, "failed to enable clock\n");
 764                return ret;
 765        }
 766#endif
 767
 768        return 0;
 769}
 770
 771int designware_i2c_probe(struct udevice *bus)
 772{
 773        struct dw_i2c *priv = dev_get_priv(bus);
 774        uint comp_type;
 775
 776        comp_type = readl(&priv->regs->comp_type);
 777        if (comp_type != DW_I2C_COMP_TYPE) {
 778                log_err("I2C bus %s has unknown type %#x\n", bus->name,
 779                        comp_type);
 780                return -ENXIO;
 781        }
 782
 783        log_debug("I2C bus %s version %#x\n", bus->name,
 784                  readl(&priv->regs->comp_version));
 785
 786        return __dw_i2c_init(priv->regs, 0, 0);
 787}
 788
 789int designware_i2c_remove(struct udevice *dev)
 790{
 791        struct dw_i2c *priv = dev_get_priv(dev);
 792
 793#if CONFIG_IS_ENABLED(CLK)
 794        clk_disable(&priv->clk);
 795        clk_free(&priv->clk);
 796#endif
 797
 798        return reset_release_bulk(&priv->resets);
 799}
 800
 801const struct dm_i2c_ops designware_i2c_ops = {
 802        .xfer           = designware_i2c_xfer,
 803        .probe_chip     = designware_i2c_probe_chip,
 804        .set_bus_speed  = designware_i2c_set_bus_speed,
 805};
 806
 807static const struct udevice_id designware_i2c_ids[] = {
 808        { .compatible = "snps,designware-i2c" },
 809        { }
 810};
 811
 812U_BOOT_DRIVER(i2c_designware) = {
 813        .name   = "i2c_designware",
 814        .id     = UCLASS_I2C,
 815        .of_match = designware_i2c_ids,
 816        .of_to_plat = designware_i2c_of_to_plat,
 817        .probe  = designware_i2c_probe,
 818        .priv_auto      = sizeof(struct dw_i2c),
 819        .remove = designware_i2c_remove,
 820        .flags  = DM_FLAG_OS_PREPARE,
 821        .ops    = &designware_i2c_ops,
 822};
 823
 824#endif /* CONFIG_DM_I2C */
 825