LXR uboot/drivers/i2c/qup

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2014, Sony Mobile Communications AB.
   5 * Copyright (c) 2022-2023, Sumit Garg <sumit.garg@linaro.org>
   6 *
   7 * Inspired by corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c
   8 */
   9
  10#include <init.h>
  11#include <env.h>
  12#include <common.h>
  13#include <log.h>
  14#include <dm/device_compat.h>
  15#include <linux/delay.h>
  16#include <linux/errno.h>
  17#include <linux/err.h>
  18#include <linux/compat.h>
  19#include <linux/bitops.h>
  20#include <asm/io.h>
  21#include <i2c.h>
  22#include <watchdog.h>
  23#include <fdtdec.h>
  24#include <clk.h>
  25#include <reset.h>
  26#include <asm/arch/gpio.h>
  27#include <cpu_func.h>
  28#include <asm/system.h>
  29#include <asm/gpio.h>
  30#include <dm.h>
  31#include <dm/pinctrl.h>
  32
  33/* QUP Registers */
  34#define QUP_CONFIG                              0x000
  35#define QUP_STATE                               0x004
  36#define QUP_IO_MODE                             0x008
  37#define QUP_SW_RESET                            0x00c
  38#define QUP_OPERATIONAL                         0x018
  39#define QUP_ERROR_FLAGS                         0x01c /* NOT USED */
  40#define QUP_ERROR_FLAGS_EN                      0x020 /* NOT USED */
  41#define QUP_TEST_CTRL                           0x024 /* NOT USED */
  42#define QUP_OPERATIONAL_MASK                    0x028 /* NOT USED */
  43#define QUP_HW_VERSION                          0x030
  44#define QUP_MX_OUTPUT_CNT                       0x100
  45#define QUP_OUT_DEBUG                           0x108 /* NOT USED */
  46#define QUP_OUT_FIFO_CNT                        0x10C /* NOT USED */
  47#define QUP_OUT_FIFO_BASE                       0x110
  48#define QUP_MX_WRITE_CNT                        0x150
  49#define QUP_MX_INPUT_CNT                        0x200
  50#define QUP_MX_READ_CNT                         0x208
  51#define QUP_IN_READ_CUR                         0x20C /* NOT USED */
  52#define QUP_IN_DEBUG                            0x210 /* NOT USED */
  53#define QUP_IN_FIFO_CNT                         0x214 /* NOT USED */
  54#define QUP_IN_FIFO_BASE                        0x218
  55#define QUP_I2C_CLK_CTL                         0x400
  56#define QUP_I2C_STATUS                          0x404 /* NOT USED */
  57#define QUP_I2C_MASTER_GEN                      0x408
  58#define QUP_I2C_MASTER_BUS_CLR                  0x40C /* NOT USED */
  59
  60/* QUP States and reset values */
  61#define QUP_RESET_STATE                         0
  62#define QUP_RUN_STATE                           1
  63#define QUP_PAUSE_STATE                         3
  64#define QUP_STATE_MASK                          3
  65
  66#define QUP_STATE_VALID                         BIT(2)
  67#define QUP_I2C_MAST_GEN                        BIT(4)
  68#define QUP_I2C_FLUSH                           BIT(6)
  69
  70#define QUP_OPERATIONAL_RESET                   0x000ff0
  71#define QUP_I2C_STATUS_RESET                    0xfffffc
  72
  73/* QUP OPERATIONAL FLAGS */
  74#define QUP_I2C_NACK_FLAG                       BIT(3)
  75#define QUP_OUT_NOT_EMPTY                       BIT(4)
  76#define QUP_IN_NOT_EMPTY                        BIT(5)
  77#define QUP_OUT_FULL                            BIT(6)
  78#define QUP_OUT_SVC_FLAG                        BIT(8)
  79#define QUP_IN_SVC_FLAG                         BIT(9)
  80#define QUP_MX_OUTPUT_DONE                      BIT(10)
  81#define QUP_MX_INPUT_DONE                       BIT(11)
  82#define OUT_BLOCK_WRITE_REQ                     BIT(12)
  83#define IN_BLOCK_READ_REQ                       BIT(13)
  84
  85/*
  86 * QUP engine acting as I2C controller is referred to as
  87 * I2C mini core, following are related macros.
  88 */
  89#define QUP_NO_OUTPUT                           BIT(6)
  90#define QUP_NO_INPUT                            BIT(7)
  91#define QUP_CLOCK_AUTO_GATE                     BIT(13)
  92#define QUP_I2C_MINI_CORE                       (2 << 8)
  93#define QUP_I2C_N_VAL_V2                        7
  94
  95/* Packing/Unpacking words in FIFOs, and IO modes */
  96#define QUP_OUTPUT_BLK_MODE                     BIT(10)
  97#define QUP_OUTPUT_BAM_MODE                     (BIT(10) | BIT(11))
  98#define QUP_INPUT_BLK_MODE                      BIT(12)
  99#define QUP_INPUT_BAM_MODE                      (BIT(12) | BIT(13))
 100#define QUP_BAM_MODE                            (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
 101#define QUP_BLK_MODE                            (QUP_OUTPUT_BLK_MODE | QUP_INPUT_BLK_MODE)
 102#define QUP_UNPACK_EN                           BIT(14)
 103#define QUP_PACK_EN                             BIT(15)
 104
 105#define QUP_REPACK_EN                           (QUP_UNPACK_EN | QUP_PACK_EN)
 106#define QUP_V2_TAGS_EN                          1
 107
 108#define QUP_OUTPUT_BLOCK_SIZE(x)                (((x) >> 0) & 0x03)
 109#define QUP_OUTPUT_FIFO_SIZE(x)                 (((x) >> 2) & 0x07)
 110#define QUP_INPUT_BLOCK_SIZE(x)                 (((x) >> 5) & 0x03)
 111#define QUP_INPUT_FIFO_SIZE(x)                  (((x) >> 7) & 0x07)
 112
 113/* QUP v2 tags */
 114#define QUP_TAG_V2_START                        0x81
 115#define QUP_TAG_V2_DATAWR                       0x82
 116#define QUP_TAG_V2_DATAWR_STOP                  0x83
 117#define QUP_TAG_V2_DATARD                       0x85
 118#define QUP_TAG_V2_DATARD_NACK                  0x86
 119#define QUP_TAG_V2_DATARD_STOP                  0x87
 120
 121#define QUP_I2C_MX_CONFIG_DURING_RUN            BIT(31)
 122
 123/* Minimum transfer timeout for i2c transfers in micro seconds */
 124#define TOUT_CNT                                (2 * 1000 * 1000)
 125
 126/* Default values. Use these if FW query fails */
 127#define DEFAULT_CLK_FREQ                        I2C_SPEED_STANDARD_RATE
 128#define DEFAULT_SRC_CLK                         19200000
 129
 130/*
 131 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
 132 * data transfer
 133 */
 134#define QUP_MAX_TAGS_LEN                        4
 135/* Max data length for each DATARD tags */
 136#define RECV_MAX_DATA_LEN                       254
 137/* TAG length for DATA READ in RX FIFO */
 138#define READ_RX_TAGS_LEN                        2
 139
 140struct qup_i2c_priv {
 141        phys_addr_t base;
 142        struct clk core;
 143        struct clk iface;
 144        u32 in_fifo_sz;
 145        u32 out_fifo_sz;
 146        u32 clk_ctl;
 147        u32 config_run;
 148};
 149
 150static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
 151{
 152        return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
 153}
 154
 155static int qup_i2c_poll_state_mask(struct qup_i2c_priv *qup,
 156                                   u32 req_state, u32 req_mask)
 157{
 158        int retries = 1;
 159        u32 state;
 160
 161        /*
 162         * State transition takes 3 AHB clocks cycles + 3 I2C master clock
 163         * cycles. So retry once after a 1uS delay.
 164         */
 165        do {
 166                state = readl(qup->base + QUP_STATE);
 167
 168                if (state & QUP_STATE_VALID &&
 169                    (state & req_mask) == req_state)
 170                        return 0;
 171
 172                udelay(1);
 173        } while (retries--);
 174
 175        return -ETIMEDOUT;
 176}
 177
 178static int qup_i2c_poll_state(struct qup_i2c_priv *qup, u32 req_state)
 179{
 180        return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
 181}
 182
 183static int qup_i2c_poll_state_valid(struct qup_i2c_priv *qup)
 184{
 185        return qup_i2c_poll_state_mask(qup, 0, 0);
 186}
 187
 188static int qup_i2c_poll_state_i2c_master(struct qup_i2c_priv *qup)
 189{
 190        return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
 191}
 192
 193static int qup_i2c_change_state(struct qup_i2c_priv *qup, u32 state)
 194{
 195        if (qup_i2c_poll_state_valid(qup) != 0)
 196                return -EIO;
 197
 198        writel(state, qup->base + QUP_STATE);
 199
 200        if (qup_i2c_poll_state(qup, state) != 0)
 201                return -EIO;
 202        return 0;
 203}
 204
 205/*
 206 * Function to check wheather Input or Output FIFO
 207 * has data to be serviced
 208 */
 209static int qup_i2c_check_fifo_status(struct qup_i2c_priv *qup, u32 reg_addr,
 210                                     u32 flags)
 211{
 212        unsigned long count = TOUT_CNT;
 213        u32 val, status_flag;
 214        int ret = 0;
 215
 216        do {
 217                val = readl(qup->base + reg_addr);
 218                status_flag = val & flags;
 219
 220                if (!count) {
 221                        printf("%s, timeout\n", __func__);
 222                        ret = -ETIMEDOUT;
 223                        break;
 224                }
 225
 226                count--;
 227                udelay(1);
 228        } while (!status_flag);
 229
 230        return ret;
 231}
 232
 233/*
 234 * Function to configure Input and Output enable/disable
 235 */
 236static void qup_i2c_enable_io_config(struct qup_i2c_priv *qup, u32 write_cnt,
 237                                     u32 read_cnt)
 238{
 239        u32 qup_config = QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2;
 240
 241        writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT);
 242
 243        if (read_cnt)
 244                writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT);
 245        else
 246                qup_config |= QUP_NO_INPUT;
 247
 248        writel(qup_config, qup->base + QUP_CONFIG);
 249}
 250
 251static unsigned int qup_i2c_read_word(struct qup_i2c_priv *qup)
 252{
 253        return readl(qup->base + QUP_IN_FIFO_BASE);
 254}
 255
 256static void qup_i2c_write_word(struct qup_i2c_priv *qup, u32 word)
 257{
 258        writel(word, qup->base + QUP_OUT_FIFO_BASE);
 259}
 260
 261static int qup_i2c_blsp_read(struct qup_i2c_priv *qup, unsigned int addr,
 262                             bool last, u8 *buffer, unsigned int bytes)
 263{
 264        unsigned int i, j, word;
 265        int ret = 0;
 266
 267        /* FIFO mode size limitation, for larger size implement block mode */
 268        if (bytes > (qup->in_fifo_sz - READ_RX_TAGS_LEN))
 269                return -EINVAL;
 270
 271        qup_i2c_enable_io_config(qup, QUP_MAX_TAGS_LEN,
 272                                 bytes + READ_RX_TAGS_LEN);
 273
 274        if (last)
 275                qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 276                                        QUP_TAG_V2_DATARD_STOP << 16 |
 277                                        bytes << 24);
 278        else
 279                qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 280                                        QUP_TAG_V2_DATARD << 16 | bytes << 24);
 281
 282        ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 283        if (ret)
 284                return ret;
 285
 286        ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
 287        if (ret)
 288                return ret;
 289        writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 290
 291        ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_IN_SVC_FLAG);
 292        if (ret)
 293                return ret;
 294        writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 295
 296        word = qup_i2c_read_word(qup);
 297        *(buffer++) = (word >> (8 * READ_RX_TAGS_LEN)) & 0xff;
 298        if (bytes > 1)
 299                *(buffer++) = (word >> (8 * (READ_RX_TAGS_LEN + 1))) & 0xff;
 300
 301        for (i = 2; i < bytes; i += 4) {
 302                word = qup_i2c_read_word(qup);
 303
 304                for (j = 0; j < 4; j++) {
 305                        if ((i + j) == bytes)
 306                                break;
 307                        *buffer = (word >> (j * 8)) & 0xff;
 308                        buffer++;
 309                }
 310        }
 311
 312        ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 313        return ret;
 314}
 315
 316static int qup_i2c_blsp_write(struct qup_i2c_priv *qup, unsigned int addr,
 317                              bool first, bool last, const u8 *buffer,
 318                              unsigned int bytes)
 319{
 320        unsigned int i;
 321        u32 word = 0;
 322        int ret = 0;
 323
 324        /* FIFO mode size limitation, for larger size implement block mode */
 325        if (bytes > (qup->out_fifo_sz - QUP_MAX_TAGS_LEN))
 326                return -EINVAL;
 327
 328        qup_i2c_enable_io_config(qup, bytes + QUP_MAX_TAGS_LEN, 0);
 329
 330        if (first) {
 331                ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 332                if (ret)
 333                        return ret;
 334
 335                writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 336
 337                ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 338                if (ret)
 339                        return ret;
 340        }
 341
 342        if (last)
 343                qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 344                                        QUP_TAG_V2_DATAWR_STOP << 16 |
 345                                        bytes << 24);
 346        else
 347                qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
 348                                        QUP_TAG_V2_DATAWR << 16 | bytes << 24);
 349
 350        for (i = 0; i < bytes; i++) {
 351                /* Write the byte of data */
 352                word |= *buffer << ((i % 4) * 8);
 353                if ((i % 4) == 3) {
 354                        qup_i2c_write_word(qup, word);
 355                        word = 0;
 356                }
 357                buffer++;
 358        }
 359
 360        if ((i % 4) != 0)
 361                qup_i2c_write_word(qup, word);
 362
 363        ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 364        if (ret)
 365                return ret;
 366
 367        ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
 368        if (ret)
 369                return ret;
 370        writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 371
 372        ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 373        return ret;
 374}
 375
 376static void qup_i2c_conf_mode_v2(struct qup_i2c_priv *qup)
 377{
 378        u32 io_mode = QUP_REPACK_EN;
 379
 380        writel(0, qup->base + QUP_MX_OUTPUT_CNT);
 381        writel(0, qup->base + QUP_MX_INPUT_CNT);
 382
 383        writel(io_mode, qup->base + QUP_IO_MODE);
 384}
 385
 386static int qup_i2c_xfer_v2(struct udevice *bus, struct i2c_msg msgs[], int num)
 387{
 388        struct qup_i2c_priv *qup = dev_get_priv(bus);
 389        int ret, idx = 0;
 390        u32 i2c_addr;
 391
 392        writel(1, qup->base + QUP_SW_RESET);
 393        ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
 394        if (ret)
 395                goto out;
 396
 397        /* Configure QUP as I2C mini core */
 398        writel(QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2 | QUP_NO_INPUT,
 399               qup->base + QUP_CONFIG);
 400        writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
 401
 402        if (qup_i2c_poll_state_i2c_master(qup)) {
 403                ret = -EIO;
 404                goto out;
 405        }
 406
 407        qup_i2c_conf_mode_v2(qup);
 408
 409        for (idx = 0; idx < num; idx++) {
 410                struct i2c_msg *m = &msgs[idx];
 411
 412                qup->config_run = !idx ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
 413                i2c_addr = i2c_8bit_addr_from_msg(m);
 414
 415                if (m->flags & I2C_M_RD)
 416                        ret = qup_i2c_blsp_read(qup, i2c_addr, idx == (num - 1),
 417                                                m->buf, m->len);
 418                else
 419                        ret = qup_i2c_blsp_write(qup, i2c_addr, idx == 0,
 420                                                 idx == (num - 1), m->buf,
 421                                                 m->len);
 422                if (ret)
 423                        break;
 424        }
 425out:
 426        qup_i2c_change_state(qup, QUP_RESET_STATE);
 427        return ret;
 428}
 429
 430static int qup_i2c_enable_clocks(struct udevice *dev, struct qup_i2c_priv *qup)
 431{
 432        int ret;
 433
 434        ret = clk_enable(&qup->core);
 435        if (ret) {
 436                dev_err(dev, "clk_enable failed %d\n", ret);
 437                return ret;
 438        }
 439
 440        ret = clk_enable(&qup->iface);
 441        if (ret) {
 442                dev_err(dev, "clk_enable failed %d\n", ret);
 443                return ret;
 444        }
 445
 446        return 0;
 447}
 448
 449static int qup_i2c_probe(struct udevice *dev)
 450{
 451        static const int blk_sizes[] = {4, 16, 32};
 452        struct qup_i2c_priv *qup = dev_get_priv(dev);
 453        u32 io_mode, hw_ver, size, size_idx;
 454        int ret;
 455
 456        qup->base = (phys_addr_t)dev_read_addr_ptr(dev);
 457        if (!qup->base)
 458                return -EINVAL;
 459
 460        ret = clk_get_by_name(dev, "core", &qup->core);
 461        if (ret) {
 462                pr_err("clk_get_by_name(core) failed: %d\n", ret);
 463                return ret;
 464        }
 465        ret = clk_get_by_name(dev, "iface", &qup->iface);
 466        if (ret) {
 467                pr_err("clk_get_by_name(iface) failed: %d\n", ret);
 468                return ret;
 469        }
 470        qup_i2c_enable_clocks(dev, qup);
 471
 472        writel(1, qup->base + QUP_SW_RESET);
 473        ret = qup_i2c_poll_state_valid(qup);
 474        if (ret)
 475                return ret;
 476
 477        hw_ver = readl(qup->base + QUP_HW_VERSION);
 478        dev_dbg(dev, "Revision %x\n", hw_ver);
 479
 480        io_mode = readl(qup->base + QUP_IO_MODE);
 481
 482        /*
 483         * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
 484         * associated with each byte written/received
 485         */
 486        size_idx = QUP_OUTPUT_BLOCK_SIZE(io_mode);
 487        if (size_idx >= ARRAY_SIZE(blk_sizes)) {
 488                ret = -EIO;
 489                return ret;
 490        }
 491        size = QUP_OUTPUT_FIFO_SIZE(io_mode);
 492        qup->out_fifo_sz = blk_sizes[size_idx] * (2 << size);
 493
 494        size_idx = QUP_INPUT_BLOCK_SIZE(io_mode);
 495        if (size_idx >= ARRAY_SIZE(blk_sizes)) {
 496                ret = -EIO;
 497                return ret;
 498        }
 499        size = QUP_INPUT_FIFO_SIZE(io_mode);
 500        qup->in_fifo_sz = blk_sizes[size_idx] * (2 << size);
 501
 502        dev_dbg(dev, "IN:fifo:%d, OUT:fifo:%d\n", qup->in_fifo_sz,
 503                qup->out_fifo_sz);
 504
 505        return 0;
 506}
 507
 508static int qup_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq)
 509{
 510        struct qup_i2c_priv *qup = dev_get_priv(dev);
 511        unsigned int src_clk_freq;
 512        int fs_div, hs_div;
 513
 514        /* We support frequencies up to FAST Mode Plus (1MHz) */
 515        if (!clk_freq || clk_freq > I2C_SPEED_FAST_PLUS_RATE) {
 516                dev_err(dev, "clock frequency not supported %d\n", clk_freq);
 517                return -EINVAL;
 518        }
 519
 520        src_clk_freq = clk_get_rate(&qup->iface);
 521        if ((int)src_clk_freq < 0) {
 522                src_clk_freq = DEFAULT_SRC_CLK;
 523                dev_dbg(dev, "using default core freq %d\n", src_clk_freq);
 524        }
 525
 526        dev_dbg(dev, "src_clk_freq %u\n", src_clk_freq);
 527        dev_dbg(dev, "clk_freq     %u\n", clk_freq);
 528
 529        hs_div = 3;
 530        if (clk_freq <= I2C_SPEED_STANDARD_RATE) {
 531                fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
 532                qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
 533        } else {
 534                /* 33%/66% duty cycle */
 535                fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
 536                qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
 537        }
 538
 539        dev_dbg(dev, "clk_ctl      %u\n", qup->clk_ctl);
 540
 541        return 0;
 542}
 543
 544/* Probe to see if a chip is present. */
 545static int qup_i2c_probe_chip(struct udevice *dev, uint chip_addr,
 546                              uint chip_flags)
 547{
 548        struct qup_i2c_priv *qup = dev_get_priv(dev);
 549        u32 hw_ver = readl(qup->base + QUP_HW_VERSION);
 550
 551        return hw_ver ? 0 : -1;
 552}
 553
 554static const struct dm_i2c_ops qup_i2c_ops = {
 555        .xfer           = qup_i2c_xfer_v2,
 556        .probe_chip     = qup_i2c_probe_chip,
 557        .set_bus_speed  = qup_i2c_set_bus_speed,
 558};
 559
 560/*
 561 * Currently this driver only supports v2.x of QUP I2C controller, hence
 562 * functions above are named with a _v2 suffix. So when we have the
 563 * v1.1.1 support added as per the Linux counterpart then it should be easy
 564 * to add corresponding functions named with a _v1 suffix.
 565 */
 566static const struct udevice_id qup_i2c_ids[] = {
 567        { .compatible = "qcom,i2c-qup-v2.1.1" },
 568        { .compatible = "qcom,i2c-qup-v2.2.1" },
 569        {}
 570};
 571
 572U_BOOT_DRIVER(i2c_qup) = {
 573        .name   = "i2c_qup",
 574        .id     = UCLASS_I2C,
 575        .of_match = qup_i2c_ids,
 576        .probe  = qup_i2c_probe,
 577        .priv_auto = sizeof(struct qup_i2c_priv),
 578        .ops    = &qup_i2c_ops,
 579};
 580