1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#include <common.h>
33#include <command.h>
34#include <cpu_func.h>
35#include <dm.h>
36#include <errno.h>
37#include <log.h>
38#include <malloc.h>
39#include <memalign.h>
40#include <net.h>
41#include <pci.h>
42#include <linux/delay.h>
43#include "e1000.h"
44#include <asm/cache.h>
45
46#define TOUT_LOOP 100000
47
48#define E1000_DEFAULT_PCI_PBA 0x00000030
49#define E1000_DEFAULT_PCIE_PBA 0x000a0026
50
51
52
53
54#define E1000_BUFFER_ALIGN 128
55
56
57
58
59
60
61
62DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
63DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
64DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
65
66static int tx_tail;
67static int rx_tail, rx_last;
68static int num_cards;
69
70static struct pci_device_id e1000_supported[] = {
71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
88
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
117 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
118 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
119
120 {}
121};
122
123
124static int e1000_setup_link(struct e1000_hw *hw);
125static int e1000_setup_fiber_link(struct e1000_hw *hw);
126static int e1000_setup_copper_link(struct e1000_hw *hw);
127static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
128static void e1000_config_collision_dist(struct e1000_hw *hw);
129static int e1000_config_mac_to_phy(struct e1000_hw *hw);
130static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
131static int e1000_check_for_link(struct e1000_hw *hw);
132static int e1000_wait_autoneg(struct e1000_hw *hw);
133static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
134 uint16_t * duplex);
135static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
136 uint16_t * phy_data);
137static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
138 uint16_t phy_data);
139static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
140static int e1000_phy_reset(struct e1000_hw *hw);
141static int e1000_detect_gig_phy(struct e1000_hw *hw);
142static void e1000_set_media_type(struct e1000_hw *hw);
143
144static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
145static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
146static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
147
148#ifndef CONFIG_E1000_NO_NVM
149static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
150static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
151static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
152 uint16_t words,
153 uint16_t *data);
154
155
156
157
158
159
160void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
161{
162
163
164
165 *eecd = *eecd | E1000_EECD_SK;
166 E1000_WRITE_REG(hw, EECD, *eecd);
167 E1000_WRITE_FLUSH(hw);
168 udelay(50);
169}
170
171
172
173
174
175
176
177void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
178{
179
180
181
182 *eecd = *eecd & ~E1000_EECD_SK;
183 E1000_WRITE_REG(hw, EECD, *eecd);
184 E1000_WRITE_FLUSH(hw);
185 udelay(50);
186}
187
188
189
190
191
192
193
194
195static void
196e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
197{
198 uint32_t eecd;
199 uint32_t mask;
200
201
202
203
204
205 mask = 0x01 << (count - 1);
206 eecd = E1000_READ_REG(hw, EECD);
207 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
208 do {
209
210
211
212
213
214 eecd &= ~E1000_EECD_DI;
215
216 if (data & mask)
217 eecd |= E1000_EECD_DI;
218
219 E1000_WRITE_REG(hw, EECD, eecd);
220 E1000_WRITE_FLUSH(hw);
221
222 udelay(50);
223
224 e1000_raise_ee_clk(hw, &eecd);
225 e1000_lower_ee_clk(hw, &eecd);
226
227 mask = mask >> 1;
228
229 } while (mask);
230
231
232 eecd &= ~E1000_EECD_DI;
233 E1000_WRITE_REG(hw, EECD, eecd);
234}
235
236
237
238
239
240
241static uint16_t
242e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
243{
244 uint32_t eecd;
245 uint32_t i;
246 uint16_t data;
247
248
249
250
251
252
253
254
255 eecd = E1000_READ_REG(hw, EECD);
256
257 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
258 data = 0;
259
260 for (i = 0; i < count; i++) {
261 data = data << 1;
262 e1000_raise_ee_clk(hw, &eecd);
263
264 eecd = E1000_READ_REG(hw, EECD);
265
266 eecd &= ~(E1000_EECD_DI);
267 if (eecd & E1000_EECD_DO)
268 data |= 1;
269
270 e1000_lower_ee_clk(hw, &eecd);
271 }
272
273 return data;
274}
275
276
277
278
279
280
281void e1000_standby_eeprom(struct e1000_hw *hw)
282{
283 struct e1000_eeprom_info *eeprom = &hw->eeprom;
284 uint32_t eecd;
285
286 eecd = E1000_READ_REG(hw, EECD);
287
288 if (eeprom->type == e1000_eeprom_microwire) {
289 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
290 E1000_WRITE_REG(hw, EECD, eecd);
291 E1000_WRITE_FLUSH(hw);
292 udelay(eeprom->delay_usec);
293
294
295 eecd |= E1000_EECD_SK;
296 E1000_WRITE_REG(hw, EECD, eecd);
297 E1000_WRITE_FLUSH(hw);
298 udelay(eeprom->delay_usec);
299
300
301 eecd |= E1000_EECD_CS;
302 E1000_WRITE_REG(hw, EECD, eecd);
303 E1000_WRITE_FLUSH(hw);
304 udelay(eeprom->delay_usec);
305
306
307 eecd &= ~E1000_EECD_SK;
308 E1000_WRITE_REG(hw, EECD, eecd);
309 E1000_WRITE_FLUSH(hw);
310 udelay(eeprom->delay_usec);
311 } else if (eeprom->type == e1000_eeprom_spi) {
312
313 eecd |= E1000_EECD_CS;
314 E1000_WRITE_REG(hw, EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 udelay(eeprom->delay_usec);
317 eecd &= ~E1000_EECD_CS;
318 E1000_WRITE_REG(hw, EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 udelay(eeprom->delay_usec);
321 }
322}
323
324
325
326
327
328
329static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
330{
331 uint32_t eecd = 0;
332
333 DEBUGFUNC();
334
335 if (hw->mac_type == e1000_ich8lan)
336 return false;
337
338 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
339 eecd = E1000_READ_REG(hw, EECD);
340
341
342 eecd = ((eecd >> 15) & 0x03);
343
344
345 if (eecd == 0x03)
346 return false;
347 }
348 return true;
349}
350
351
352
353
354
355
356
357
358
359int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
360{
361 struct e1000_eeprom_info *eeprom = &hw->eeprom;
362 uint32_t eecd, i = 0;
363
364 DEBUGFUNC();
365
366 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
367 return -E1000_ERR_SWFW_SYNC;
368 eecd = E1000_READ_REG(hw, EECD);
369
370 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
371
372 if (hw->mac_type > e1000_82544) {
373 eecd |= E1000_EECD_REQ;
374 E1000_WRITE_REG(hw, EECD, eecd);
375 eecd = E1000_READ_REG(hw, EECD);
376 while ((!(eecd & E1000_EECD_GNT)) &&
377 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
378 i++;
379 udelay(5);
380 eecd = E1000_READ_REG(hw, EECD);
381 }
382 if (!(eecd & E1000_EECD_GNT)) {
383 eecd &= ~E1000_EECD_REQ;
384 E1000_WRITE_REG(hw, EECD, eecd);
385 DEBUGOUT("Could not acquire EEPROM grant\n");
386 return -E1000_ERR_EEPROM;
387 }
388 }
389 }
390
391
392
393 if (eeprom->type == e1000_eeprom_microwire) {
394
395 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
396 E1000_WRITE_REG(hw, EECD, eecd);
397
398
399 eecd |= E1000_EECD_CS;
400 E1000_WRITE_REG(hw, EECD, eecd);
401 } else if (eeprom->type == e1000_eeprom_spi) {
402
403 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404 E1000_WRITE_REG(hw, EECD, eecd);
405 udelay(1);
406 }
407
408 return E1000_SUCCESS;
409}
410
411
412
413
414
415
416
417
418static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
419{
420 struct e1000_eeprom_info *eeprom = &hw->eeprom;
421 uint32_t eecd;
422 int32_t ret_val = E1000_SUCCESS;
423 uint16_t eeprom_size;
424
425 if (hw->mac_type == e1000_igb)
426 eecd = E1000_READ_REG(hw, I210_EECD);
427 else
428 eecd = E1000_READ_REG(hw, EECD);
429
430 DEBUGFUNC();
431
432 switch (hw->mac_type) {
433 case e1000_82542_rev2_0:
434 case e1000_82542_rev2_1:
435 case e1000_82543:
436 case e1000_82544:
437 eeprom->type = e1000_eeprom_microwire;
438 eeprom->word_size = 64;
439 eeprom->opcode_bits = 3;
440 eeprom->address_bits = 6;
441 eeprom->delay_usec = 50;
442 eeprom->use_eerd = false;
443 eeprom->use_eewr = false;
444 break;
445 case e1000_82540:
446 case e1000_82545:
447 case e1000_82545_rev_3:
448 case e1000_82546:
449 case e1000_82546_rev_3:
450 eeprom->type = e1000_eeprom_microwire;
451 eeprom->opcode_bits = 3;
452 eeprom->delay_usec = 50;
453 if (eecd & E1000_EECD_SIZE) {
454 eeprom->word_size = 256;
455 eeprom->address_bits = 8;
456 } else {
457 eeprom->word_size = 64;
458 eeprom->address_bits = 6;
459 }
460 eeprom->use_eerd = false;
461 eeprom->use_eewr = false;
462 break;
463 case e1000_82541:
464 case e1000_82541_rev_2:
465 case e1000_82547:
466 case e1000_82547_rev_2:
467 if (eecd & E1000_EECD_TYPE) {
468 eeprom->type = e1000_eeprom_spi;
469 eeprom->opcode_bits = 8;
470 eeprom->delay_usec = 1;
471 if (eecd & E1000_EECD_ADDR_BITS) {
472 eeprom->page_size = 32;
473 eeprom->address_bits = 16;
474 } else {
475 eeprom->page_size = 8;
476 eeprom->address_bits = 8;
477 }
478 } else {
479 eeprom->type = e1000_eeprom_microwire;
480 eeprom->opcode_bits = 3;
481 eeprom->delay_usec = 50;
482 if (eecd & E1000_EECD_ADDR_BITS) {
483 eeprom->word_size = 256;
484 eeprom->address_bits = 8;
485 } else {
486 eeprom->word_size = 64;
487 eeprom->address_bits = 6;
488 }
489 }
490 eeprom->use_eerd = false;
491 eeprom->use_eewr = false;
492 break;
493 case e1000_82571:
494 case e1000_82572:
495 eeprom->type = e1000_eeprom_spi;
496 eeprom->opcode_bits = 8;
497 eeprom->delay_usec = 1;
498 if (eecd & E1000_EECD_ADDR_BITS) {
499 eeprom->page_size = 32;
500 eeprom->address_bits = 16;
501 } else {
502 eeprom->page_size = 8;
503 eeprom->address_bits = 8;
504 }
505 eeprom->use_eerd = false;
506 eeprom->use_eewr = false;
507 break;
508 case e1000_82573:
509 case e1000_82574:
510 eeprom->type = e1000_eeprom_spi;
511 eeprom->opcode_bits = 8;
512 eeprom->delay_usec = 1;
513 if (eecd & E1000_EECD_ADDR_BITS) {
514 eeprom->page_size = 32;
515 eeprom->address_bits = 16;
516 } else {
517 eeprom->page_size = 8;
518 eeprom->address_bits = 8;
519 }
520 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
521 eeprom->use_eerd = true;
522 eeprom->use_eewr = true;
523
524 eeprom->type = e1000_eeprom_flash;
525 eeprom->word_size = 2048;
526
527
528
529 eecd &= ~E1000_EECD_AUPDEN;
530 E1000_WRITE_REG(hw, EECD, eecd);
531 }
532 break;
533 case e1000_80003es2lan:
534 eeprom->type = e1000_eeprom_spi;
535 eeprom->opcode_bits = 8;
536 eeprom->delay_usec = 1;
537 if (eecd & E1000_EECD_ADDR_BITS) {
538 eeprom->page_size = 32;
539 eeprom->address_bits = 16;
540 } else {
541 eeprom->page_size = 8;
542 eeprom->address_bits = 8;
543 }
544 eeprom->use_eerd = true;
545 eeprom->use_eewr = false;
546 break;
547 case e1000_igb:
548
549 eeprom->type = e1000_eeprom_invm;
550 eeprom->opcode_bits = 8;
551 eeprom->delay_usec = 1;
552 eeprom->page_size = 32;
553 eeprom->address_bits = 16;
554 eeprom->use_eerd = true;
555 eeprom->use_eewr = false;
556 break;
557 default:
558 break;
559 }
560
561 if (eeprom->type == e1000_eeprom_spi ||
562 eeprom->type == e1000_eeprom_invm) {
563
564
565
566
567 if (hw->mac_type <= e1000_82547_rev_2) {
568
569 eeprom->word_size = 64;
570 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
571 &eeprom_size);
572 if (ret_val)
573 return ret_val;
574 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
575 >> EEPROM_SIZE_SHIFT;
576
577
578
579
580 if (eeprom_size)
581 eeprom_size++;
582 } else {
583 eeprom_size = (uint16_t)((eecd &
584 E1000_EECD_SIZE_EX_MASK) >>
585 E1000_EECD_SIZE_EX_SHIFT);
586 }
587
588 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
589 }
590 return ret_val;
591}
592
593
594
595
596
597
598static int32_t
599e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
600{
601 uint32_t attempts = 100000;
602 uint32_t i, reg = 0;
603 int32_t done = E1000_ERR_EEPROM;
604
605 for (i = 0; i < attempts; i++) {
606 if (eerd == E1000_EEPROM_POLL_READ) {
607 if (hw->mac_type == e1000_igb)
608 reg = E1000_READ_REG(hw, I210_EERD);
609 else
610 reg = E1000_READ_REG(hw, EERD);
611 } else {
612 if (hw->mac_type == e1000_igb)
613 reg = E1000_READ_REG(hw, I210_EEWR);
614 else
615 reg = E1000_READ_REG(hw, EEWR);
616 }
617
618 if (reg & E1000_EEPROM_RW_REG_DONE) {
619 done = E1000_SUCCESS;
620 break;
621 }
622 udelay(5);
623 }
624
625 return done;
626}
627
628
629
630
631
632
633
634
635
636static int32_t
637e1000_read_eeprom_eerd(struct e1000_hw *hw,
638 uint16_t offset,
639 uint16_t words,
640 uint16_t *data)
641{
642 uint32_t i, eerd = 0;
643 int32_t error = 0;
644
645 for (i = 0; i < words; i++) {
646 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
647 E1000_EEPROM_RW_REG_START;
648
649 if (hw->mac_type == e1000_igb)
650 E1000_WRITE_REG(hw, I210_EERD, eerd);
651 else
652 E1000_WRITE_REG(hw, EERD, eerd);
653
654 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
655
656 if (error)
657 break;
658
659 if (hw->mac_type == e1000_igb) {
660 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
661 E1000_EEPROM_RW_REG_DATA);
662 } else {
663 data[i] = (E1000_READ_REG(hw, EERD) >>
664 E1000_EEPROM_RW_REG_DATA);
665 }
666
667 }
668
669 return error;
670}
671
672void e1000_release_eeprom(struct e1000_hw *hw)
673{
674 uint32_t eecd;
675
676 DEBUGFUNC();
677
678 eecd = E1000_READ_REG(hw, EECD);
679
680 if (hw->eeprom.type == e1000_eeprom_spi) {
681 eecd |= E1000_EECD_CS;
682 eecd &= ~E1000_EECD_SK;
683
684 E1000_WRITE_REG(hw, EECD, eecd);
685
686 udelay(hw->eeprom.delay_usec);
687 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
688
689
690
691 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
692
693 E1000_WRITE_REG(hw, EECD, eecd);
694
695
696 eecd |= E1000_EECD_SK;
697 E1000_WRITE_REG(hw, EECD, eecd);
698 E1000_WRITE_FLUSH(hw);
699 udelay(hw->eeprom.delay_usec);
700
701
702 eecd &= ~E1000_EECD_SK;
703 E1000_WRITE_REG(hw, EECD, eecd);
704 E1000_WRITE_FLUSH(hw);
705 udelay(hw->eeprom.delay_usec);
706 }
707
708
709 if (hw->mac_type > e1000_82544) {
710 eecd &= ~E1000_EECD_REQ;
711 E1000_WRITE_REG(hw, EECD, eecd);
712 }
713
714 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
715}
716
717
718
719
720
721
722static int32_t
723e1000_spi_eeprom_ready(struct e1000_hw *hw)
724{
725 uint16_t retry_count = 0;
726 uint8_t spi_stat_reg;
727
728 DEBUGFUNC();
729
730
731
732
733
734
735 retry_count = 0;
736 do {
737 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
738 hw->eeprom.opcode_bits);
739 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
740 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
741 break;
742
743 udelay(5);
744 retry_count += 5;
745
746 e1000_standby_eeprom(hw);
747 } while (retry_count < EEPROM_MAX_RETRY_SPI);
748
749
750
751
752 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
753 DEBUGOUT("SPI EEPROM Status error\n");
754 return -E1000_ERR_EEPROM;
755 }
756
757 return E1000_SUCCESS;
758}
759
760
761
762
763
764
765
766
767static int32_t
768e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
769 uint16_t words, uint16_t *data)
770{
771 struct e1000_eeprom_info *eeprom = &hw->eeprom;
772 uint32_t i = 0;
773
774 DEBUGFUNC();
775
776
777 if (eeprom->word_size == 0)
778 e1000_init_eeprom_params(hw);
779
780
781
782
783 if ((offset >= eeprom->word_size) ||
784 (words > eeprom->word_size - offset) ||
785 (words == 0)) {
786 DEBUGOUT("\"words\" parameter out of bounds."
787 "Words = %d, size = %d\n", offset, eeprom->word_size);
788 return -E1000_ERR_EEPROM;
789 }
790
791
792
793
794
795 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
796 hw->eeprom.use_eerd == false) {
797
798
799 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
800 return -E1000_ERR_EEPROM;
801 }
802
803
804 if (eeprom->use_eerd == true)
805 return e1000_read_eeprom_eerd(hw, offset, words, data);
806
807
808
809 if (eeprom->type == e1000_eeprom_spi) {
810 uint16_t word_in;
811 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
812
813 if (e1000_spi_eeprom_ready(hw)) {
814 e1000_release_eeprom(hw);
815 return -E1000_ERR_EEPROM;
816 }
817
818 e1000_standby_eeprom(hw);
819
820
821
822 if ((eeprom->address_bits == 8) && (offset >= 128))
823 read_opcode |= EEPROM_A8_OPCODE_SPI;
824
825
826 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
827 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
828 eeprom->address_bits);
829
830
831
832
833
834
835
836 for (i = 0; i < words; i++) {
837 word_in = e1000_shift_in_ee_bits(hw, 16);
838 data[i] = (word_in >> 8) | (word_in << 8);
839 }
840 } else if (eeprom->type == e1000_eeprom_microwire) {
841 for (i = 0; i < words; i++) {
842
843 e1000_shift_out_ee_bits(hw,
844 EEPROM_READ_OPCODE_MICROWIRE,
845 eeprom->opcode_bits);
846 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
847 eeprom->address_bits);
848
849
850
851 data[i] = e1000_shift_in_ee_bits(hw, 16);
852 e1000_standby_eeprom(hw);
853 }
854 }
855
856
857 e1000_release_eeprom(hw);
858
859 return E1000_SUCCESS;
860}
861
862
863
864
865
866
867
868
869
870
871
872
873
874static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
875 uint16_t words, uint16_t *data)
876{
877 struct e1000_eeprom_info *eeprom = &hw->eeprom;
878 uint32_t i, k, eewr = 0;
879 uint32_t attempts = 100000;
880 int32_t ret_val = 0;
881
882
883
884
885 if ((offset >= eeprom->word_size) ||
886 (words > (eeprom->word_size - offset)) || (words == 0)) {
887 DEBUGOUT("nvm parameter(s) out of bounds\n");
888 ret_val = -E1000_ERR_EEPROM;
889 goto out;
890 }
891
892 for (i = 0; i < words; i++) {
893 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
894 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
895 E1000_EEPROM_RW_REG_START;
896
897 E1000_WRITE_REG(hw, I210_EEWR, eewr);
898
899 for (k = 0; k < attempts; k++) {
900 if (E1000_EEPROM_RW_REG_DONE &
901 E1000_READ_REG(hw, I210_EEWR)) {
902 ret_val = 0;
903 break;
904 }
905 udelay(5);
906 }
907
908 if (ret_val) {
909 DEBUGOUT("Shadow RAM write EEWR timed out\n");
910 break;
911 }
912 }
913
914out:
915 return ret_val;
916}
917
918
919
920
921
922
923static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
924{
925 int32_t ret_val = -E1000_ERR_EEPROM;
926 uint32_t i, reg;
927
928 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
929 reg = E1000_READ_REG(hw, EECD);
930 if (reg & E1000_EECD_FLUDONE_I210) {
931 ret_val = 0;
932 break;
933 }
934 udelay(5);
935 }
936
937 return ret_val;
938}
939
940
941
942
943
944
945static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
946{
947 int32_t ret_val = 0;
948 uint32_t flup;
949
950 ret_val = e1000_pool_flash_update_done_i210(hw);
951 if (ret_val == -E1000_ERR_EEPROM) {
952 DEBUGOUT("Flash update time out\n");
953 goto out;
954 }
955
956 flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
957 E1000_WRITE_REG(hw, EECD, flup);
958
959 ret_val = e1000_pool_flash_update_done_i210(hw);
960 if (ret_val)
961 DEBUGOUT("Flash update time out\n");
962 else
963 DEBUGOUT("Flash update complete\n");
964
965out:
966 return ret_val;
967}
968
969
970
971
972
973
974
975
976
977static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
978{
979 int32_t ret_val = 0;
980 uint16_t checksum = 0;
981 uint16_t i, nvm_data;
982
983
984
985
986
987 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
988 if (ret_val) {
989 DEBUGOUT("EEPROM read failed\n");
990 goto out;
991 }
992
993 if (!(e1000_get_hw_eeprom_semaphore(hw))) {
994
995
996
997
998
999 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1000 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1001 if (ret_val) {
1002 e1000_put_hw_eeprom_semaphore(hw);
1003 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1004 goto out;
1005 }
1006 checksum += nvm_data;
1007 }
1008 checksum = (uint16_t)EEPROM_SUM - checksum;
1009 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1010 &checksum);
1011 if (ret_val) {
1012 e1000_put_hw_eeprom_semaphore(hw);
1013 DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1014 goto out;
1015 }
1016
1017 e1000_put_hw_eeprom_semaphore(hw);
1018
1019 ret_val = e1000_update_flash_i210(hw);
1020 } else {
1021 ret_val = -E1000_ERR_SWFW_SYNC;
1022 }
1023
1024out:
1025 return ret_val;
1026}
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1038{
1039 uint16_t i, checksum, checksum_reg, *buf;
1040
1041 DEBUGFUNC();
1042
1043
1044 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1045 if (!buf) {
1046 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1047 return -E1000_ERR_EEPROM;
1048 }
1049
1050
1051 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1052 E1000_ERR(hw, "Unable to read EEPROM!\n");
1053 return -E1000_ERR_EEPROM;
1054 }
1055
1056
1057 checksum = 0;
1058 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1059 checksum += buf[i];
1060 checksum = ((uint16_t)EEPROM_SUM) - checksum;
1061 checksum_reg = buf[i];
1062
1063
1064 if (checksum == checksum_reg)
1065 return 0;
1066
1067
1068 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1069 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
1070 checksum_reg, checksum);
1071
1072 return -E1000_ERR_EEPROM;
1073}
1074#endif
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084static int32_t
1085e1000_set_phy_mode(struct e1000_hw *hw)
1086{
1087#ifndef CONFIG_E1000_NO_NVM
1088 int32_t ret_val;
1089 uint16_t eeprom_data;
1090
1091 DEBUGFUNC();
1092
1093 if ((hw->mac_type == e1000_82545_rev_3) &&
1094 (hw->media_type == e1000_media_type_copper)) {
1095 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1096 1, &eeprom_data);
1097 if (ret_val)
1098 return ret_val;
1099
1100 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1101 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1102 ret_val = e1000_write_phy_reg(hw,
1103 M88E1000_PHY_PAGE_SELECT, 0x000B);
1104 if (ret_val)
1105 return ret_val;
1106 ret_val = e1000_write_phy_reg(hw,
1107 M88E1000_PHY_GEN_CONTROL, 0x8104);
1108 if (ret_val)
1109 return ret_val;
1110
1111 hw->phy_reset_disable = false;
1112 }
1113 }
1114#endif
1115 return E1000_SUCCESS;
1116}
1117
1118#ifndef CONFIG_E1000_NO_NVM
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129static int32_t
1130e1000_get_software_semaphore(struct e1000_hw *hw)
1131{
1132 int32_t timeout = hw->eeprom.word_size + 1;
1133 uint32_t swsm;
1134
1135 DEBUGFUNC();
1136
1137 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1138 return E1000_SUCCESS;
1139
1140 while (timeout) {
1141 swsm = E1000_READ_REG(hw, SWSM);
1142
1143
1144 if (!(swsm & E1000_SWSM_SMBI))
1145 break;
1146 mdelay(1);
1147 timeout--;
1148 }
1149
1150 if (!timeout) {
1151 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1152 return -E1000_ERR_RESET;
1153 }
1154
1155 return E1000_SUCCESS;
1156}
1157#endif
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167static void
1168e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1169{
1170#ifndef CONFIG_E1000_NO_NVM
1171 uint32_t swsm;
1172
1173 DEBUGFUNC();
1174
1175 if (!hw->eeprom_semaphore_present)
1176 return;
1177
1178 swsm = E1000_READ_REG(hw, SWSM);
1179 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1180
1181 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1182 } else
1183 swsm &= ~(E1000_SWSM_SWESMBI);
1184 E1000_WRITE_REG(hw, SWSM, swsm);
1185#endif
1186}
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199static int32_t
1200e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1201{
1202#ifndef CONFIG_E1000_NO_NVM
1203 int32_t timeout;
1204 uint32_t swsm;
1205
1206 DEBUGFUNC();
1207
1208 if (!hw->eeprom_semaphore_present)
1209 return E1000_SUCCESS;
1210
1211 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1212
1213 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1214 return -E1000_ERR_EEPROM;
1215 }
1216
1217
1218 timeout = hw->eeprom.word_size + 1;
1219 while (timeout) {
1220 swsm = E1000_READ_REG(hw, SWSM);
1221 swsm |= E1000_SWSM_SWESMBI;
1222 E1000_WRITE_REG(hw, SWSM, swsm);
1223
1224 swsm = E1000_READ_REG(hw, SWSM);
1225 if (swsm & E1000_SWSM_SWESMBI)
1226 break;
1227
1228 udelay(50);
1229 timeout--;
1230 }
1231
1232 if (!timeout) {
1233
1234 e1000_put_hw_eeprom_semaphore(hw);
1235 DEBUGOUT("Driver can't access the Eeprom - "
1236 "SWESMBI bit is set.\n");
1237 return -E1000_ERR_EEPROM;
1238 }
1239#endif
1240 return E1000_SUCCESS;
1241}
1242
1243
1244static int32_t
1245e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1246{
1247 uint32_t swfw_sync = 0;
1248 uint32_t swmask = mask;
1249 uint32_t fwmask = mask << 16;
1250 int32_t timeout = 200;
1251
1252 DEBUGFUNC();
1253 while (timeout) {
1254 if (e1000_get_hw_eeprom_semaphore(hw))
1255 return -E1000_ERR_SWFW_SYNC;
1256
1257 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1258 if (!(swfw_sync & (fwmask | swmask)))
1259 break;
1260
1261
1262
1263 e1000_put_hw_eeprom_semaphore(hw);
1264 mdelay(5);
1265 timeout--;
1266 }
1267
1268 if (!timeout) {
1269 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1270 return -E1000_ERR_SWFW_SYNC;
1271 }
1272
1273 swfw_sync |= swmask;
1274 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1275
1276 e1000_put_hw_eeprom_semaphore(hw);
1277 return E1000_SUCCESS;
1278}
1279
1280static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1281{
1282 uint32_t swfw_sync = 0;
1283
1284 DEBUGFUNC();
1285 while (e1000_get_hw_eeprom_semaphore(hw))
1286 ;
1287
1288 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1289 swfw_sync &= ~mask;
1290 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1291
1292 e1000_put_hw_eeprom_semaphore(hw);
1293}
1294
1295static bool e1000_is_second_port(struct e1000_hw *hw)
1296{
1297 switch (hw->mac_type) {
1298 case e1000_80003es2lan:
1299 case e1000_82546:
1300 case e1000_82571:
1301 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1302 return true;
1303
1304 default:
1305 return false;
1306 }
1307}
1308
1309#ifndef CONFIG_E1000_NO_NVM
1310
1311
1312
1313
1314
1315
1316static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1317 unsigned char enetaddr[6])
1318{
1319 uint16_t offset;
1320 uint16_t eeprom_data;
1321 int i;
1322
1323 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1324 offset = i >> 1;
1325 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1326 DEBUGOUT("EEPROM Read Error\n");
1327 return -E1000_ERR_EEPROM;
1328 }
1329 enetaddr[i] = eeprom_data & 0xff;
1330 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1331 }
1332
1333 return 0;
1334}
1335
1336
1337
1338
1339
1340
1341
1342static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1343 unsigned char enetaddr[6])
1344{
1345 uint16_t offset, tmp;
1346 uint32_t reg_data = 0;
1347 int i;
1348
1349 if (hw->mac_type != e1000_igb)
1350 return -E1000_ERR_MAC_TYPE;
1351
1352 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1353 offset = i >> 1;
1354
1355 if (offset == 0)
1356 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1357 else if (offset == 1)
1358 reg_data >>= 16;
1359 else if (offset == 2)
1360 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1361 tmp = reg_data & 0xffff;
1362
1363 enetaddr[i] = tmp & 0xff;
1364 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1365 }
1366
1367 return 0;
1368}
1369
1370
1371
1372
1373
1374
1375
1376
1377static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1378{
1379 int ret_val;
1380
1381 if (hw->mac_type == e1000_igb) {
1382
1383 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1384 } else {
1385 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1386 }
1387 if (ret_val)
1388 return ret_val;
1389
1390
1391 if (e1000_is_second_port(hw))
1392 enetaddr[5] ^= 1;
1393
1394 return 0;
1395}
1396#endif
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407static void
1408e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1409{
1410 uint32_t i;
1411 uint32_t addr_low;
1412 uint32_t addr_high;
1413
1414 DEBUGFUNC();
1415
1416
1417 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1418 addr_low = (enetaddr[0] |
1419 (enetaddr[1] << 8) |
1420 (enetaddr[2] << 16) | (enetaddr[3] << 24));
1421
1422 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1423
1424 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1425 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1426
1427
1428 DEBUGOUT("Clearing RAR[1-15]\n");
1429 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1430 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1431 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1432 }
1433}
1434
1435
1436
1437
1438
1439
1440static void
1441e1000_clear_vfta(struct e1000_hw *hw)
1442{
1443 uint32_t offset;
1444
1445 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1446 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1447}
1448
1449
1450
1451
1452
1453
1454int32_t
1455e1000_set_mac_type(struct e1000_hw *hw)
1456{
1457 DEBUGFUNC();
1458
1459 switch (hw->device_id) {
1460 case E1000_DEV_ID_82542:
1461 switch (hw->revision_id) {
1462 case E1000_82542_2_0_REV_ID:
1463 hw->mac_type = e1000_82542_rev2_0;
1464 break;
1465 case E1000_82542_2_1_REV_ID:
1466 hw->mac_type = e1000_82542_rev2_1;
1467 break;
1468 default:
1469
1470 return -E1000_ERR_MAC_TYPE;
1471 }
1472 break;
1473 case E1000_DEV_ID_82543GC_FIBER:
1474 case E1000_DEV_ID_82543GC_COPPER:
1475 hw->mac_type = e1000_82543;
1476 break;
1477 case E1000_DEV_ID_82544EI_COPPER:
1478 case E1000_DEV_ID_82544EI_FIBER:
1479 case E1000_DEV_ID_82544GC_COPPER:
1480 case E1000_DEV_ID_82544GC_LOM:
1481 hw->mac_type = e1000_82544;
1482 break;
1483 case E1000_DEV_ID_82540EM:
1484 case E1000_DEV_ID_82540EM_LOM:
1485 case E1000_DEV_ID_82540EP:
1486 case E1000_DEV_ID_82540EP_LOM:
1487 case E1000_DEV_ID_82540EP_LP:
1488 hw->mac_type = e1000_82540;
1489 break;
1490 case E1000_DEV_ID_82545EM_COPPER:
1491 case E1000_DEV_ID_82545EM_FIBER:
1492 hw->mac_type = e1000_82545;
1493 break;
1494 case E1000_DEV_ID_82545GM_COPPER:
1495 case E1000_DEV_ID_82545GM_FIBER:
1496 case E1000_DEV_ID_82545GM_SERDES:
1497 hw->mac_type = e1000_82545_rev_3;
1498 break;
1499 case E1000_DEV_ID_82546EB_COPPER:
1500 case E1000_DEV_ID_82546EB_FIBER:
1501 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1502 hw->mac_type = e1000_82546;
1503 break;
1504 case E1000_DEV_ID_82546GB_COPPER:
1505 case E1000_DEV_ID_82546GB_FIBER:
1506 case E1000_DEV_ID_82546GB_SERDES:
1507 case E1000_DEV_ID_82546GB_PCIE:
1508 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1509 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1510 hw->mac_type = e1000_82546_rev_3;
1511 break;
1512 case E1000_DEV_ID_82541EI:
1513 case E1000_DEV_ID_82541EI_MOBILE:
1514 case E1000_DEV_ID_82541ER_LOM:
1515 hw->mac_type = e1000_82541;
1516 break;
1517 case E1000_DEV_ID_82541ER:
1518 case E1000_DEV_ID_82541GI:
1519 case E1000_DEV_ID_82541GI_LF:
1520 case E1000_DEV_ID_82541GI_MOBILE:
1521 hw->mac_type = e1000_82541_rev_2;
1522 break;
1523 case E1000_DEV_ID_82547EI:
1524 case E1000_DEV_ID_82547EI_MOBILE:
1525 hw->mac_type = e1000_82547;
1526 break;
1527 case E1000_DEV_ID_82547GI:
1528 hw->mac_type = e1000_82547_rev_2;
1529 break;
1530 case E1000_DEV_ID_82571EB_COPPER:
1531 case E1000_DEV_ID_82571EB_FIBER:
1532 case E1000_DEV_ID_82571EB_SERDES:
1533 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1534 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1535 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1536 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1537 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1538 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1539 hw->mac_type = e1000_82571;
1540 break;
1541 case E1000_DEV_ID_82572EI_COPPER:
1542 case E1000_DEV_ID_82572EI_FIBER:
1543 case E1000_DEV_ID_82572EI_SERDES:
1544 case E1000_DEV_ID_82572EI:
1545 hw->mac_type = e1000_82572;
1546 break;
1547 case E1000_DEV_ID_82573E:
1548 case E1000_DEV_ID_82573E_IAMT:
1549 case E1000_DEV_ID_82573L:
1550 hw->mac_type = e1000_82573;
1551 break;
1552 case E1000_DEV_ID_82574L:
1553 hw->mac_type = e1000_82574;
1554 break;
1555 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1556 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1557 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1558 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1559 hw->mac_type = e1000_80003es2lan;
1560 break;
1561 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1562 case E1000_DEV_ID_ICH8_IGP_AMT:
1563 case E1000_DEV_ID_ICH8_IGP_C:
1564 case E1000_DEV_ID_ICH8_IFE:
1565 case E1000_DEV_ID_ICH8_IFE_GT:
1566 case E1000_DEV_ID_ICH8_IFE_G:
1567 case E1000_DEV_ID_ICH8_IGP_M:
1568 hw->mac_type = e1000_ich8lan;
1569 break;
1570 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1571 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1572 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1573 case PCI_DEVICE_ID_INTEL_I211_COPPER:
1574 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1575 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1576 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1577 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1578 hw->mac_type = e1000_igb;
1579 break;
1580 default:
1581
1582 return -E1000_ERR_MAC_TYPE;
1583 }
1584 return E1000_SUCCESS;
1585}
1586
1587
1588
1589
1590
1591
1592void
1593e1000_reset_hw(struct e1000_hw *hw)
1594{
1595 uint32_t ctrl;
1596 uint32_t ctrl_ext;
1597 uint32_t manc;
1598 uint32_t pba = 0;
1599 uint32_t reg;
1600
1601 DEBUGFUNC();
1602
1603
1604 if (hw->mac_type < e1000_82571)
1605 pba = E1000_DEFAULT_PCI_PBA;
1606 else
1607 pba = E1000_DEFAULT_PCIE_PBA;
1608
1609
1610 if (hw->mac_type == e1000_82542_rev2_0) {
1611 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1612 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1613 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1614 }
1615
1616
1617 DEBUGOUT("Masking off all interrupts\n");
1618 if (hw->mac_type == e1000_igb)
1619 E1000_WRITE_REG(hw, I210_IAM, 0);
1620 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1621
1622
1623
1624
1625
1626 E1000_WRITE_REG(hw, RCTL, 0);
1627 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1628 E1000_WRITE_FLUSH(hw);
1629
1630 if (hw->mac_type == e1000_igb) {
1631 E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
1632 E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
1633 }
1634
1635
1636 hw->tbi_compatibility_on = false;
1637
1638
1639
1640
1641 mdelay(10);
1642
1643
1644
1645
1646
1647
1648 DEBUGOUT("Issuing a global reset to MAC\n");
1649 ctrl = E1000_READ_REG(hw, CTRL);
1650
1651 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1652
1653
1654 if (hw->mac_type == e1000_igb) {
1655 mdelay(20);
1656 reg = E1000_READ_REG(hw, STATUS);
1657 if (reg & E1000_STATUS_PF_RST_DONE)
1658 DEBUGOUT("PF OK\n");
1659 reg = E1000_READ_REG(hw, I210_EECD);
1660 if (reg & E1000_EECD_AUTO_RD)
1661 DEBUGOUT("EEC OK\n");
1662 } else if (hw->mac_type < e1000_82540) {
1663
1664 udelay(10);
1665 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1666 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1667 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1668 E1000_WRITE_FLUSH(hw);
1669
1670 mdelay(2);
1671 } else {
1672
1673 mdelay(4);
1674
1675 manc = E1000_READ_REG(hw, MANC);
1676 manc &= ~(E1000_MANC_ARP_EN);
1677 E1000_WRITE_REG(hw, MANC, manc);
1678 }
1679
1680
1681 DEBUGOUT("Masking off all interrupts\n");
1682 if (hw->mac_type == e1000_igb)
1683 E1000_WRITE_REG(hw, I210_IAM, 0);
1684 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1685
1686
1687 E1000_READ_REG(hw, ICR);
1688
1689
1690 if (hw->mac_type == e1000_82542_rev2_0) {
1691 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1692 }
1693 if (hw->mac_type != e1000_igb)
1694 E1000_WRITE_REG(hw, PBA, pba);
1695}
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706static void
1707e1000_initialize_hardware_bits(struct e1000_hw *hw)
1708{
1709 if ((hw->mac_type >= e1000_82571) &&
1710 (!hw->initialize_hw_bits_disable)) {
1711
1712 uint32_t reg_ctrl, reg_ctrl_ext;
1713 uint32_t reg_tarc0, reg_tarc1;
1714 uint32_t reg_tctl;
1715 uint32_t reg_txdctl, reg_txdctl1;
1716
1717
1718 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1719 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1720
1721
1722 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1723 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1724 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1725
1726 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1727 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1728 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1729
1730
1731 switch (hw->mac_type) {
1732 case e1000_igb:
1733 return;
1734 case e1000_82571:
1735 case e1000_82572:
1736
1737 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1738 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1739
1740
1741 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1742
1743
1744 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1745
1746
1747 reg_tctl = E1000_READ_REG(hw, TCTL);
1748 if (reg_tctl & E1000_TCTL_MULR)
1749 reg_tarc1 &= ~(1 << 28);
1750 else
1751 reg_tarc1 |= (1 << 28);
1752
1753 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1754 break;
1755 case e1000_82573:
1756 case e1000_82574:
1757 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1758 reg_ctrl_ext &= ~(1 << 23);
1759 reg_ctrl_ext |= (1 << 22);
1760
1761
1762 reg_ctrl = E1000_READ_REG(hw, CTRL);
1763 reg_ctrl &= ~(1 << 29);
1764
1765 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1766 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1767 break;
1768 case e1000_80003es2lan:
1769
1770 if ((hw->media_type == e1000_media_type_fiber)
1771 || (hw->media_type ==
1772 e1000_media_type_internal_serdes)) {
1773 reg_tarc0 &= ~(1 << 20);
1774 }
1775
1776
1777 reg_tctl = E1000_READ_REG(hw, TCTL);
1778 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1779 if (reg_tctl & E1000_TCTL_MULR)
1780 reg_tarc1 &= ~(1 << 28);
1781 else
1782 reg_tarc1 |= (1 << 28);
1783
1784 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1785 break;
1786 case e1000_ich8lan:
1787
1788 if ((hw->revision_id < 3) ||
1789 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1790 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1791 reg_tarc0 |= ((1 << 29)|(1 << 28));
1792
1793 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1794 reg_ctrl_ext |= (1 << 22);
1795 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1796
1797
1798 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1799
1800
1801 reg_tctl = E1000_READ_REG(hw, TCTL);
1802 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1803 if (reg_tctl & E1000_TCTL_MULR)
1804 reg_tarc1 &= ~(1 << 28);
1805 else
1806 reg_tarc1 |= (1 << 28);
1807
1808
1809 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1810
1811 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1812 break;
1813 default:
1814 break;
1815 }
1816
1817 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1818 }
1819}
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832static int
1833e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1834{
1835 uint32_t ctrl;
1836 uint32_t i;
1837 int32_t ret_val;
1838 uint16_t pcix_cmd_word;
1839 uint16_t pcix_stat_hi_word;
1840 uint16_t cmd_mmrbc;
1841 uint16_t stat_mmrbc;
1842 uint32_t mta_size;
1843 uint32_t reg_data;
1844 uint32_t ctrl_ext;
1845 DEBUGFUNC();
1846
1847 if ((hw->mac_type == e1000_ich8lan) &&
1848 ((hw->revision_id < 3) ||
1849 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1850 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1851 reg_data = E1000_READ_REG(hw, STATUS);
1852 reg_data &= ~0x80000000;
1853 E1000_WRITE_REG(hw, STATUS, reg_data);
1854 }
1855
1856
1857
1858 e1000_set_media_type(hw);
1859
1860
1861
1862 e1000_initialize_hardware_bits(hw);
1863
1864
1865 DEBUGOUT("Initializing the IEEE VLAN\n");
1866
1867 if (hw->mac_type != e1000_ich8lan) {
1868 if (hw->mac_type < e1000_82545_rev_3)
1869 E1000_WRITE_REG(hw, VET, 0);
1870 e1000_clear_vfta(hw);
1871 }
1872
1873
1874 if (hw->mac_type == e1000_82542_rev2_0) {
1875 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1876 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1877 hw->
1878 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1879 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1880 E1000_WRITE_FLUSH(hw);
1881 mdelay(5);
1882 }
1883
1884
1885
1886
1887 e1000_init_rx_addrs(hw, enetaddr);
1888
1889
1890 if (hw->mac_type == e1000_82542_rev2_0) {
1891 E1000_WRITE_REG(hw, RCTL, 0);
1892 E1000_WRITE_FLUSH(hw);
1893 mdelay(1);
1894 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1895 }
1896
1897
1898 DEBUGOUT("Zeroing the MTA\n");
1899 mta_size = E1000_MC_TBL_SIZE;
1900 if (hw->mac_type == e1000_ich8lan)
1901 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1902 for (i = 0; i < mta_size; i++) {
1903 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1904
1905
1906 E1000_WRITE_FLUSH(hw);
1907 }
1908
1909 switch (hw->mac_type) {
1910 case e1000_82545_rev_3:
1911 case e1000_82546_rev_3:
1912 case e1000_igb:
1913 break;
1914 default:
1915
1916 if (hw->bus_type == e1000_bus_type_pcix) {
1917 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1918 &pcix_cmd_word);
1919 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1920 &pcix_stat_hi_word);
1921 cmd_mmrbc =
1922 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1923 PCIX_COMMAND_MMRBC_SHIFT;
1924 stat_mmrbc =
1925 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1926 PCIX_STATUS_HI_MMRBC_SHIFT;
1927 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1928 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1929 if (cmd_mmrbc > stat_mmrbc) {
1930 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1931 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1932 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1933 pcix_cmd_word);
1934 }
1935 }
1936 break;
1937 }
1938
1939
1940 if (hw->mac_type == e1000_ich8lan)
1941 mdelay(15);
1942 if (hw->mac_type == e1000_igb)
1943 mdelay(15);
1944
1945
1946 ret_val = e1000_setup_link(hw);
1947
1948
1949 if (hw->mac_type > e1000_82544) {
1950 ctrl = E1000_READ_REG(hw, TXDCTL);
1951 ctrl =
1952 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1953 E1000_TXDCTL_FULL_TX_DESC_WB;
1954 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1955 }
1956
1957
1958 if (hw->mac_type >= e1000_82571) {
1959 ctrl = E1000_READ_REG(hw, RXDCTL);
1960 ctrl =
1961 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1962 E1000_RXDCTL_FULL_RX_DESC_WB;
1963 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1964 }
1965
1966 switch (hw->mac_type) {
1967 default:
1968 break;
1969 case e1000_80003es2lan:
1970
1971 reg_data = E1000_READ_REG(hw, TCTL);
1972 reg_data |= E1000_TCTL_RTLC;
1973 E1000_WRITE_REG(hw, TCTL, reg_data);
1974
1975
1976 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1977 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1978 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1979 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1980
1981
1982 reg_data = E1000_READ_REG(hw, TIPG);
1983 reg_data &= ~E1000_TIPG_IPGT_MASK;
1984 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1985 E1000_WRITE_REG(hw, TIPG, reg_data);
1986
1987 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1988 reg_data &= ~0x00100000;
1989 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1990
1991 case e1000_82571:
1992 case e1000_82572:
1993 case e1000_ich8lan:
1994 ctrl = E1000_READ_REG(hw, TXDCTL1);
1995 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1996 | E1000_TXDCTL_FULL_TX_DESC_WB;
1997 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1998 break;
1999 case e1000_82573:
2000 case e1000_82574:
2001 reg_data = E1000_READ_REG(hw, GCR);
2002 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2003 E1000_WRITE_REG(hw, GCR, reg_data);
2004 case e1000_igb:
2005 break;
2006 }
2007
2008 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2009 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2010 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2011
2012
2013 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2014 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2015 }
2016
2017 return ret_val;
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031static int
2032e1000_setup_link(struct e1000_hw *hw)
2033{
2034 int32_t ret_val;
2035#ifndef CONFIG_E1000_NO_NVM
2036 uint32_t ctrl_ext;
2037 uint16_t eeprom_data;
2038#endif
2039
2040 DEBUGFUNC();
2041
2042
2043
2044 if (e1000_check_phy_reset_block(hw))
2045 return E1000_SUCCESS;
2046
2047#ifndef CONFIG_E1000_NO_NVM
2048
2049
2050
2051
2052
2053
2054
2055
2056 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2057 &eeprom_data) < 0) {
2058 DEBUGOUT("EEPROM Read Error\n");
2059 return -E1000_ERR_EEPROM;
2060 }
2061#endif
2062 if (hw->fc == e1000_fc_default) {
2063 switch (hw->mac_type) {
2064 case e1000_ich8lan:
2065 case e1000_82573:
2066 case e1000_82574:
2067 case e1000_igb:
2068 hw->fc = e1000_fc_full;
2069 break;
2070 default:
2071#ifndef CONFIG_E1000_NO_NVM
2072 ret_val = e1000_read_eeprom(hw,
2073 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2074 if (ret_val) {
2075 DEBUGOUT("EEPROM Read Error\n");
2076 return -E1000_ERR_EEPROM;
2077 }
2078 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2079 hw->fc = e1000_fc_none;
2080 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2081 EEPROM_WORD0F_ASM_DIR)
2082 hw->fc = e1000_fc_tx_pause;
2083 else
2084#endif
2085 hw->fc = e1000_fc_full;
2086 break;
2087 }
2088 }
2089
2090
2091
2092
2093
2094 if (hw->mac_type == e1000_82542_rev2_0)
2095 hw->fc &= (~e1000_fc_tx_pause);
2096
2097 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2098 hw->fc &= (~e1000_fc_rx_pause);
2099
2100 hw->original_fc = hw->fc;
2101
2102 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2103
2104#ifndef CONFIG_E1000_NO_NVM
2105
2106
2107
2108
2109
2110
2111
2112 if (hw->mac_type == e1000_82543) {
2113 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2114 SWDPIO__EXT_SHIFT);
2115 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2116 }
2117#endif
2118
2119
2120 ret_val = (hw->media_type == e1000_media_type_fiber) ?
2121 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2122 if (ret_val < 0) {
2123 return ret_val;
2124 }
2125
2126
2127
2128
2129
2130
2131 DEBUGOUT("Initializing the Flow Control address, type"
2132 "and timer regs\n");
2133
2134
2135 if (hw->mac_type != e1000_ich8lan) {
2136 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2137 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2138 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2139 }
2140
2141 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2142
2143
2144
2145
2146
2147
2148
2149 if (!(hw->fc & e1000_fc_tx_pause)) {
2150 E1000_WRITE_REG(hw, FCRTL, 0);
2151 E1000_WRITE_REG(hw, FCRTH, 0);
2152 } else {
2153
2154
2155
2156 if (hw->fc_send_xon) {
2157 E1000_WRITE_REG(hw, FCRTL,
2158 (hw->fc_low_water | E1000_FCRTL_XONE));
2159 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2160 } else {
2161 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2162 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2163 }
2164 }
2165 return ret_val;
2166}
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177static int
2178e1000_setup_fiber_link(struct e1000_hw *hw)
2179{
2180 uint32_t ctrl;
2181 uint32_t status;
2182 uint32_t txcw = 0;
2183 uint32_t i;
2184 uint32_t signal;
2185 int32_t ret_val;
2186
2187 DEBUGFUNC();
2188
2189
2190
2191
2192 ctrl = E1000_READ_REG(hw, CTRL);
2193 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2194 signal = E1000_CTRL_SWDPIN1;
2195 else
2196 signal = 0;
2197
2198 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2199 ctrl);
2200
2201 ctrl &= ~(E1000_CTRL_LRST);
2202
2203 e1000_config_collision_dist(hw);
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220 switch (hw->fc) {
2221 case e1000_fc_none:
2222
2223 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2224 break;
2225 case e1000_fc_rx_pause:
2226
2227
2228
2229
2230
2231
2232 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2233 break;
2234 case e1000_fc_tx_pause:
2235
2236
2237
2238 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2239 break;
2240 case e1000_fc_full:
2241
2242 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2243 break;
2244 default:
2245 DEBUGOUT("Flow control param set incorrectly\n");
2246 return -E1000_ERR_CONFIG;
2247 break;
2248 }
2249
2250
2251
2252
2253
2254
2255
2256 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2257
2258 E1000_WRITE_REG(hw, TXCW, txcw);
2259 E1000_WRITE_REG(hw, CTRL, ctrl);
2260 E1000_WRITE_FLUSH(hw);
2261
2262 hw->txcw = txcw;
2263 mdelay(1);
2264
2265
2266
2267
2268
2269
2270 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2271 DEBUGOUT("Looking for Link\n");
2272 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2273 mdelay(10);
2274 status = E1000_READ_REG(hw, STATUS);
2275 if (status & E1000_STATUS_LU)
2276 break;
2277 }
2278 if (i == (LINK_UP_TIMEOUT / 10)) {
2279
2280
2281
2282
2283
2284 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2285 hw->autoneg_failed = 1;
2286 ret_val = e1000_check_for_link(hw);
2287 if (ret_val < 0) {
2288 DEBUGOUT("Error while checking for link\n");
2289 return ret_val;
2290 }
2291 hw->autoneg_failed = 0;
2292 } else {
2293 hw->autoneg_failed = 0;
2294 DEBUGOUT("Valid Link Found\n");
2295 }
2296 } else {
2297 DEBUGOUT("No Signal Detected\n");
2298 return -E1000_ERR_NOLINK;
2299 }
2300 return 0;
2301}
2302
2303
2304
2305
2306
2307
2308static int32_t
2309e1000_copper_link_preconfig(struct e1000_hw *hw)
2310{
2311 uint32_t ctrl;
2312 int32_t ret_val;
2313 uint16_t phy_data;
2314
2315 DEBUGFUNC();
2316
2317 ctrl = E1000_READ_REG(hw, CTRL);
2318
2319
2320
2321
2322 if (hw->mac_type > e1000_82543) {
2323 ctrl |= E1000_CTRL_SLU;
2324 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2325 E1000_WRITE_REG(hw, CTRL, ctrl);
2326 } else {
2327 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2328 | E1000_CTRL_SLU);
2329 E1000_WRITE_REG(hw, CTRL, ctrl);
2330 ret_val = e1000_phy_hw_reset(hw);
2331 if (ret_val)
2332 return ret_val;
2333 }
2334
2335
2336 ret_val = e1000_detect_gig_phy(hw);
2337 if (ret_val) {
2338 DEBUGOUT("Error, did not detect valid phy.\n");
2339 return ret_val;
2340 }
2341 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2342
2343
2344 ret_val = e1000_set_phy_mode(hw);
2345 if (ret_val)
2346 return ret_val;
2347 if ((hw->mac_type == e1000_82545_rev_3) ||
2348 (hw->mac_type == e1000_82546_rev_3)) {
2349 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2350 &phy_data);
2351 phy_data |= 0x00000008;
2352 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2353 phy_data);
2354 }
2355
2356 if (hw->mac_type <= e1000_82543 ||
2357 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2358 hw->mac_type == e1000_82541_rev_2
2359 || hw->mac_type == e1000_82547_rev_2)
2360 hw->phy_reset_disable = false;
2361
2362 return E1000_SUCCESS;
2363}
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379static int32_t
2380e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2381{
2382 uint32_t phy_ctrl = 0;
2383 int32_t ret_val;
2384 uint16_t phy_data;
2385 DEBUGFUNC();
2386
2387 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2388 && hw->phy_type != e1000_phy_igp_3)
2389 return E1000_SUCCESS;
2390
2391
2392
2393
2394 if (hw->mac_type == e1000_82541_rev_2
2395 || hw->mac_type == e1000_82547_rev_2) {
2396 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2397 &phy_data);
2398 if (ret_val)
2399 return ret_val;
2400 } else if (hw->mac_type == e1000_ich8lan) {
2401
2402
2403
2404 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2405 } else {
2406 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2407 &phy_data);
2408 if (ret_val)
2409 return ret_val;
2410 }
2411
2412 if (!active) {
2413 if (hw->mac_type == e1000_82541_rev_2 ||
2414 hw->mac_type == e1000_82547_rev_2) {
2415 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2416 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2417 phy_data);
2418 if (ret_val)
2419 return ret_val;
2420 } else {
2421 if (hw->mac_type == e1000_ich8lan) {
2422 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2423 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2424 } else {
2425 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2426 ret_val = e1000_write_phy_reg(hw,
2427 IGP02E1000_PHY_POWER_MGMT, phy_data);
2428 if (ret_val)
2429 return ret_val;
2430 }
2431 }
2432
2433
2434
2435
2436
2437 if (hw->smart_speed == e1000_smart_speed_on) {
2438 ret_val = e1000_read_phy_reg(hw,
2439 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2440 if (ret_val)
2441 return ret_val;
2442
2443 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2444 ret_val = e1000_write_phy_reg(hw,
2445 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2446 if (ret_val)
2447 return ret_val;
2448 } else if (hw->smart_speed == e1000_smart_speed_off) {
2449 ret_val = e1000_read_phy_reg(hw,
2450 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2451 if (ret_val)
2452 return ret_val;
2453
2454 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2455 ret_val = e1000_write_phy_reg(hw,
2456 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2457 if (ret_val)
2458 return ret_val;
2459 }
2460
2461 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2462 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2463 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2464
2465 if (hw->mac_type == e1000_82541_rev_2 ||
2466 hw->mac_type == e1000_82547_rev_2) {
2467 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2468 ret_val = e1000_write_phy_reg(hw,
2469 IGP01E1000_GMII_FIFO, phy_data);
2470 if (ret_val)
2471 return ret_val;
2472 } else {
2473 if (hw->mac_type == e1000_ich8lan) {
2474 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2475 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2476 } else {
2477 phy_data |= IGP02E1000_PM_D3_LPLU;
2478 ret_val = e1000_write_phy_reg(hw,
2479 IGP02E1000_PHY_POWER_MGMT, phy_data);
2480 if (ret_val)
2481 return ret_val;
2482 }
2483 }
2484
2485
2486 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2487 &phy_data);
2488 if (ret_val)
2489 return ret_val;
2490
2491 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2492 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2493 phy_data);
2494 if (ret_val)
2495 return ret_val;
2496 }
2497 return E1000_SUCCESS;
2498}
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514static int32_t
2515e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2516{
2517 uint32_t phy_ctrl = 0;
2518 int32_t ret_val;
2519 uint16_t phy_data;
2520 DEBUGFUNC();
2521
2522 if (hw->mac_type <= e1000_82547_rev_2)
2523 return E1000_SUCCESS;
2524
2525 if (hw->mac_type == e1000_ich8lan) {
2526 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2527 } else if (hw->mac_type == e1000_igb) {
2528 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2529 } else {
2530 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2531 &phy_data);
2532 if (ret_val)
2533 return ret_val;
2534 }
2535
2536 if (!active) {
2537 if (hw->mac_type == e1000_ich8lan) {
2538 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2539 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2540 } else if (hw->mac_type == e1000_igb) {
2541 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2542 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2543 } else {
2544 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2545 ret_val = e1000_write_phy_reg(hw,
2546 IGP02E1000_PHY_POWER_MGMT, phy_data);
2547 if (ret_val)
2548 return ret_val;
2549 }
2550
2551 if (hw->mac_type == e1000_igb)
2552 return E1000_SUCCESS;
2553
2554
2555
2556
2557
2558 if (hw->smart_speed == e1000_smart_speed_on) {
2559 ret_val = e1000_read_phy_reg(hw,
2560 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2561 if (ret_val)
2562 return ret_val;
2563
2564 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2565 ret_val = e1000_write_phy_reg(hw,
2566 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2567 if (ret_val)
2568 return ret_val;
2569 } else if (hw->smart_speed == e1000_smart_speed_off) {
2570 ret_val = e1000_read_phy_reg(hw,
2571 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2572 if (ret_val)
2573 return ret_val;
2574
2575 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2576 ret_val = e1000_write_phy_reg(hw,
2577 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2578 if (ret_val)
2579 return ret_val;
2580 }
2581
2582
2583 } else {
2584
2585 if (hw->mac_type == e1000_ich8lan) {
2586 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2587 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2588 } else if (hw->mac_type == e1000_igb) {
2589 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2590 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2591 } else {
2592 phy_data |= IGP02E1000_PM_D0_LPLU;
2593 ret_val = e1000_write_phy_reg(hw,
2594 IGP02E1000_PHY_POWER_MGMT, phy_data);
2595 if (ret_val)
2596 return ret_val;
2597 }
2598
2599 if (hw->mac_type == e1000_igb)
2600 return E1000_SUCCESS;
2601
2602
2603 ret_val = e1000_read_phy_reg(hw,
2604 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2605 if (ret_val)
2606 return ret_val;
2607
2608 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2609 ret_val = e1000_write_phy_reg(hw,
2610 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2611 if (ret_val)
2612 return ret_val;
2613
2614 }
2615 return E1000_SUCCESS;
2616}
2617
2618
2619
2620
2621
2622
2623static int32_t
2624e1000_copper_link_igp_setup(struct e1000_hw *hw)
2625{
2626 uint32_t led_ctrl;
2627 int32_t ret_val;
2628 uint16_t phy_data;
2629
2630 DEBUGFUNC();
2631
2632 if (hw->phy_reset_disable)
2633 return E1000_SUCCESS;
2634
2635 ret_val = e1000_phy_reset(hw);
2636 if (ret_val) {
2637 DEBUGOUT("Error Resetting the PHY\n");
2638 return ret_val;
2639 }
2640
2641
2642 mdelay(15);
2643 if (hw->mac_type != e1000_ich8lan) {
2644
2645 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2646 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2647 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2648 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2649 }
2650
2651
2652 if (hw->phy_type == e1000_phy_igp) {
2653
2654 ret_val = e1000_set_d3_lplu_state(hw, false);
2655 if (ret_val) {
2656 DEBUGOUT("Error Disabling LPLU D3\n");
2657 return ret_val;
2658 }
2659 }
2660
2661
2662 ret_val = e1000_set_d0_lplu_state(hw, false);
2663 if (ret_val) {
2664 DEBUGOUT("Error Disabling LPLU D0\n");
2665 return ret_val;
2666 }
2667
2668 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2669 if (ret_val)
2670 return ret_val;
2671
2672 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2673 hw->dsp_config_state = e1000_dsp_config_disabled;
2674
2675 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2676 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2677 hw->mdix = 1;
2678
2679 } else {
2680 hw->dsp_config_state = e1000_dsp_config_enabled;
2681 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2682
2683 switch (hw->mdix) {
2684 case 1:
2685 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2686 break;
2687 case 2:
2688 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2689 break;
2690 case 0:
2691 default:
2692 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2693 break;
2694 }
2695 }
2696 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2697 if (ret_val)
2698 return ret_val;
2699
2700
2701 if (hw->autoneg) {
2702 e1000_ms_type phy_ms_setting = hw->master_slave;
2703
2704 if (hw->ffe_config_state == e1000_ffe_config_active)
2705 hw->ffe_config_state = e1000_ffe_config_enabled;
2706
2707 if (hw->dsp_config_state == e1000_dsp_config_activated)
2708 hw->dsp_config_state = e1000_dsp_config_enabled;
2709
2710
2711
2712
2713 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2714
2715 ret_val = e1000_read_phy_reg(hw,
2716 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2717 if (ret_val)
2718 return ret_val;
2719 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2720 ret_val = e1000_write_phy_reg(hw,
2721 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2722 if (ret_val)
2723 return ret_val;
2724
2725 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2726 &phy_data);
2727 if (ret_val)
2728 return ret_val;
2729 phy_data &= ~CR_1000T_MS_ENABLE;
2730 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2731 phy_data);
2732 if (ret_val)
2733 return ret_val;
2734 }
2735
2736 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2737 if (ret_val)
2738 return ret_val;
2739
2740
2741 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2742 ((phy_data & CR_1000T_MS_VALUE) ?
2743 e1000_ms_force_master :
2744 e1000_ms_force_slave) :
2745 e1000_ms_auto;
2746
2747 switch (phy_ms_setting) {
2748 case e1000_ms_force_master:
2749 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2750 break;
2751 case e1000_ms_force_slave:
2752 phy_data |= CR_1000T_MS_ENABLE;
2753 phy_data &= ~(CR_1000T_MS_VALUE);
2754 break;
2755 case e1000_ms_auto:
2756 phy_data &= ~CR_1000T_MS_ENABLE;
2757 default:
2758 break;
2759 }
2760 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2761 if (ret_val)
2762 return ret_val;
2763 }
2764
2765 return E1000_SUCCESS;
2766}
2767
2768
2769
2770
2771
2772
2773bool
2774e1000_check_mng_mode(struct e1000_hw *hw)
2775{
2776 uint32_t fwsm;
2777 DEBUGFUNC();
2778
2779 fwsm = E1000_READ_REG(hw, FWSM);
2780
2781 if (hw->mac_type == e1000_ich8lan) {
2782 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2783 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2784 return true;
2785 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2786 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2787 return true;
2788
2789 return false;
2790}
2791
2792static int32_t
2793e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2794{
2795 uint16_t swfw = E1000_SWFW_PHY0_SM;
2796 uint32_t reg_val;
2797 DEBUGFUNC();
2798
2799 if (e1000_is_second_port(hw))
2800 swfw = E1000_SWFW_PHY1_SM;
2801
2802 if (e1000_swfw_sync_acquire(hw, swfw))
2803 return -E1000_ERR_SWFW_SYNC;
2804
2805 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2806 & E1000_KUMCTRLSTA_OFFSET) | data;
2807 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2808 udelay(2);
2809
2810 return E1000_SUCCESS;
2811}
2812
2813static int32_t
2814e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2815{
2816 uint16_t swfw = E1000_SWFW_PHY0_SM;
2817 uint32_t reg_val;
2818 DEBUGFUNC();
2819
2820 if (e1000_is_second_port(hw))
2821 swfw = E1000_SWFW_PHY1_SM;
2822
2823 if (e1000_swfw_sync_acquire(hw, swfw)) {
2824 debug("%s[%i]\n", __func__, __LINE__);
2825 return -E1000_ERR_SWFW_SYNC;
2826 }
2827
2828
2829 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2830 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2831 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2832 udelay(2);
2833
2834
2835 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2836 *data = (uint16_t)reg_val;
2837
2838 return E1000_SUCCESS;
2839}
2840
2841
2842
2843
2844
2845
2846static int32_t
2847e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2848{
2849 int32_t ret_val;
2850 uint16_t phy_data;
2851 uint32_t reg_data;
2852
2853 DEBUGFUNC();
2854
2855 if (!hw->phy_reset_disable) {
2856
2857 ret_val = e1000_read_phy_reg(hw,
2858 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2859 if (ret_val)
2860 return ret_val;
2861
2862 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2863
2864 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2865
2866 ret_val = e1000_write_phy_reg(hw,
2867 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2868 if (ret_val)
2869 return ret_val;
2870
2871
2872
2873
2874
2875
2876
2877
2878 ret_val = e1000_read_phy_reg(hw,
2879 GG82563_PHY_SPEC_CTRL, &phy_data);
2880 if (ret_val)
2881 return ret_val;
2882
2883 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2884
2885 switch (hw->mdix) {
2886 case 1:
2887 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2888 break;
2889 case 2:
2890 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2891 break;
2892 case 0:
2893 default:
2894 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2895 break;
2896 }
2897
2898
2899
2900
2901
2902
2903
2904 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2905 ret_val = e1000_write_phy_reg(hw,
2906 GG82563_PHY_SPEC_CTRL, phy_data);
2907
2908 if (ret_val)
2909 return ret_val;
2910
2911
2912 ret_val = e1000_phy_reset(hw);
2913 if (ret_val) {
2914 DEBUGOUT("Error Resetting the PHY\n");
2915 return ret_val;
2916 }
2917 }
2918
2919 if (hw->mac_type == e1000_80003es2lan) {
2920
2921 ret_val = e1000_write_kmrn_reg(hw,
2922 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2923 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2924 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2925 if (ret_val)
2926 return ret_val;
2927
2928 ret_val = e1000_read_phy_reg(hw,
2929 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2930 if (ret_val)
2931 return ret_val;
2932
2933 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2934 ret_val = e1000_write_phy_reg(hw,
2935 GG82563_PHY_SPEC_CTRL_2, phy_data);
2936
2937 if (ret_val)
2938 return ret_val;
2939
2940 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2941 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2942 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2943
2944 ret_val = e1000_read_phy_reg(hw,
2945 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2946 if (ret_val)
2947 return ret_val;
2948
2949
2950
2951
2952
2953 if (e1000_check_mng_mode(hw) == false) {
2954
2955 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2956 ret_val = e1000_write_phy_reg(hw,
2957 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2958 if (ret_val)
2959 return ret_val;
2960
2961 ret_val = e1000_read_phy_reg(hw,
2962 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2963 if (ret_val)
2964 return ret_val;
2965
2966 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2967 ret_val = e1000_write_phy_reg(hw,
2968 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2969
2970 if (ret_val)
2971 return ret_val;
2972 }
2973
2974
2975
2976
2977 ret_val = e1000_read_phy_reg(hw,
2978 GG82563_PHY_INBAND_CTRL, &phy_data);
2979 if (ret_val)
2980 return ret_val;
2981 phy_data |= GG82563_ICR_DIS_PADDING;
2982 ret_val = e1000_write_phy_reg(hw,
2983 GG82563_PHY_INBAND_CTRL, phy_data);
2984 if (ret_val)
2985 return ret_val;
2986 }
2987 return E1000_SUCCESS;
2988}
2989
2990
2991
2992
2993
2994
2995static int32_t
2996e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2997{
2998 int32_t ret_val;
2999 uint16_t phy_data;
3000
3001 DEBUGFUNC();
3002
3003 if (hw->phy_reset_disable)
3004 return E1000_SUCCESS;
3005
3006
3007 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3008 if (ret_val)
3009 return ret_val;
3010
3011 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3012
3013
3014
3015
3016
3017
3018
3019
3020 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3021
3022 switch (hw->mdix) {
3023 case 1:
3024 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3025 break;
3026 case 2:
3027 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3028 break;
3029 case 3:
3030 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3031 break;
3032 case 0:
3033 default:
3034 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3035 break;
3036 }
3037
3038
3039
3040
3041
3042
3043
3044 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3045 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3046 if (ret_val)
3047 return ret_val;
3048
3049 if (hw->phy_revision < M88E1011_I_REV_4) {
3050
3051
3052
3053 ret_val = e1000_read_phy_reg(hw,
3054 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3055 if (ret_val)
3056 return ret_val;
3057
3058 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3059
3060 if ((hw->phy_revision == E1000_REVISION_2) &&
3061 (hw->phy_id == M88E1111_I_PHY_ID)) {
3062
3063 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3064 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3065 ret_val = e1000_write_phy_reg(hw,
3066 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3067 if (ret_val)
3068 return ret_val;
3069 } else {
3070
3071 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3072 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3073 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3074 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3075 ret_val = e1000_write_phy_reg(hw,
3076 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3077 if (ret_val)
3078 return ret_val;
3079 }
3080 }
3081
3082
3083 ret_val = e1000_phy_reset(hw);
3084 if (ret_val) {
3085 DEBUGOUT("Error Resetting the PHY\n");
3086 return ret_val;
3087 }
3088
3089 return E1000_SUCCESS;
3090}
3091
3092
3093
3094
3095
3096
3097
3098static int32_t
3099e1000_copper_link_autoneg(struct e1000_hw *hw)
3100{
3101 int32_t ret_val;
3102 uint16_t phy_data;
3103
3104 DEBUGFUNC();
3105
3106
3107
3108
3109 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3110
3111
3112
3113
3114 if (hw->autoneg_advertised == 0)
3115 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3116
3117
3118 if (hw->phy_type == e1000_phy_ife)
3119 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3120
3121 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3122 ret_val = e1000_phy_setup_autoneg(hw);
3123 if (ret_val) {
3124 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3125 return ret_val;
3126 }
3127 DEBUGOUT("Restarting Auto-Neg\n");
3128
3129
3130
3131
3132 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3133 if (ret_val)
3134 return ret_val;
3135
3136 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3137 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3138 if (ret_val)
3139 return ret_val;
3140
3141
3142
3143
3144
3145
3146
3147
3148 if (hw->wait_autoneg_complete) {
3149 ret_val = e1000_wait_autoneg(hw);
3150 if (ret_val) {
3151 DEBUGOUT("Error while waiting for autoneg"
3152 "to complete\n");
3153 return ret_val;
3154 }
3155 }
3156
3157 hw->get_link_status = true;
3158
3159 return E1000_SUCCESS;
3160}
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174static int32_t
3175e1000_copper_link_postconfig(struct e1000_hw *hw)
3176{
3177 int32_t ret_val;
3178 DEBUGFUNC();
3179
3180 if (hw->mac_type >= e1000_82544) {
3181 e1000_config_collision_dist(hw);
3182 } else {
3183 ret_val = e1000_config_mac_to_phy(hw);
3184 if (ret_val) {
3185 DEBUGOUT("Error configuring MAC to PHY settings\n");
3186 return ret_val;
3187 }
3188 }
3189 ret_val = e1000_config_fc_after_link_up(hw);
3190 if (ret_val) {
3191 DEBUGOUT("Error Configuring Flow Control\n");
3192 return ret_val;
3193 }
3194 return E1000_SUCCESS;
3195}
3196
3197
3198
3199
3200
3201
3202static int
3203e1000_setup_copper_link(struct e1000_hw *hw)
3204{
3205 int32_t ret_val;
3206 uint16_t i;
3207 uint16_t phy_data;
3208 uint16_t reg_data;
3209
3210 DEBUGFUNC();
3211
3212 switch (hw->mac_type) {
3213 case e1000_80003es2lan:
3214 case e1000_ich8lan:
3215
3216
3217
3218 ret_val = e1000_write_kmrn_reg(hw,
3219 GG82563_REG(0x34, 4), 0xFFFF);
3220 if (ret_val)
3221 return ret_val;
3222 ret_val = e1000_read_kmrn_reg(hw,
3223 GG82563_REG(0x34, 9), ®_data);
3224 if (ret_val)
3225 return ret_val;
3226 reg_data |= 0x3F;
3227 ret_val = e1000_write_kmrn_reg(hw,
3228 GG82563_REG(0x34, 9), reg_data);
3229 if (ret_val)
3230 return ret_val;
3231 default:
3232 break;
3233 }
3234
3235
3236 ret_val = e1000_copper_link_preconfig(hw);
3237 if (ret_val)
3238 return ret_val;
3239 switch (hw->mac_type) {
3240 case e1000_80003es2lan:
3241
3242 reg_data =
3243 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3244 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3245 ret_val = e1000_write_kmrn_reg(hw,
3246 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3247 if (ret_val)
3248 return ret_val;
3249 break;
3250 default:
3251 break;
3252 }
3253
3254 if (hw->phy_type == e1000_phy_igp ||
3255 hw->phy_type == e1000_phy_igp_3 ||
3256 hw->phy_type == e1000_phy_igp_2) {
3257 ret_val = e1000_copper_link_igp_setup(hw);
3258 if (ret_val)
3259 return ret_val;
3260 } else if (hw->phy_type == e1000_phy_m88 ||
3261 hw->phy_type == e1000_phy_igb) {
3262 ret_val = e1000_copper_link_mgp_setup(hw);
3263 if (ret_val)
3264 return ret_val;
3265 } else if (hw->phy_type == e1000_phy_gg82563) {
3266 ret_val = e1000_copper_link_ggp_setup(hw);
3267 if (ret_val)
3268 return ret_val;
3269 }
3270
3271
3272
3273
3274 ret_val = e1000_copper_link_autoneg(hw);
3275 if (ret_val)
3276 return ret_val;
3277
3278
3279
3280
3281 for (i = 0; i < 10; i++) {
3282 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3283 if (ret_val)
3284 return ret_val;
3285 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3286 if (ret_val)
3287 return ret_val;
3288
3289 if (phy_data & MII_SR_LINK_STATUS) {
3290
3291 ret_val = e1000_copper_link_postconfig(hw);
3292 if (ret_val)
3293 return ret_val;
3294
3295 DEBUGOUT("Valid link established!!!\n");
3296 return E1000_SUCCESS;
3297 }
3298 udelay(10);
3299 }
3300
3301 DEBUGOUT("Unable to establish link!!!\n");
3302 return E1000_SUCCESS;
3303}
3304
3305
3306
3307
3308
3309
3310int32_t
3311e1000_phy_setup_autoneg(struct e1000_hw *hw)
3312{
3313 int32_t ret_val;
3314 uint16_t mii_autoneg_adv_reg;
3315 uint16_t mii_1000t_ctrl_reg;
3316
3317 DEBUGFUNC();
3318
3319
3320 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3321 if (ret_val)
3322 return ret_val;
3323
3324 if (hw->phy_type != e1000_phy_ife) {
3325
3326 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3327 &mii_1000t_ctrl_reg);
3328 if (ret_val)
3329 return ret_val;
3330 } else
3331 mii_1000t_ctrl_reg = 0;
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3345 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3346
3347 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3348
3349
3350 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3351 DEBUGOUT("Advertise 10mb Half duplex\n");
3352 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3353 }
3354
3355
3356 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3357 DEBUGOUT("Advertise 10mb Full duplex\n");
3358 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3359 }
3360
3361
3362 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3363 DEBUGOUT("Advertise 100mb Half duplex\n");
3364 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3365 }
3366
3367
3368 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3369 DEBUGOUT("Advertise 100mb Full duplex\n");
3370 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3371 }
3372
3373
3374 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3375 DEBUGOUT
3376 ("Advertise 1000mb Half duplex requested, request denied!\n");
3377 }
3378
3379
3380 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3381 DEBUGOUT("Advertise 1000mb Full duplex\n");
3382 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3383 }
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401 switch (hw->fc) {
3402 case e1000_fc_none:
3403
3404
3405
3406 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3407 break;
3408 case e1000_fc_rx_pause:
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3419 break;
3420 case e1000_fc_tx_pause:
3421
3422
3423
3424 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3425 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3426 break;
3427 case e1000_fc_full:
3428
3429
3430
3431 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3432 break;
3433 default:
3434 DEBUGOUT("Flow control param set incorrectly\n");
3435 return -E1000_ERR_CONFIG;
3436 }
3437
3438 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3439 if (ret_val)
3440 return ret_val;
3441
3442 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3443
3444 if (hw->phy_type != e1000_phy_ife) {
3445 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3446 mii_1000t_ctrl_reg);
3447 if (ret_val)
3448 return ret_val;
3449 }
3450
3451 return E1000_SUCCESS;
3452}
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462static void
3463e1000_config_collision_dist(struct e1000_hw *hw)
3464{
3465 uint32_t tctl, coll_dist;
3466
3467 DEBUGFUNC();
3468
3469 if (hw->mac_type < e1000_82543)
3470 coll_dist = E1000_COLLISION_DISTANCE_82542;
3471 else
3472 coll_dist = E1000_COLLISION_DISTANCE;
3473
3474 tctl = E1000_READ_REG(hw, TCTL);
3475
3476 tctl &= ~E1000_TCTL_COLD;
3477 tctl |= coll_dist << E1000_COLD_SHIFT;
3478
3479 E1000_WRITE_REG(hw, TCTL, tctl);
3480 E1000_WRITE_FLUSH(hw);
3481}
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492static int
3493e1000_config_mac_to_phy(struct e1000_hw *hw)
3494{
3495 uint32_t ctrl;
3496 uint16_t phy_data;
3497
3498 DEBUGFUNC();
3499
3500
3501
3502
3503 ctrl = E1000_READ_REG(hw, CTRL);
3504 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3505 ctrl &= ~(E1000_CTRL_ILOS);
3506 ctrl |= (E1000_CTRL_SPD_SEL);
3507
3508
3509
3510
3511 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3512 DEBUGOUT("PHY Read Error\n");
3513 return -E1000_ERR_PHY;
3514 }
3515 if (phy_data & M88E1000_PSSR_DPLX)
3516 ctrl |= E1000_CTRL_FD;
3517 else
3518 ctrl &= ~E1000_CTRL_FD;
3519
3520 e1000_config_collision_dist(hw);
3521
3522
3523
3524
3525 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3526 ctrl |= E1000_CTRL_SPD_1000;
3527 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3528 ctrl |= E1000_CTRL_SPD_100;
3529
3530 E1000_WRITE_REG(hw, CTRL, ctrl);
3531 return 0;
3532}
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545static int
3546e1000_force_mac_fc(struct e1000_hw *hw)
3547{
3548 uint32_t ctrl;
3549
3550 DEBUGFUNC();
3551
3552
3553 ctrl = E1000_READ_REG(hw, CTRL);
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573 switch (hw->fc) {
3574 case e1000_fc_none:
3575 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3576 break;
3577 case e1000_fc_rx_pause:
3578 ctrl &= (~E1000_CTRL_TFCE);
3579 ctrl |= E1000_CTRL_RFCE;
3580 break;
3581 case e1000_fc_tx_pause:
3582 ctrl &= (~E1000_CTRL_RFCE);
3583 ctrl |= E1000_CTRL_TFCE;
3584 break;
3585 case e1000_fc_full:
3586 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3587 break;
3588 default:
3589 DEBUGOUT("Flow control param set incorrectly\n");
3590 return -E1000_ERR_CONFIG;
3591 }
3592
3593
3594 if (hw->mac_type == e1000_82542_rev2_0)
3595 ctrl &= (~E1000_CTRL_TFCE);
3596
3597 E1000_WRITE_REG(hw, CTRL, ctrl);
3598 return 0;
3599}
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612static int32_t
3613e1000_config_fc_after_link_up(struct e1000_hw *hw)
3614{
3615 int32_t ret_val;
3616 uint16_t mii_status_reg;
3617 uint16_t mii_nway_adv_reg;
3618 uint16_t mii_nway_lp_ability_reg;
3619 uint16_t speed;
3620 uint16_t duplex;
3621
3622 DEBUGFUNC();
3623
3624
3625
3626
3627
3628 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3629 || ((hw->media_type == e1000_media_type_internal_serdes)
3630 && (hw->autoneg_failed))
3631 || ((hw->media_type == e1000_media_type_copper)
3632 && (!hw->autoneg))) {
3633 ret_val = e1000_force_mac_fc(hw);
3634 if (ret_val < 0) {
3635 DEBUGOUT("Error forcing flow control settings\n");
3636 return ret_val;
3637 }
3638 }
3639
3640
3641
3642
3643
3644
3645 if (hw->media_type == e1000_media_type_copper) {
3646
3647
3648
3649
3650 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3651 DEBUGOUT("PHY Read Error\n");
3652 return -E1000_ERR_PHY;
3653 }
3654 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3655 DEBUGOUT("PHY Read Error\n");
3656 return -E1000_ERR_PHY;
3657 }
3658
3659 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3660
3661
3662
3663
3664
3665
3666 if (e1000_read_phy_reg
3667 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3668 DEBUGOUT("PHY Read Error\n");
3669 return -E1000_ERR_PHY;
3670 }
3671 if (e1000_read_phy_reg
3672 (hw, PHY_LP_ABILITY,
3673 &mii_nway_lp_ability_reg) < 0) {
3674 DEBUGOUT("PHY Read Error\n");
3675 return -E1000_ERR_PHY;
3676 }
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3713 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3714
3715
3716
3717
3718
3719
3720 if (hw->original_fc == e1000_fc_full) {
3721 hw->fc = e1000_fc_full;
3722 DEBUGOUT("Flow Control = FULL.\r\n");
3723 } else {
3724 hw->fc = e1000_fc_rx_pause;
3725 DEBUGOUT
3726 ("Flow Control = RX PAUSE frames only.\r\n");
3727 }
3728 }
3729
3730
3731
3732
3733
3734
3735
3736
3737 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3738 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3739 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3740 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3741 {
3742 hw->fc = e1000_fc_tx_pause;
3743 DEBUGOUT
3744 ("Flow Control = TX PAUSE frames only.\r\n");
3745 }
3746
3747
3748
3749
3750
3751
3752
3753
3754 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3755 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3756 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3757 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3758 {
3759 hw->fc = e1000_fc_rx_pause;
3760 DEBUGOUT
3761 ("Flow Control = RX PAUSE frames only.\r\n");
3762 }
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783 else if (hw->original_fc == e1000_fc_none ||
3784 hw->original_fc == e1000_fc_tx_pause) {
3785 hw->fc = e1000_fc_none;
3786 DEBUGOUT("Flow Control = NONE.\r\n");
3787 } else {
3788 hw->fc = e1000_fc_rx_pause;
3789 DEBUGOUT
3790 ("Flow Control = RX PAUSE frames only.\r\n");
3791 }
3792
3793
3794
3795
3796
3797 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3798
3799 if (duplex == HALF_DUPLEX)
3800 hw->fc = e1000_fc_none;
3801
3802
3803
3804
3805 ret_val = e1000_force_mac_fc(hw);
3806 if (ret_val < 0) {
3807 DEBUGOUT
3808 ("Error forcing flow control settings\n");
3809 return ret_val;
3810 }
3811 } else {
3812 DEBUGOUT
3813 ("Copper PHY and Auto Neg has not completed.\r\n");
3814 }
3815 }
3816 return E1000_SUCCESS;
3817}
3818
3819
3820
3821
3822
3823
3824
3825
3826static int
3827e1000_check_for_link(struct e1000_hw *hw)
3828{
3829 uint32_t rxcw;
3830 uint32_t ctrl;
3831 uint32_t status;
3832 uint32_t rctl;
3833 uint32_t signal;
3834 int32_t ret_val;
3835 uint16_t phy_data;
3836 uint16_t lp_capability;
3837
3838 DEBUGFUNC();
3839
3840
3841
3842
3843
3844 ctrl = E1000_READ_REG(hw, CTRL);
3845 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3846 signal = E1000_CTRL_SWDPIN1;
3847 else
3848 signal = 0;
3849
3850 status = E1000_READ_REG(hw, STATUS);
3851 rxcw = E1000_READ_REG(hw, RXCW);
3852 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3853
3854
3855
3856
3857
3858
3859
3860 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3861
3862
3863
3864
3865
3866 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3867 DEBUGOUT("PHY Read Error\n");
3868 return -E1000_ERR_PHY;
3869 }
3870 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3871 DEBUGOUT("PHY Read Error\n");
3872 return -E1000_ERR_PHY;
3873 }
3874
3875 if (phy_data & MII_SR_LINK_STATUS) {
3876 hw->get_link_status = false;
3877 } else {
3878
3879 return -E1000_ERR_NOLINK;
3880 }
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890 if (hw->mac_type >= e1000_82544)
3891 e1000_config_collision_dist(hw);
3892 else {
3893 ret_val = e1000_config_mac_to_phy(hw);
3894 if (ret_val < 0) {
3895 DEBUGOUT
3896 ("Error configuring MAC to PHY settings\n");
3897 return ret_val;
3898 }
3899 }
3900
3901
3902
3903
3904
3905 ret_val = e1000_config_fc_after_link_up(hw);
3906 if (ret_val < 0) {
3907 DEBUGOUT("Error configuring flow control\n");
3908 return ret_val;
3909 }
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920 if (hw->tbi_compatibility_en) {
3921 if (e1000_read_phy_reg
3922 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3923 DEBUGOUT("PHY Read Error\n");
3924 return -E1000_ERR_PHY;
3925 }
3926 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3927 NWAY_LPAR_10T_FD_CAPS |
3928 NWAY_LPAR_100TX_HD_CAPS |
3929 NWAY_LPAR_100TX_FD_CAPS |
3930 NWAY_LPAR_100T4_CAPS)) {
3931
3932
3933
3934 if (hw->tbi_compatibility_on) {
3935
3936 rctl = E1000_READ_REG(hw, RCTL);
3937 rctl &= ~E1000_RCTL_SBP;
3938 E1000_WRITE_REG(hw, RCTL, rctl);
3939 hw->tbi_compatibility_on = false;
3940 }
3941 } else {
3942
3943
3944
3945
3946
3947 if (!hw->tbi_compatibility_on) {
3948 hw->tbi_compatibility_on = true;
3949 rctl = E1000_READ_REG(hw, RCTL);
3950 rctl |= E1000_RCTL_SBP;
3951 E1000_WRITE_REG(hw, RCTL, rctl);
3952 }
3953 }
3954 }
3955 }
3956
3957
3958
3959
3960
3961
3962
3963 else if ((hw->media_type == e1000_media_type_fiber) &&
3964 (!(status & E1000_STATUS_LU)) &&
3965 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3966 (!(rxcw & E1000_RXCW_C))) {
3967 if (hw->autoneg_failed == 0) {
3968 hw->autoneg_failed = 1;
3969 return 0;
3970 }
3971 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3972
3973
3974 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3975
3976
3977 ctrl = E1000_READ_REG(hw, CTRL);
3978 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3979 E1000_WRITE_REG(hw, CTRL, ctrl);
3980
3981
3982 ret_val = e1000_config_fc_after_link_up(hw);
3983 if (ret_val < 0) {
3984 DEBUGOUT("Error configuring flow control\n");
3985 return ret_val;
3986 }
3987 }
3988
3989
3990
3991
3992
3993 else if ((hw->media_type == e1000_media_type_fiber) &&
3994 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3995 DEBUGOUT
3996 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3997 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3998 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3999 }
4000 return 0;
4001}
4002
4003
4004
4005
4006
4007
4008static int32_t
4009e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4010{
4011 int32_t ret_val = E1000_SUCCESS;
4012 uint32_t tipg;
4013 uint16_t reg_data;
4014
4015 DEBUGFUNC();
4016
4017 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4018 ret_val = e1000_write_kmrn_reg(hw,
4019 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4020 if (ret_val)
4021 return ret_val;
4022
4023
4024 tipg = E1000_READ_REG(hw, TIPG);
4025 tipg &= ~E1000_TIPG_IPGT_MASK;
4026 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4027 E1000_WRITE_REG(hw, TIPG, tipg);
4028
4029 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4030
4031 if (ret_val)
4032 return ret_val;
4033
4034 if (duplex == HALF_DUPLEX)
4035 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4036 else
4037 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4038
4039 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4040
4041 return ret_val;
4042}
4043
4044static int32_t
4045e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4046{
4047 int32_t ret_val = E1000_SUCCESS;
4048 uint16_t reg_data;
4049 uint32_t tipg;
4050
4051 DEBUGFUNC();
4052
4053 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4054 ret_val = e1000_write_kmrn_reg(hw,
4055 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4056 if (ret_val)
4057 return ret_val;
4058
4059
4060 tipg = E1000_READ_REG(hw, TIPG);
4061 tipg &= ~E1000_TIPG_IPGT_MASK;
4062 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4063 E1000_WRITE_REG(hw, TIPG, tipg);
4064
4065 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4066
4067 if (ret_val)
4068 return ret_val;
4069
4070 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4071 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4072
4073 return ret_val;
4074}
4075
4076
4077
4078
4079
4080
4081
4082
4083static int
4084e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4085 uint16_t *duplex)
4086{
4087 uint32_t status;
4088 int32_t ret_val;
4089 uint16_t phy_data;
4090
4091 DEBUGFUNC();
4092
4093 if (hw->mac_type >= e1000_82543) {
4094 status = E1000_READ_REG(hw, STATUS);
4095 if (status & E1000_STATUS_SPEED_1000) {
4096 *speed = SPEED_1000;
4097 DEBUGOUT("1000 Mbs, ");
4098 } else if (status & E1000_STATUS_SPEED_100) {
4099 *speed = SPEED_100;
4100 DEBUGOUT("100 Mbs, ");
4101 } else {
4102 *speed = SPEED_10;
4103 DEBUGOUT("10 Mbs, ");
4104 }
4105
4106 if (status & E1000_STATUS_FD) {
4107 *duplex = FULL_DUPLEX;
4108 DEBUGOUT("Full Duplex\r\n");
4109 } else {
4110 *duplex = HALF_DUPLEX;
4111 DEBUGOUT(" Half Duplex\r\n");
4112 }
4113 } else {
4114 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4115 *speed = SPEED_1000;
4116 *duplex = FULL_DUPLEX;
4117 }
4118
4119
4120
4121
4122
4123 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4124 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4125 if (ret_val)
4126 return ret_val;
4127
4128 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4129 *duplex = HALF_DUPLEX;
4130 else {
4131 ret_val = e1000_read_phy_reg(hw,
4132 PHY_LP_ABILITY, &phy_data);
4133 if (ret_val)
4134 return ret_val;
4135 if ((*speed == SPEED_100 &&
4136 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4137 || (*speed == SPEED_10
4138 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4139 *duplex = HALF_DUPLEX;
4140 }
4141 }
4142
4143 if ((hw->mac_type == e1000_80003es2lan) &&
4144 (hw->media_type == e1000_media_type_copper)) {
4145 if (*speed == SPEED_1000)
4146 ret_val = e1000_configure_kmrn_for_1000(hw);
4147 else
4148 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4149 if (ret_val)
4150 return ret_val;
4151 }
4152 return E1000_SUCCESS;
4153}
4154
4155
4156
4157
4158
4159
4160static int
4161e1000_wait_autoneg(struct e1000_hw *hw)
4162{
4163 uint16_t i;
4164 uint16_t phy_data;
4165
4166 DEBUGFUNC();
4167 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4168
4169
4170 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4171
4172
4173
4174 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4175 DEBUGOUT("PHY Read Error\n");
4176 return -E1000_ERR_PHY;
4177 }
4178 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4179 DEBUGOUT("PHY Read Error\n");
4180 return -E1000_ERR_PHY;
4181 }
4182 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4183 DEBUGOUT("Auto-Neg complete.\n");
4184 return 0;
4185 }
4186 mdelay(100);
4187 }
4188 DEBUGOUT("Auto-Neg timedout.\n");
4189 return -E1000_ERR_TIMEOUT;
4190}
4191
4192
4193
4194
4195
4196
4197
4198static void
4199e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4200{
4201
4202
4203
4204 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4205 E1000_WRITE_FLUSH(hw);
4206 udelay(2);
4207}
4208
4209
4210
4211
4212
4213
4214
4215static void
4216e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4217{
4218
4219
4220
4221 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4222 E1000_WRITE_FLUSH(hw);
4223 udelay(2);
4224}
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235static void
4236e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4237{
4238 uint32_t ctrl;
4239 uint32_t mask;
4240
4241
4242
4243
4244
4245 mask = 0x01;
4246 mask <<= (count - 1);
4247
4248 ctrl = E1000_READ_REG(hw, CTRL);
4249
4250
4251 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4252
4253 while (mask) {
4254
4255
4256
4257
4258
4259 if (data & mask)
4260 ctrl |= E1000_CTRL_MDIO;
4261 else
4262 ctrl &= ~E1000_CTRL_MDIO;
4263
4264 E1000_WRITE_REG(hw, CTRL, ctrl);
4265 E1000_WRITE_FLUSH(hw);
4266
4267 udelay(2);
4268
4269 e1000_raise_mdi_clk(hw, &ctrl);
4270 e1000_lower_mdi_clk(hw, &ctrl);
4271
4272 mask = mask >> 1;
4273 }
4274}
4275
4276
4277
4278
4279
4280
4281
4282
4283static uint16_t
4284e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4285{
4286 uint32_t ctrl;
4287 uint16_t data = 0;
4288 uint8_t i;
4289
4290
4291
4292
4293
4294
4295
4296
4297 ctrl = E1000_READ_REG(hw, CTRL);
4298
4299
4300 ctrl &= ~E1000_CTRL_MDIO_DIR;
4301 ctrl &= ~E1000_CTRL_MDIO;
4302
4303 E1000_WRITE_REG(hw, CTRL, ctrl);
4304 E1000_WRITE_FLUSH(hw);
4305
4306
4307
4308
4309
4310 e1000_raise_mdi_clk(hw, &ctrl);
4311 e1000_lower_mdi_clk(hw, &ctrl);
4312
4313 for (data = 0, i = 0; i < 16; i++) {
4314 data = data << 1;
4315 e1000_raise_mdi_clk(hw, &ctrl);
4316 ctrl = E1000_READ_REG(hw, CTRL);
4317
4318 if (ctrl & E1000_CTRL_MDIO)
4319 data |= 1;
4320 e1000_lower_mdi_clk(hw, &ctrl);
4321 }
4322
4323 e1000_raise_mdi_clk(hw, &ctrl);
4324 e1000_lower_mdi_clk(hw, &ctrl);
4325
4326 return data;
4327}
4328
4329
4330
4331
4332
4333
4334
4335static int
4336e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4337{
4338 uint32_t i;
4339 uint32_t mdic = 0;
4340 const uint32_t phy_addr = 1;
4341
4342 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4343 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4344 return -E1000_ERR_PARAM;
4345 }
4346
4347 if (hw->mac_type > e1000_82543) {
4348
4349
4350
4351
4352 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4353 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4354 (E1000_MDIC_OP_READ));
4355
4356 E1000_WRITE_REG(hw, MDIC, mdic);
4357
4358
4359 for (i = 0; i < 64; i++) {
4360 udelay(10);
4361 mdic = E1000_READ_REG(hw, MDIC);
4362 if (mdic & E1000_MDIC_READY)
4363 break;
4364 }
4365 if (!(mdic & E1000_MDIC_READY)) {
4366 DEBUGOUT("MDI Read did not complete\n");
4367 return -E1000_ERR_PHY;
4368 }
4369 if (mdic & E1000_MDIC_ERROR) {
4370 DEBUGOUT("MDI Error\n");
4371 return -E1000_ERR_PHY;
4372 }
4373 *phy_data = (uint16_t) mdic;
4374 } else {
4375
4376
4377
4378
4379 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392 mdic = ((reg_addr) | (phy_addr << 5) |
4393 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4394
4395 e1000_shift_out_mdi_bits(hw, mdic, 14);
4396
4397
4398
4399
4400
4401 *phy_data = e1000_shift_in_mdi_bits(hw);
4402 }
4403 return 0;
4404}
4405
4406
4407
4408
4409
4410
4411
4412
4413static int
4414e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4415{
4416 uint32_t i;
4417 uint32_t mdic = 0;
4418 const uint32_t phy_addr = 1;
4419
4420 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4421 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4422 return -E1000_ERR_PARAM;
4423 }
4424
4425 if (hw->mac_type > e1000_82543) {
4426
4427
4428
4429
4430 mdic = (((uint32_t) phy_data) |
4431 (reg_addr << E1000_MDIC_REG_SHIFT) |
4432 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4433 (E1000_MDIC_OP_WRITE));
4434
4435 E1000_WRITE_REG(hw, MDIC, mdic);
4436
4437
4438 for (i = 0; i < 64; i++) {
4439 udelay(10);
4440 mdic = E1000_READ_REG(hw, MDIC);
4441 if (mdic & E1000_MDIC_READY)
4442 break;
4443 }
4444 if (!(mdic & E1000_MDIC_READY)) {
4445 DEBUGOUT("MDI Write did not complete\n");
4446 return -E1000_ERR_PHY;
4447 }
4448 } else {
4449
4450
4451
4452
4453
4454 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4455
4456
4457
4458
4459
4460
4461
4462 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4463 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4464 mdic <<= 16;
4465 mdic |= (uint32_t) phy_data;
4466
4467 e1000_shift_out_mdi_bits(hw, mdic, 32);
4468 }
4469 return 0;
4470}
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483int32_t
4484e1000_check_phy_reset_block(struct e1000_hw *hw)
4485{
4486 uint32_t manc = 0;
4487 uint32_t fwsm = 0;
4488
4489 if (hw->mac_type == e1000_ich8lan) {
4490 fwsm = E1000_READ_REG(hw, FWSM);
4491 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4492 : E1000_BLK_PHY_RESET;
4493 }
4494
4495 if (hw->mac_type > e1000_82547_rev_2)
4496 manc = E1000_READ_REG(hw, MANC);
4497 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4498 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4499}
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510static int32_t
4511e1000_get_phy_cfg_done(struct e1000_hw *hw)
4512{
4513 int32_t timeout = PHY_CFG_TIMEOUT;
4514 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4515
4516 DEBUGFUNC();
4517
4518 switch (hw->mac_type) {
4519 default:
4520 mdelay(10);
4521 break;
4522
4523 case e1000_80003es2lan:
4524
4525 if (e1000_is_second_port(hw))
4526 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4527
4528
4529 case e1000_82571:
4530 case e1000_82572:
4531 case e1000_igb:
4532 while (timeout) {
4533 if (hw->mac_type == e1000_igb) {
4534 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4535 break;
4536 } else {
4537 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4538 break;
4539 }
4540 mdelay(1);
4541 timeout--;
4542 }
4543 if (!timeout) {
4544 DEBUGOUT("MNG configuration cycle has not "
4545 "completed.\n");
4546 return -E1000_ERR_RESET;
4547 }
4548 break;
4549 }
4550
4551 return E1000_SUCCESS;
4552}
4553
4554
4555
4556
4557
4558
4559int32_t
4560e1000_phy_hw_reset(struct e1000_hw *hw)
4561{
4562 uint16_t swfw = E1000_SWFW_PHY0_SM;
4563 uint32_t ctrl, ctrl_ext;
4564 uint32_t led_ctrl;
4565 int32_t ret_val;
4566
4567 DEBUGFUNC();
4568
4569
4570
4571 ret_val = e1000_check_phy_reset_block(hw);
4572 if (ret_val)
4573 return E1000_SUCCESS;
4574
4575 DEBUGOUT("Resetting Phy...\n");
4576
4577 if (hw->mac_type > e1000_82543) {
4578 if (e1000_is_second_port(hw))
4579 swfw = E1000_SWFW_PHY1_SM;
4580
4581 if (e1000_swfw_sync_acquire(hw, swfw)) {
4582 DEBUGOUT("Unable to acquire swfw sync\n");
4583 return -E1000_ERR_SWFW_SYNC;
4584 }
4585
4586
4587
4588
4589 ctrl = E1000_READ_REG(hw, CTRL);
4590 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4591 E1000_WRITE_FLUSH(hw);
4592
4593 if (hw->mac_type < e1000_82571)
4594 udelay(10);
4595 else
4596 udelay(100);
4597
4598 E1000_WRITE_REG(hw, CTRL, ctrl);
4599 E1000_WRITE_FLUSH(hw);
4600
4601 if (hw->mac_type >= e1000_82571)
4602 mdelay(10);
4603
4604 } else {
4605
4606
4607
4608 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4609 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4610 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4611 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4612 E1000_WRITE_FLUSH(hw);
4613 mdelay(10);
4614 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4615 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4616 E1000_WRITE_FLUSH(hw);
4617 }
4618 udelay(150);
4619
4620 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4621
4622 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4623 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4624 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4625 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4626 }
4627
4628 e1000_swfw_sync_release(hw, swfw);
4629
4630
4631 ret_val = e1000_get_phy_cfg_done(hw);
4632 if (ret_val != E1000_SUCCESS)
4633 return ret_val;
4634
4635 return ret_val;
4636}
4637
4638
4639
4640
4641
4642
4643static void
4644e1000_phy_init_script(struct e1000_hw *hw)
4645{
4646 uint32_t ret_val;
4647 uint16_t phy_saved_data;
4648 DEBUGFUNC();
4649
4650 if (hw->phy_init_script) {
4651 mdelay(20);
4652
4653
4654
4655 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4656
4657
4658 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4659
4660 mdelay(20);
4661
4662 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4663
4664 mdelay(5);
4665
4666 switch (hw->mac_type) {
4667 case e1000_82541:
4668 case e1000_82547:
4669 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4670
4671 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4672
4673 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4674
4675 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4676
4677 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4678
4679 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4680
4681 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4682
4683 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4684
4685 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4686 break;
4687
4688 case e1000_82541_rev_2:
4689 case e1000_82547_rev_2:
4690 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4691 break;
4692 default:
4693 break;
4694 }
4695
4696 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4697
4698 mdelay(20);
4699
4700
4701 if (!ret_val)
4702 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4703
4704 if (hw->mac_type == e1000_82547) {
4705 uint16_t fused, fine, coarse;
4706
4707
4708 e1000_read_phy_reg(hw,
4709 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4710
4711 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4712 e1000_read_phy_reg(hw,
4713 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4714
4715 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4716 coarse = fused
4717 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4718
4719 if (coarse >
4720 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4721 coarse -=
4722 IGP01E1000_ANALOG_FUSE_COARSE_10;
4723 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4724 } else if (coarse
4725 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4726 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4727
4728 fused = (fused
4729 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4730 (fine
4731 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4732 (coarse
4733 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4734
4735 e1000_write_phy_reg(hw,
4736 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4737 e1000_write_phy_reg(hw,
4738 IGP01E1000_ANALOG_FUSE_BYPASS,
4739 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4740 }
4741 }
4742 }
4743}
4744
4745
4746
4747
4748
4749
4750
4751
4752int32_t
4753e1000_phy_reset(struct e1000_hw *hw)
4754{
4755 int32_t ret_val;
4756 uint16_t phy_data;
4757
4758 DEBUGFUNC();
4759
4760
4761
4762 ret_val = e1000_check_phy_reset_block(hw);
4763 if (ret_val)
4764 return E1000_SUCCESS;
4765
4766 switch (hw->phy_type) {
4767 case e1000_phy_igp:
4768 case e1000_phy_igp_2:
4769 case e1000_phy_igp_3:
4770 case e1000_phy_ife:
4771 case e1000_phy_igb:
4772 ret_val = e1000_phy_hw_reset(hw);
4773 if (ret_val)
4774 return ret_val;
4775 break;
4776 default:
4777 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4778 if (ret_val)
4779 return ret_val;
4780
4781 phy_data |= MII_CR_RESET;
4782 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4783 if (ret_val)
4784 return ret_val;
4785
4786 udelay(1);
4787 break;
4788 }
4789
4790 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4791 e1000_phy_init_script(hw);
4792
4793 return E1000_SUCCESS;
4794}
4795
4796static int e1000_set_phy_type (struct e1000_hw *hw)
4797{
4798 DEBUGFUNC ();
4799
4800 if (hw->mac_type == e1000_undefined)
4801 return -E1000_ERR_PHY_TYPE;
4802
4803 switch (hw->phy_id) {
4804 case M88E1000_E_PHY_ID:
4805 case M88E1000_I_PHY_ID:
4806 case M88E1011_I_PHY_ID:
4807 case M88E1111_I_PHY_ID:
4808 hw->phy_type = e1000_phy_m88;
4809 break;
4810 case IGP01E1000_I_PHY_ID:
4811 if (hw->mac_type == e1000_82541 ||
4812 hw->mac_type == e1000_82541_rev_2 ||
4813 hw->mac_type == e1000_82547 ||
4814 hw->mac_type == e1000_82547_rev_2) {
4815 hw->phy_type = e1000_phy_igp;
4816 break;
4817 }
4818 case IGP03E1000_E_PHY_ID:
4819 hw->phy_type = e1000_phy_igp_3;
4820 break;
4821 case IFE_E_PHY_ID:
4822 case IFE_PLUS_E_PHY_ID:
4823 case IFE_C_E_PHY_ID:
4824 hw->phy_type = e1000_phy_ife;
4825 break;
4826 case GG82563_E_PHY_ID:
4827 if (hw->mac_type == e1000_80003es2lan) {
4828 hw->phy_type = e1000_phy_gg82563;
4829 break;
4830 }
4831 case BME1000_E_PHY_ID:
4832 hw->phy_type = e1000_phy_bm;
4833 break;
4834 case I210_I_PHY_ID:
4835 hw->phy_type = e1000_phy_igb;
4836 break;
4837
4838 default:
4839
4840 hw->phy_type = e1000_phy_undefined;
4841 return -E1000_ERR_PHY_TYPE;
4842 }
4843
4844 return E1000_SUCCESS;
4845}
4846
4847
4848
4849
4850
4851
4852static int32_t
4853e1000_detect_gig_phy(struct e1000_hw *hw)
4854{
4855 int32_t phy_init_status, ret_val;
4856 uint16_t phy_id_high, phy_id_low;
4857 bool match = false;
4858
4859 DEBUGFUNC();
4860
4861
4862
4863
4864 if (hw->mac_type == e1000_82571 ||
4865 hw->mac_type == e1000_82572) {
4866 hw->phy_id = IGP01E1000_I_PHY_ID;
4867 hw->phy_type = e1000_phy_igp_2;
4868 return E1000_SUCCESS;
4869 }
4870
4871
4872
4873
4874
4875
4876
4877 if (hw->mac_type == e1000_80003es2lan)
4878 hw->phy_type = e1000_phy_gg82563;
4879
4880
4881 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4882 if (ret_val)
4883 return ret_val;
4884
4885 hw->phy_id = (uint32_t) (phy_id_high << 16);
4886 udelay(20);
4887 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4888 if (ret_val)
4889 return ret_val;
4890
4891 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4892 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4893
4894 switch (hw->mac_type) {
4895 case e1000_82543:
4896 if (hw->phy_id == M88E1000_E_PHY_ID)
4897 match = true;
4898 break;
4899 case e1000_82544:
4900 if (hw->phy_id == M88E1000_I_PHY_ID)
4901 match = true;
4902 break;
4903 case e1000_82540:
4904 case e1000_82545:
4905 case e1000_82545_rev_3:
4906 case e1000_82546:
4907 case e1000_82546_rev_3:
4908 if (hw->phy_id == M88E1011_I_PHY_ID)
4909 match = true;
4910 break;
4911 case e1000_82541:
4912 case e1000_82541_rev_2:
4913 case e1000_82547:
4914 case e1000_82547_rev_2:
4915 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4916 match = true;
4917
4918 break;
4919 case e1000_82573:
4920 if (hw->phy_id == M88E1111_I_PHY_ID)
4921 match = true;
4922 break;
4923 case e1000_82574:
4924 if (hw->phy_id == BME1000_E_PHY_ID)
4925 match = true;
4926 break;
4927 case e1000_80003es2lan:
4928 if (hw->phy_id == GG82563_E_PHY_ID)
4929 match = true;
4930 break;
4931 case e1000_ich8lan:
4932 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4933 match = true;
4934 if (hw->phy_id == IFE_E_PHY_ID)
4935 match = true;
4936 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4937 match = true;
4938 if (hw->phy_id == IFE_C_E_PHY_ID)
4939 match = true;
4940 break;
4941 case e1000_igb:
4942 if (hw->phy_id == I210_I_PHY_ID)
4943 match = true;
4944 break;
4945 default:
4946 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4947 return -E1000_ERR_CONFIG;
4948 }
4949
4950 phy_init_status = e1000_set_phy_type(hw);
4951
4952 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4953 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4954 return 0;
4955 }
4956 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4957 return -E1000_ERR_PHY;
4958}
4959
4960
4961
4962
4963
4964
4965void
4966e1000_set_media_type(struct e1000_hw *hw)
4967{
4968 uint32_t status;
4969
4970 DEBUGFUNC();
4971
4972 if (hw->mac_type != e1000_82543) {
4973
4974 hw->tbi_compatibility_en = false;
4975 }
4976
4977 switch (hw->device_id) {
4978 case E1000_DEV_ID_82545GM_SERDES:
4979 case E1000_DEV_ID_82546GB_SERDES:
4980 case E1000_DEV_ID_82571EB_SERDES:
4981 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4982 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4983 case E1000_DEV_ID_82572EI_SERDES:
4984 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4985 hw->media_type = e1000_media_type_internal_serdes;
4986 break;
4987 default:
4988 switch (hw->mac_type) {
4989 case e1000_82542_rev2_0:
4990 case e1000_82542_rev2_1:
4991 hw->media_type = e1000_media_type_fiber;
4992 break;
4993 case e1000_ich8lan:
4994 case e1000_82573:
4995 case e1000_82574:
4996 case e1000_igb:
4997
4998
4999
5000 hw->media_type = e1000_media_type_copper;
5001 break;
5002 default:
5003 status = E1000_READ_REG(hw, STATUS);
5004 if (status & E1000_STATUS_TBIMODE) {
5005 hw->media_type = e1000_media_type_fiber;
5006
5007 hw->tbi_compatibility_en = false;
5008 } else {
5009 hw->media_type = e1000_media_type_copper;
5010 }
5011 break;
5012 }
5013 }
5014}
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024static int
5025e1000_sw_init(struct e1000_hw *hw)
5026{
5027 int result;
5028
5029
5030 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5031 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5032 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5033 &hw->subsystem_vendor_id);
5034 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5035
5036 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5037 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5038
5039
5040 result = e1000_set_mac_type(hw);
5041 if (result) {
5042 E1000_ERR(hw, "Unknown MAC Type\n");
5043 return result;
5044 }
5045
5046 switch (hw->mac_type) {
5047 default:
5048 break;
5049 case e1000_82541:
5050 case e1000_82547:
5051 case e1000_82541_rev_2:
5052 case e1000_82547_rev_2:
5053 hw->phy_init_script = 1;
5054 break;
5055 }
5056
5057
5058 hw->fc_high_water = E1000_FC_HIGH_THRESH;
5059 hw->fc_low_water = E1000_FC_LOW_THRESH;
5060 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5061 hw->fc_send_xon = 1;
5062
5063
5064 hw->tbi_compatibility_en = true;
5065 e1000_set_media_type(hw);
5066
5067 if (hw->mac_type >= e1000_82543) {
5068 uint32_t status = E1000_READ_REG(hw, STATUS);
5069
5070 if (status & E1000_STATUS_TBIMODE) {
5071 DEBUGOUT("fiber interface\n");
5072 hw->media_type = e1000_media_type_fiber;
5073 } else {
5074 DEBUGOUT("copper interface\n");
5075 hw->media_type = e1000_media_type_copper;
5076 }
5077 } else {
5078 hw->media_type = e1000_media_type_fiber;
5079 }
5080
5081 hw->wait_autoneg_complete = true;
5082 if (hw->mac_type < e1000_82543)
5083 hw->report_tx_early = 0;
5084 else
5085 hw->report_tx_early = 1;
5086
5087 return E1000_SUCCESS;
5088}
5089
5090void
5091fill_rx(struct e1000_hw *hw)
5092{
5093 struct e1000_rx_desc *rd;
5094 unsigned long flush_start, flush_end;
5095
5096 rx_last = rx_tail;
5097 rd = rx_base + rx_tail;
5098 rx_tail = (rx_tail + 1) % 8;
5099 memset(rd, 0, 16);
5100 rd->buffer_addr = cpu_to_le64(virt_to_phys(packet));
5101
5102
5103
5104
5105
5106
5107 invalidate_dcache_range((unsigned long)packet,
5108 (unsigned long)packet + 4096);
5109
5110 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5111 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5112 flush_dcache_range(flush_start, flush_end);
5113
5114 E1000_WRITE_REG(hw, RDT, rx_tail);
5115}
5116
5117
5118
5119
5120
5121
5122
5123
5124static void
5125e1000_configure_tx(struct e1000_hw *hw)
5126{
5127 unsigned long tctl;
5128 unsigned long tipg, tarc;
5129 uint32_t ipgr1, ipgr2;
5130
5131 E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base)));
5132 E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base)));
5133
5134 E1000_WRITE_REG(hw, TDLEN, 128);
5135
5136
5137 E1000_WRITE_REG(hw, TDH, 0);
5138 E1000_WRITE_REG(hw, TDT, 0);
5139 tx_tail = 0;
5140
5141
5142 if (hw->mac_type <= e1000_82547_rev_2 &&
5143 (hw->media_type == e1000_media_type_fiber ||
5144 hw->media_type == e1000_media_type_internal_serdes))
5145 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5146 else
5147 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5148
5149
5150 switch (hw->mac_type) {
5151 case e1000_82542_rev2_0:
5152 case e1000_82542_rev2_1:
5153 tipg = DEFAULT_82542_TIPG_IPGT;
5154 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5155 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5156 break;
5157 case e1000_80003es2lan:
5158 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5159 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5160 break;
5161 default:
5162 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5163 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5164 break;
5165 }
5166 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5167 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5168 E1000_WRITE_REG(hw, TIPG, tipg);
5169
5170 tctl = E1000_READ_REG(hw, TCTL);
5171 tctl &= ~E1000_TCTL_CT;
5172 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5173 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5174
5175 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5176 tarc = E1000_READ_REG(hw, TARC0);
5177
5178
5179
5180 } else if (hw->mac_type == e1000_80003es2lan) {
5181 tarc = E1000_READ_REG(hw, TARC0);
5182 tarc |= 1;
5183 E1000_WRITE_REG(hw, TARC0, tarc);
5184 tarc = E1000_READ_REG(hw, TARC1);
5185 tarc |= 1;
5186 E1000_WRITE_REG(hw, TARC1, tarc);
5187 }
5188
5189
5190 e1000_config_collision_dist(hw);
5191
5192 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5193
5194
5195 if (hw->mac_type < e1000_82543)
5196 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5197 else
5198 hw->txd_cmd |= E1000_TXD_CMD_RS;
5199
5200
5201 if (hw->mac_type == e1000_igb) {
5202 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5203
5204 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5205 reg_txdctl |= 1 << 25;
5206 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5207 mdelay(20);
5208 }
5209
5210 E1000_WRITE_REG(hw, TCTL, tctl);
5211}
5212
5213
5214
5215
5216
5217static void
5218e1000_setup_rctl(struct e1000_hw *hw)
5219{
5220 uint32_t rctl;
5221
5222 rctl = E1000_READ_REG(hw, RCTL);
5223
5224 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5225
5226 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5227 | E1000_RCTL_RDMTS_HALF;
5228
5229
5230 if (hw->tbi_compatibility_on == 1)
5231 rctl |= E1000_RCTL_SBP;
5232 else
5233 rctl &= ~E1000_RCTL_SBP;
5234
5235 rctl &= ~(E1000_RCTL_SZ_4096);
5236 rctl |= E1000_RCTL_SZ_2048;
5237 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5238 E1000_WRITE_REG(hw, RCTL, rctl);
5239}
5240
5241
5242
5243
5244
5245
5246
5247static void
5248e1000_configure_rx(struct e1000_hw *hw)
5249{
5250 unsigned long rctl, ctrl_ext;
5251 rx_tail = 0;
5252
5253
5254 rctl = E1000_READ_REG(hw, RCTL);
5255 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5256 if (hw->mac_type >= e1000_82540) {
5257
5258
5259#define MAX_INTS_PER_SEC 8000
5260#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5261 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5262 }
5263
5264 if (hw->mac_type >= e1000_82571) {
5265 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5266
5267 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5268 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5269 E1000_WRITE_FLUSH(hw);
5270 }
5271
5272 E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base)));
5273 E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base)));
5274
5275 E1000_WRITE_REG(hw, RDLEN, 128);
5276
5277
5278 E1000_WRITE_REG(hw, RDH, 0);
5279 E1000_WRITE_REG(hw, RDT, 0);
5280
5281
5282 if (hw->mac_type == e1000_igb) {
5283
5284 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5285 reg_rxdctl |= 1 << 25;
5286 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5287 mdelay(20);
5288 }
5289
5290 E1000_WRITE_REG(hw, RCTL, rctl);
5291
5292 fill_rx(hw);
5293}
5294
5295
5296
5297
5298static int
5299_e1000_poll(struct e1000_hw *hw)
5300{
5301 struct e1000_rx_desc *rd;
5302 unsigned long inval_start, inval_end;
5303 uint32_t len;
5304
5305
5306 rd = rx_base + rx_last;
5307
5308
5309 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5310 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5311 invalidate_dcache_range(inval_start, inval_end);
5312
5313 if (!(rd->status & E1000_RXD_STAT_DD))
5314 return 0;
5315
5316
5317 len = le16_to_cpu(rd->length);
5318 invalidate_dcache_range((unsigned long)packet,
5319 (unsigned long)packet +
5320 roundup(len, ARCH_DMA_MINALIGN));
5321 return len;
5322}
5323
5324static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5325{
5326 void *nv_packet = (void *)txpacket;
5327 struct e1000_tx_desc *txp;
5328 int i = 0;
5329 unsigned long flush_start, flush_end;
5330
5331 txp = tx_base + tx_tail;
5332 tx_tail = (tx_tail + 1) % 8;
5333
5334 txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet));
5335 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5336 txp->upper.data = 0;
5337
5338
5339 flush_dcache_range((unsigned long)nv_packet,
5340 (unsigned long)nv_packet +
5341 roundup(length, ARCH_DMA_MINALIGN));
5342
5343 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5344 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5345 flush_dcache_range(flush_start, flush_end);
5346
5347 E1000_WRITE_REG(hw, TDT, tx_tail);
5348
5349 E1000_WRITE_FLUSH(hw);
5350 while (1) {
5351 invalidate_dcache_range(flush_start, flush_end);
5352 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5353 break;
5354 if (i++ > TOUT_LOOP) {
5355 DEBUGOUT("e1000: tx timeout\n");
5356 return 0;
5357 }
5358 udelay(10);
5359 }
5360 return 1;
5361}
5362
5363static void
5364_e1000_disable(struct e1000_hw *hw)
5365{
5366
5367 E1000_WRITE_REG(hw, RCTL, 0);
5368 E1000_WRITE_REG(hw, TCTL, 0);
5369
5370
5371 E1000_WRITE_REG(hw, TDH, 0);
5372 E1000_WRITE_REG(hw, TDT, 0);
5373
5374
5375 E1000_WRITE_REG(hw, RDH, 0);
5376 E1000_WRITE_REG(hw, RDT, 0);
5377
5378 mdelay(10);
5379}
5380
5381
5382static inline int
5383e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5384{
5385 e1000_reset_hw(hw);
5386 if (hw->mac_type >= e1000_82544)
5387 E1000_WRITE_REG(hw, WUC, 0);
5388
5389 return e1000_init_hw(hw, enetaddr);
5390}
5391
5392static int
5393_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5394{
5395 int ret_val = 0;
5396
5397 ret_val = e1000_reset(hw, enetaddr);
5398 if (ret_val < 0) {
5399 if ((ret_val == -E1000_ERR_NOLINK) ||
5400 (ret_val == -E1000_ERR_TIMEOUT)) {
5401 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5402 } else {
5403 E1000_ERR(hw, "Hardware Initialization Failed\n");
5404 }
5405 return ret_val;
5406 }
5407 e1000_configure_tx(hw);
5408 e1000_setup_rctl(hw);
5409 e1000_configure_rx(hw);
5410 return 0;
5411}
5412
5413
5414
5415
5416
5417
5418void e1000_get_bus_type(struct e1000_hw *hw)
5419{
5420 uint32_t status;
5421
5422 switch (hw->mac_type) {
5423 case e1000_82542_rev2_0:
5424 case e1000_82542_rev2_1:
5425 hw->bus_type = e1000_bus_type_pci;
5426 break;
5427 case e1000_82571:
5428 case e1000_82572:
5429 case e1000_82573:
5430 case e1000_82574:
5431 case e1000_80003es2lan:
5432 case e1000_ich8lan:
5433 case e1000_igb:
5434 hw->bus_type = e1000_bus_type_pci_express;
5435 break;
5436 default:
5437 status = E1000_READ_REG(hw, STATUS);
5438 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5439 e1000_bus_type_pcix : e1000_bus_type_pci;
5440 break;
5441 }
5442}
5443
5444static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5445 struct udevice *devno, unsigned char enetaddr[6])
5446{
5447 u32 val;
5448
5449
5450 hw->pdev = devno;
5451 hw->cardnum = cardnum;
5452
5453
5454 dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5455 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5456
5457
5458 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5459 dm_pci_write_config32(devno, PCI_COMMAND, val);
5460
5461
5462 dm_pci_read_config32(devno, PCI_COMMAND, &val);
5463 if (!(val & PCI_COMMAND_MEMORY)) {
5464 E1000_ERR(hw, "Can't enable I/O memory\n");
5465 return -ENOSPC;
5466 }
5467 if (!(val & PCI_COMMAND_MASTER)) {
5468 E1000_ERR(hw, "Can't enable bus-mastering\n");
5469 return -EPERM;
5470 }
5471
5472
5473 hw->fc = e1000_fc_default;
5474 hw->original_fc = e1000_fc_default;
5475 hw->autoneg_failed = 0;
5476 hw->autoneg = 1;
5477 hw->get_link_status = true;
5478#ifndef CONFIG_E1000_NO_NVM
5479 hw->eeprom_semaphore_present = true;
5480#endif
5481 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0,
5482 PCI_REGION_TYPE, PCI_REGION_MEM);
5483 hw->mac_type = e1000_undefined;
5484
5485
5486 if (e1000_sw_init(hw) < 0) {
5487 E1000_ERR(hw, "Software init failed\n");
5488 return -EIO;
5489 }
5490 if (e1000_check_phy_reset_block(hw))
5491 E1000_ERR(hw, "PHY Reset is blocked!\n");
5492
5493
5494 e1000_reset_hw(hw);
5495
5496#ifndef CONFIG_E1000_NO_NVM
5497
5498 if (e1000_init_eeprom_params(hw)) {
5499 E1000_ERR(hw, "EEPROM is invalid!\n");
5500 return -EINVAL;
5501 }
5502 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5503 e1000_validate_eeprom_checksum(hw))
5504 return -ENXIO;
5505 e1000_read_mac_addr(hw, enetaddr);
5506#endif
5507 e1000_get_bus_type(hw);
5508
5509#ifndef CONFIG_E1000_NO_NVM
5510 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5511 enetaddr[0], enetaddr[1], enetaddr[2],
5512 enetaddr[3], enetaddr[4], enetaddr[5]);
5513#else
5514 memset(enetaddr, 0, 6);
5515 printf("e1000: no NVM\n");
5516#endif
5517
5518 return 0;
5519}
5520
5521
5522static void e1000_name(char *str, int cardnum)
5523{
5524 sprintf(str, "e1000#%u", cardnum);
5525}
5526
5527static int e1000_write_hwaddr(struct udevice *dev)
5528{
5529#ifndef CONFIG_E1000_NO_NVM
5530 unsigned char current_mac[6];
5531 struct eth_pdata *plat = dev_get_plat(dev);
5532 struct e1000_hw *hw = dev_get_priv(dev);
5533 u8 *mac = plat->enetaddr;
5534 uint16_t data[3];
5535 int ret_val, i;
5536
5537 DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5538
5539 if ((hw->eeprom.type == e1000_eeprom_invm) &&
5540 !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
5541 return -ENOSYS;
5542
5543 memset(current_mac, 0, 6);
5544
5545
5546
5547
5548 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5549 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5550
5551
5552
5553
5554 if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5555 return 0;
5556
5557 for (i = 0; i < 3; ++i)
5558 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5559
5560 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5561
5562 if (!ret_val)
5563 ret_val = e1000_update_eeprom_checksum_i210(hw);
5564
5565 return ret_val;
5566#else
5567 return 0;
5568#endif
5569}
5570
5571#ifdef CONFIG_CMD_E1000
5572static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5573 char *const argv[])
5574{
5575 unsigned char *mac = NULL;
5576 struct eth_pdata *plat;
5577 struct udevice *dev;
5578 char name[30];
5579 int ret;
5580#if defined(CONFIG_E1000_SPI)
5581 struct e1000_hw *hw;
5582#endif
5583 int cardnum;
5584
5585 if (argc < 3) {
5586 cmd_usage(cmdtp);
5587 return 1;
5588 }
5589
5590
5591 cardnum = dectoul(argv[1], NULL);
5592 e1000_name(name, cardnum);
5593 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5594 if (!ret) {
5595 plat = dev_get_plat(dev);
5596 mac = plat->enetaddr;
5597 }
5598 if (!mac) {
5599 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5600 return 1;
5601 }
5602
5603 if (!strcmp(argv[2], "print-mac-address")) {
5604 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5605 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5606 return 0;
5607 }
5608
5609#ifdef CONFIG_E1000_SPI
5610 hw = dev_get_priv(dev);
5611
5612 if (!strcmp(argv[2], "spi"))
5613 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5614#endif
5615
5616 cmd_usage(cmdtp);
5617 return 1;
5618}
5619
5620U_BOOT_CMD(
5621 e1000, 7, 0, do_e1000,
5622 "Intel e1000 controller management",
5623 "<card#> print-mac-address\n"
5624#ifdef CONFIG_E1000_SPI
5625 "e1000 <card#> spi show [<offset> [<length>]]\n"
5626 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5627 "e1000 <card#> spi program <addr> <offset> <length>\n"
5628 "e1000 <card#> spi checksum [update]\n"
5629#endif
5630 " - Manage the Intel E1000 PCI device"
5631);
5632#endif
5633
5634static int e1000_eth_start(struct udevice *dev)
5635{
5636 struct eth_pdata *plat = dev_get_plat(dev);
5637 struct e1000_hw *hw = dev_get_priv(dev);
5638
5639 return _e1000_init(hw, plat->enetaddr);
5640}
5641
5642static void e1000_eth_stop(struct udevice *dev)
5643{
5644 struct e1000_hw *hw = dev_get_priv(dev);
5645
5646 _e1000_disable(hw);
5647}
5648
5649static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5650{
5651 struct e1000_hw *hw = dev_get_priv(dev);
5652 int ret;
5653
5654 ret = _e1000_transmit(hw, packet, length);
5655
5656 return ret ? 0 : -ETIMEDOUT;
5657}
5658
5659static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5660{
5661 struct e1000_hw *hw = dev_get_priv(dev);
5662 int len;
5663
5664 len = _e1000_poll(hw);
5665 if (len)
5666 *packetp = packet;
5667
5668 return len ? len : -EAGAIN;
5669}
5670
5671static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5672{
5673 struct e1000_hw *hw = dev_get_priv(dev);
5674
5675 fill_rx(hw);
5676
5677 return 0;
5678}
5679
5680static int e1000_eth_probe(struct udevice *dev)
5681{
5682 struct eth_pdata *plat = dev_get_plat(dev);
5683 struct e1000_hw *hw = dev_get_priv(dev);
5684 int ret;
5685
5686 hw->name = dev->name;
5687 ret = e1000_init_one(hw, trailing_strtol(dev->name),
5688 dev, plat->enetaddr);
5689 if (ret < 0) {
5690 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5691 return ret;
5692 }
5693
5694 return 0;
5695}
5696
5697static int e1000_eth_bind(struct udevice *dev)
5698{
5699 char name[20];
5700
5701
5702
5703
5704
5705
5706
5707 e1000_name(name, num_cards++);
5708
5709 return device_set_name(dev, name);
5710}
5711
5712static const struct eth_ops e1000_eth_ops = {
5713 .start = e1000_eth_start,
5714 .send = e1000_eth_send,
5715 .recv = e1000_eth_recv,
5716 .stop = e1000_eth_stop,
5717 .free_pkt = e1000_free_pkt,
5718 .write_hwaddr = e1000_write_hwaddr,
5719};
5720
5721static const struct udevice_id e1000_eth_ids[] = {
5722 { .compatible = "intel,e1000" },
5723 { }
5724};
5725
5726U_BOOT_DRIVER(eth_e1000) = {
5727 .name = "eth_e1000",
5728 .id = UCLASS_ETH,
5729 .of_match = e1000_eth_ids,
5730 .bind = e1000_eth_bind,
5731 .probe = e1000_eth_probe,
5732 .ops = &e1000_eth_ops,
5733 .priv_auto = sizeof(struct e1000_hw),
5734 .plat_auto = sizeof(struct eth_pdata),
5735};
5736
5737U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5738