LXR uboot/drivers/net/fm/p5020.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2011 Freescale Semiconductor, Inc.
   4 */
   5#include <common.h>
   6#include <phy.h>
   7#include <fm_eth.h>
   8#include <asm/io.h>
   9#include <asm/immap_85xx.h>
  10#include <asm/fsl_serdes.h>
  11
  12static u32 port_to_devdisr[] = {
  13        [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  14        [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  15        [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  16        [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  17        [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  18        [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  19};
  20
  21static int is_device_disabled(enum fm_port port)
  22{
  23        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  24        u32 devdisr2 = in_be32(&gur->devdisr2);
  25
  26        return port_to_devdisr[port] & devdisr2;
  27}
  28
  29void fman_disable_port(enum fm_port port)
  30{
  31        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  32
  33        /* don't allow disabling of DTSEC1 as its needed for MDIO */
  34        if (port == FM1_DTSEC1)
  35                return;
  36
  37        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  38}
  39
  40void fman_enable_port(enum fm_port port)
  41{
  42        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  43
  44        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  45}
  46
  47phy_interface_t fman_port_enet_if(enum fm_port port)
  48{
  49        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  50        u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  51
  52        if (is_device_disabled(port))
  53                return PHY_INTERFACE_MODE_NA;
  54
  55        if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  56                return PHY_INTERFACE_MODE_XGMII;
  57
  58        /* handle RGMII first */
  59        if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  60                FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
  61                return PHY_INTERFACE_MODE_RGMII;
  62
  63        if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  64                FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
  65                return PHY_INTERFACE_MODE_MII;
  66
  67        if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  68                FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
  69                return PHY_INTERFACE_MODE_RGMII;
  70
  71        if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  72                FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
  73                return PHY_INTERFACE_MODE_MII;
  74
  75        switch (port) {
  76        case FM1_DTSEC1:
  77        case FM1_DTSEC2:
  78        case FM1_DTSEC3:
  79        case FM1_DTSEC4:
  80        case FM1_DTSEC5:
  81                if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  82                        return PHY_INTERFACE_MODE_SGMII;
  83                break;
  84        default:
  85                return PHY_INTERFACE_MODE_NA;
  86        }
  87
  88        return PHY_INTERFACE_MODE_NA;
  89}
  90