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14#include <common.h>
15#include <clk.h>
16#include <cpu_func.h>
17#include <dm.h>
18#include <log.h>
19#include <malloc.h>
20#include <miiphy.h>
21#include <net.h>
22#include <wait_bit.h>
23#include <asm/cache.h>
24#include <dm/device_compat.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28
29#include "ftgmac100.h"
30
31
32#define ETH_ZLEN 60
33
34
35#define FTGMAC100_RBSR_DEFAULT 0x640
36
37
38#define PKTBUFSTX 4
39
40
41#define FTGMAC100_TX_TIMEOUT_MS 1000
42
43
44#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
45
46
47
48
49
50
51#define MDC_CYCTHR 0x34
52
53
54
55
56enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
59};
60
61
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76
77
78struct ftgmac100_data {
79 struct ftgmac100 *iobase;
80
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
83 int tx_index;
84 int rx_index;
85
86 u32 phy_addr;
87 struct phy_device *phydev;
88 struct mii_dev *bus;
89 u32 phy_mode;
90 u32 max_speed;
91
92 struct clk_bulk clks;
93
94
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
97};
98
99
100
101
102static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
103 int reg_addr)
104{
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
107 int phycr;
108 int data;
109 int ret;
110
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
116
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
120 if (ret) {
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 bus->name, phy_addr, reg_addr);
123 return ret;
124 }
125
126 data = readl(&ftgmac100->phydata);
127
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
129}
130
131static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
133{
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
136 int phycr;
137 int data;
138 int ret;
139
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
145
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
148
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
152 if (ret) {
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 bus->name, phy_addr, reg_addr);
155 }
156
157 return ret;
158}
159
160static int ftgmac100_mdio_init(struct udevice *dev)
161{
162 struct ftgmac100_data *priv = dev_get_priv(dev);
163 struct mii_dev *bus;
164 int ret;
165
166 bus = mdio_alloc();
167 if (!bus)
168 return -ENOMEM;
169
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
172 bus->priv = priv;
173
174 ret = mdio_register_seq(bus, dev_seq(dev));
175 if (ret) {
176 free(bus);
177 return ret;
178 }
179
180 priv->bus = bus;
181
182 return 0;
183}
184
185static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
186{
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
189 u32 maccr;
190
191 if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
192 dev_err(phydev->dev, "No link\n");
193 return -EREMOTEIO;
194 }
195
196
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
201
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
204
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
207
208 if (phydev->duplex)
209 maccr |= FTGMAC100_MACCR_FULLDUP;
210
211
212 writel(maccr, &ftgmac100->maccr);
213
214 return 0;
215}
216
217static int ftgmac100_phy_init(struct udevice *dev)
218{
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
221 int ret;
222
223 if (IS_ENABLED(CONFIG_DM_MDIO))
224 phydev = dm_eth_phy_connect(dev);
225 else
226 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
227
228 if (!phydev)
229 return -ENODEV;
230
231 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
232 phydev->supported &= PHY_GBIT_FEATURES;
233 if (priv->max_speed) {
234 ret = phy_set_supported(phydev, priv->max_speed);
235 if (ret)
236 return ret;
237 }
238 phydev->advertising = phydev->supported;
239 priv->phydev = phydev;
240 phy_config(phydev);
241
242 return 0;
243}
244
245
246
247
248static void ftgmac100_reset(struct ftgmac100_data *priv)
249{
250 struct ftgmac100 *ftgmac100 = priv->iobase;
251
252 debug("%s()\n", __func__);
253
254 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
255
256 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
257 ;
258}
259
260
261
262
263static int ftgmac100_set_mac(struct ftgmac100_data *priv,
264 const unsigned char *mac)
265{
266 struct ftgmac100 *ftgmac100 = priv->iobase;
267 unsigned int maddr = mac[0] << 8 | mac[1];
268 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
269
270 debug("%s(%x %x)\n", __func__, maddr, laddr);
271
272 writel(maddr, &ftgmac100->mac_madr);
273 writel(laddr, &ftgmac100->mac_ladr);
274
275 return 0;
276}
277
278
279
280
281static int ftgmac100_get_mac(struct ftgmac100_data *priv,
282 unsigned char *mac)
283{
284 struct ftgmac100 *ftgmac100 = priv->iobase;
285 unsigned int maddr = readl(&ftgmac100->mac_madr);
286 unsigned int laddr = readl(&ftgmac100->mac_ladr);
287
288 debug("%s(%x %x)\n", __func__, maddr, laddr);
289
290 mac[0] = (maddr >> 8) & 0xff;
291 mac[1] = maddr & 0xff;
292 mac[2] = (laddr >> 24) & 0xff;
293 mac[3] = (laddr >> 16) & 0xff;
294 mac[4] = (laddr >> 8) & 0xff;
295 mac[5] = laddr & 0xff;
296
297 return 0;
298}
299
300
301
302
303static void ftgmac100_stop(struct udevice *dev)
304{
305 struct ftgmac100_data *priv = dev_get_priv(dev);
306 struct ftgmac100 *ftgmac100 = priv->iobase;
307
308 debug("%s()\n", __func__);
309
310 writel(0, &ftgmac100->maccr);
311
312 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
313 phy_shutdown(priv->phydev);
314}
315
316static int ftgmac100_start(struct udevice *dev)
317{
318 struct eth_pdata *plat = dev_get_plat(dev);
319 struct ftgmac100_data *priv = dev_get_priv(dev);
320 struct ftgmac100 *ftgmac100 = priv->iobase;
321 struct phy_device *phydev = priv->phydev;
322 unsigned int maccr;
323 ulong start, end;
324 int ret;
325 int i;
326
327 debug("%s()\n", __func__);
328
329 ftgmac100_reset(priv);
330
331
332 ftgmac100_set_mac(priv, plat->enetaddr);
333
334
335 writel(0, &ftgmac100->ier);
336
337
338 priv->tx_index = 0;
339 priv->rx_index = 0;
340
341 for (i = 0; i < PKTBUFSTX; i++) {
342 priv->txdes[i].txdes3 = 0;
343 priv->txdes[i].txdes0 = 0;
344 }
345 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
346
347 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
348 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
349 flush_dcache_range(start, end);
350
351 for (i = 0; i < PKTBUFSRX; i++) {
352 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
353 priv->rxdes[i].rxdes0 = 0;
354 }
355 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
356
357 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
358 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
359 flush_dcache_range(start, end);
360
361
362 writel((u32)priv->txdes, &ftgmac100->txr_badr);
363
364
365 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
366
367
368 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
369
370
371 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
372
373
374 maccr = FTGMAC100_MACCR_TXMAC_EN |
375 FTGMAC100_MACCR_RXMAC_EN |
376 FTGMAC100_MACCR_TXDMA_EN |
377 FTGMAC100_MACCR_RXDMA_EN |
378 FTGMAC100_MACCR_CRC_APD |
379 FTGMAC100_MACCR_FULLDUP |
380 FTGMAC100_MACCR_RX_RUNT |
381 FTGMAC100_MACCR_RX_BROADPKT;
382
383 writel(maccr, &ftgmac100->maccr);
384
385 ret = phy_startup(phydev);
386 if (ret) {
387 dev_err(phydev->dev, "Could not start PHY\n");
388 return ret;
389 }
390
391 ret = ftgmac100_phy_adjust_link(priv);
392 if (ret) {
393 dev_err(phydev->dev, "Could not adjust link\n");
394 return ret;
395 }
396
397 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
398 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
399
400 return 0;
401}
402
403static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
404{
405 struct ftgmac100_data *priv = dev_get_priv(dev);
406 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
407 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
408 ulong des_end = des_start +
409 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
410
411
412 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
413 flush_dcache_range(des_start, des_end);
414
415
416 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
417
418 return 0;
419}
420
421
422
423
424static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
425{
426 struct ftgmac100_data *priv = dev_get_priv(dev);
427 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
428 unsigned short rxlen;
429 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
430 ulong des_end = des_start +
431 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
432 ulong data_start = curr_des->rxdes3;
433 ulong data_end;
434
435 invalidate_dcache_range(des_start, des_end);
436
437 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
438 return -EAGAIN;
439
440 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
441 FTGMAC100_RXDES0_CRC_ERR |
442 FTGMAC100_RXDES0_FTL |
443 FTGMAC100_RXDES0_RUNT |
444 FTGMAC100_RXDES0_RX_ODD_NB)) {
445 return -EAGAIN;
446 }
447
448 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
449
450 debug("%s(): RX buffer %d, %x received\n",
451 __func__, priv->rx_index, rxlen);
452
453
454 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
455 invalidate_dcache_range(data_start, data_end);
456 *packetp = (uchar *)data_start;
457
458 return rxlen;
459}
460
461static u32 ftgmac100_read_txdesc(const void *desc)
462{
463 const struct ftgmac100_txdes *txdes = desc;
464 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
465 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
466
467 invalidate_dcache_range(des_start, des_end);
468
469 return txdes->txdes0;
470}
471
472BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
473
474
475
476
477static int ftgmac100_send(struct udevice *dev, void *packet, int length)
478{
479 struct ftgmac100_data *priv = dev_get_priv(dev);
480 struct ftgmac100 *ftgmac100 = priv->iobase;
481 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
482 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
483 ulong des_end = des_start +
484 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
485 ulong data_start;
486 ulong data_end;
487 int rc;
488
489 invalidate_dcache_range(des_start, des_end);
490
491 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
492 dev_err(dev, "no TX descriptor available\n");
493 return -EPERM;
494 }
495
496 debug("%s(%x, %x)\n", __func__, (int)packet, length);
497
498 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
499
500 curr_des->txdes3 = (unsigned int)packet;
501
502
503 data_start = curr_des->txdes3;
504 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
505 flush_dcache_range(data_start, data_end);
506
507
508 curr_des->txdes0 &= priv->txdes0_edotr_mask;
509 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
510 FTGMAC100_TXDES0_LTS |
511 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
512 FTGMAC100_TXDES0_TXDMA_OWN ;
513
514
515 flush_dcache_range(des_start, des_end);
516
517
518 writel(1, &ftgmac100->txpd);
519
520 rc = wait_for_bit_ftgmac100_txdone(curr_des,
521 FTGMAC100_TXDES0_TXDMA_OWN, false,
522 FTGMAC100_TX_TIMEOUT_MS, true);
523 if (rc)
524 return rc;
525
526 debug("%s(): packet sent\n", __func__);
527
528
529 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
530
531 return 0;
532}
533
534static int ftgmac100_write_hwaddr(struct udevice *dev)
535{
536 struct eth_pdata *pdata = dev_get_plat(dev);
537 struct ftgmac100_data *priv = dev_get_priv(dev);
538
539 return ftgmac100_set_mac(priv, pdata->enetaddr);
540}
541
542static int ftgmac_read_hwaddr(struct udevice *dev)
543{
544 struct eth_pdata *pdata = dev_get_plat(dev);
545 struct ftgmac100_data *priv = dev_get_priv(dev);
546
547 return ftgmac100_get_mac(priv, pdata->enetaddr);
548}
549
550static int ftgmac100_of_to_plat(struct udevice *dev)
551{
552 struct eth_pdata *pdata = dev_get_plat(dev);
553 struct ftgmac100_data *priv = dev_get_priv(dev);
554
555 pdata->iobase = dev_read_addr(dev);
556
557 pdata->phy_interface = dev_read_phy_mode(dev);
558 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
559 return -EINVAL;
560
561 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
562
563 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
564 priv->rxdes0_edorr_mask = BIT(30);
565 priv->txdes0_edotr_mask = BIT(30);
566 } else {
567 priv->rxdes0_edorr_mask = BIT(15);
568 priv->txdes0_edotr_mask = BIT(15);
569 }
570
571 return clk_get_bulk(dev, &priv->clks);
572}
573
574static int ftgmac100_probe(struct udevice *dev)
575{
576 struct eth_pdata *pdata = dev_get_plat(dev);
577 struct ftgmac100_data *priv = dev_get_priv(dev);
578 int ret;
579
580 priv->iobase = (struct ftgmac100 *)pdata->iobase;
581 priv->phy_mode = pdata->phy_interface;
582 priv->max_speed = pdata->max_speed;
583 priv->phy_addr = 0;
584
585 if (dev_read_bool(dev, "use-ncsi"))
586 priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
587
588#ifdef CONFIG_PHY_ADDR
589 priv->phy_addr = CONFIG_PHY_ADDR;
590#endif
591
592 ret = clk_enable_bulk(&priv->clks);
593 if (ret)
594 goto out;
595
596
597
598
599
600 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
601 !IS_ENABLED(CONFIG_DM_MDIO)) {
602 ret = ftgmac100_mdio_init(dev);
603 if (ret) {
604 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
605 goto out;
606 }
607 }
608
609 ret = ftgmac100_phy_init(dev);
610 if (ret) {
611 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
612 goto out;
613 }
614
615 ftgmac_read_hwaddr(dev);
616
617out:
618 if (ret)
619 clk_release_bulk(&priv->clks);
620
621 return ret;
622}
623
624static int ftgmac100_remove(struct udevice *dev)
625{
626 struct ftgmac100_data *priv = dev_get_priv(dev);
627
628 free(priv->phydev);
629 mdio_unregister(priv->bus);
630 mdio_free(priv->bus);
631 clk_release_bulk(&priv->clks);
632
633 return 0;
634}
635
636static const struct eth_ops ftgmac100_ops = {
637 .start = ftgmac100_start,
638 .send = ftgmac100_send,
639 .recv = ftgmac100_recv,
640 .stop = ftgmac100_stop,
641 .free_pkt = ftgmac100_free_pkt,
642 .write_hwaddr = ftgmac100_write_hwaddr,
643};
644
645static const struct udevice_id ftgmac100_ids[] = {
646 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
647 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
648 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
649 { }
650};
651
652U_BOOT_DRIVER(ftgmac100) = {
653 .name = "ftgmac100",
654 .id = UCLASS_ETH,
655 .of_match = ftgmac100_ids,
656 .of_to_plat = ftgmac100_of_to_plat,
657 .probe = ftgmac100_probe,
658 .remove = ftgmac100_remove,
659 .ops = &ftgmac100_ops,
660 .priv_auto = sizeof(struct ftgmac100_data),
661 .plat_auto = sizeof(struct eth_pdata),
662 .flags = DM_FLAG_ALLOC_PRIV_DMA,
663};
664
