uboot/drivers/net/sni_ave.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/**
   3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
   4 * Copyright 2016-2018 Socionext inc.
   5 */
   6
   7#include <clk.h>
   8#include <cpu_func.h>
   9#include <dm.h>
  10#include <fdt_support.h>
  11#include <log.h>
  12#include <malloc.h>
  13#include <miiphy.h>
  14#include <net.h>
  15#include <regmap.h>
  16#include <reset.h>
  17#include <syscon.h>
  18#include <asm/cache.h>
  19#include <asm/global_data.h>
  20#include <dm/device_compat.h>
  21#include <linux/bitops.h>
  22#include <linux/delay.h>
  23#include <linux/err.h>
  24#include <linux/io.h>
  25#include <linux/iopoll.h>
  26
  27#define AVE_GRST_DELAY_MSEC     40
  28#define AVE_MIN_XMITSIZE        60
  29#define AVE_SEND_TIMEOUT_COUNT  1000
  30#define AVE_MDIO_TIMEOUT_USEC   10000
  31#define AVE_HALT_TIMEOUT_USEC   10000
  32
  33/* General Register Group */
  34#define AVE_IDR                 0x000   /* ID */
  35#define AVE_VR                  0x004   /* Version */
  36#define AVE_GRR                 0x008   /* Global Reset */
  37#define AVE_CFGR                0x00c   /* Configuration */
  38
  39/* Interrupt Register Group */
  40#define AVE_GIMR                0x100   /* Global Interrupt Mask */
  41#define AVE_GISR                0x104   /* Global Interrupt Status */
  42
  43/* MAC Register Group */
  44#define AVE_TXCR                0x200   /* TX Setup */
  45#define AVE_RXCR                0x204   /* RX Setup */
  46#define AVE_RXMAC1R             0x208   /* MAC address (lower) */
  47#define AVE_RXMAC2R             0x20c   /* MAC address (upper) */
  48#define AVE_MDIOCTR             0x214   /* MDIO Control */
  49#define AVE_MDIOAR              0x218   /* MDIO Address */
  50#define AVE_MDIOWDR             0x21c   /* MDIO Data */
  51#define AVE_MDIOSR              0x220   /* MDIO Status */
  52#define AVE_MDIORDR             0x224   /* MDIO Rd Data */
  53
  54/* Descriptor Control Register Group */
  55#define AVE_DESCC               0x300   /* Descriptor Control */
  56#define AVE_TXDC                0x304   /* TX Descriptor Configuration */
  57#define AVE_RXDC                0x308   /* RX Descriptor Ring0 Configuration */
  58#define AVE_IIRQC               0x34c   /* Interval IRQ Control */
  59
  60/* 64bit descriptor memory */
  61#define AVE_DESC_SIZE_64        12      /* Descriptor Size */
  62#define AVE_TXDM_64             0x1000  /* Tx Descriptor Memory */
  63#define AVE_RXDM_64             0x1c00  /* Rx Descriptor Memory */
  64
  65/* 32bit descriptor memory */
  66#define AVE_DESC_SIZE_32        8       /* Descriptor Size */
  67#define AVE_TXDM_32             0x1000  /* Tx Descriptor Memory */
  68#define AVE_RXDM_32             0x1800  /* Rx Descriptor Memory */
  69
  70/* RMII Bridge Register Group */
  71#define AVE_RSTCTRL             0x8028  /* Reset control */
  72#define AVE_RSTCTRL_RMIIRST     BIT(16)
  73#define AVE_LINKSEL             0x8034  /* Link speed setting */
  74#define AVE_LINKSEL_100M        BIT(0)
  75
  76/* AVE_GRR */
  77#define AVE_GRR_PHYRST          BIT(4)  /* Reset external PHY */
  78#define AVE_GRR_GRST            BIT(0)  /* Reset all MAC */
  79
  80/* AVE_CFGR */
  81#define AVE_CFGR_MII            BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
  82
  83/* AVE_GISR (common with GIMR) */
  84#define AVE_GIMR_CLR            0
  85#define AVE_GISR_CLR            GENMASK(31, 0)
  86
  87/* AVE_TXCR */
  88#define AVE_TXCR_FLOCTR         BIT(18) /* Flow control */
  89#define AVE_TXCR_TXSPD_1G       BIT(17)
  90#define AVE_TXCR_TXSPD_100      BIT(16)
  91
  92/* AVE_RXCR */
  93#define AVE_RXCR_RXEN           BIT(30) /* Rx enable */
  94#define AVE_RXCR_FDUPEN         BIT(22) /* Interface mode */
  95#define AVE_RXCR_FLOCTR         BIT(21) /* Flow control */
  96
  97/* AVE_MDIOCTR */
  98#define AVE_MDIOCTR_RREQ        BIT(3)  /* Read request */
  99#define AVE_MDIOCTR_WREQ        BIT(2)  /* Write request */
 100
 101/* AVE_MDIOSR */
 102#define AVE_MDIOSR_STS          BIT(0)  /* access status */
 103
 104/* AVE_DESCC */
 105#define AVE_DESCC_RXDSTPSTS     BIT(20)
 106#define AVE_DESCC_RD0           BIT(8)  /* Enable Rx descriptor Ring0 */
 107#define AVE_DESCC_RXDSTP        BIT(4)  /* Pause Rx descriptor */
 108#define AVE_DESCC_TD            BIT(0)  /* Enable Tx descriptor */
 109
 110/* AVE_TXDC/RXDC */
 111#define AVE_DESC_SIZE(priv, num) \
 112        ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 :      \
 113                  AVE_DESC_SIZE_32))
 114
 115/* Command status for descriptor */
 116#define AVE_STS_OWN             BIT(31) /* Descriptor ownership */
 117#define AVE_STS_OK              BIT(27) /* Normal transmit */
 118#define AVE_STS_1ST             BIT(26) /* Head of buffer chain */
 119#define AVE_STS_LAST            BIT(25) /* Tail of buffer chain */
 120#define AVE_STS_PKTLEN_TX_MASK  GENMASK(15, 0)
 121#define AVE_STS_PKTLEN_RX_MASK  GENMASK(10, 0)
 122
 123#define AVE_DESC_OFS_CMDSTS     0
 124#define AVE_DESC_OFS_ADDRL      4
 125#define AVE_DESC_OFS_ADDRU      8
 126
 127/* Parameter for ethernet frame */
 128#define AVE_RXCR_MTU            1518
 129
 130/* SG */
 131#define SG_ETPINMODE            0x540
 132#define SG_ETPINMODE_EXTPHY     BIT(1)  /* for LD11 */
 133#define SG_ETPINMODE_RMII(ins)  BIT(ins)
 134
 135#define AVE_MAX_CLKS            4
 136#define AVE_MAX_RSTS            2
 137
 138enum desc_id {
 139        AVE_DESCID_TX,
 140        AVE_DESCID_RX,
 141};
 142
 143struct ave_private {
 144        phys_addr_t iobase;
 145        unsigned int nclks;
 146        struct clk clk[AVE_MAX_CLKS];
 147        unsigned int nrsts;
 148        struct reset_ctl rst[AVE_MAX_RSTS];
 149        struct regmap *regmap;
 150        unsigned int regmap_arg;
 151
 152        struct mii_dev *bus;
 153        struct phy_device *phydev;
 154        int phy_mode;
 155        int max_speed;
 156
 157        int rx_pos;
 158        int rx_siz;
 159        int rx_off;
 160        int tx_num;
 161
 162        u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
 163        void *tx_adj_buf;
 164
 165        const struct ave_soc_data *data;
 166};
 167
 168struct ave_soc_data {
 169        bool    is_desc_64bit;
 170        const char      *clock_names[AVE_MAX_CLKS];
 171        const char      *reset_names[AVE_MAX_RSTS];
 172        int     (*get_pinmode)(struct ave_private *priv);
 173};
 174
 175static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
 176                         int offset)
 177{
 178        int desc_size;
 179        u32 addr;
 180
 181        if (priv->data->is_desc_64bit) {
 182                desc_size = AVE_DESC_SIZE_64;
 183                addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
 184        } else {
 185                desc_size = AVE_DESC_SIZE_32;
 186                addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
 187        }
 188
 189        addr += entry * desc_size + offset;
 190
 191        return readl(priv->iobase + addr);
 192}
 193
 194static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
 195                                int entry)
 196{
 197        return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
 198}
 199
 200static void ave_desc_write(struct ave_private *priv, enum desc_id id,
 201                           int entry, int offset, u32 val)
 202{
 203        int desc_size;
 204        u32 addr;
 205
 206        if (priv->data->is_desc_64bit) {
 207                desc_size = AVE_DESC_SIZE_64;
 208                addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
 209        } else {
 210                desc_size = AVE_DESC_SIZE_32;
 211                addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
 212        }
 213
 214        addr += entry * desc_size + offset;
 215        writel(val, priv->iobase + addr);
 216}
 217
 218static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
 219                                  int entry, u32 val)
 220{
 221        ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
 222}
 223
 224static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
 225                                int entry, uintptr_t paddr)
 226{
 227        ave_desc_write(priv, id, entry,
 228                       AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
 229        if (priv->data->is_desc_64bit)
 230                ave_desc_write(priv, id, entry,
 231                               AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
 232}
 233
 234static void ave_cache_invalidate(uintptr_t vaddr, int len)
 235{
 236        invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
 237                                roundup(vaddr + len, ARCH_DMA_MINALIGN));
 238}
 239
 240static void ave_cache_flush(uintptr_t vaddr, int len)
 241{
 242        flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
 243                           roundup(vaddr + len, ARCH_DMA_MINALIGN));
 244}
 245
 246static int ave_mdiobus_read(struct mii_dev *bus,
 247                            int phyid, int devad, int regnum)
 248{
 249        struct ave_private *priv = bus->priv;
 250        u32 mdioctl, mdiosr;
 251        int ret;
 252
 253        /* write address */
 254        writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
 255
 256        /* read request */
 257        mdioctl = readl(priv->iobase + AVE_MDIOCTR);
 258        writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
 259
 260        ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
 261                                 !(mdiosr & AVE_MDIOSR_STS),
 262                                 AVE_MDIO_TIMEOUT_USEC);
 263        if (ret) {
 264                pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
 265                       priv->phydev->dev->name, phyid, regnum);
 266                return ret;
 267        }
 268
 269        return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
 270}
 271
 272static int ave_mdiobus_write(struct mii_dev *bus,
 273                             int phyid, int devad, int regnum, u16 val)
 274{
 275        struct ave_private *priv = bus->priv;
 276        u32 mdioctl, mdiosr;
 277        int ret;
 278
 279        /* write address */
 280        writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
 281
 282        /* write data */
 283        writel(val, priv->iobase + AVE_MDIOWDR);
 284
 285        /* write request */
 286        mdioctl = readl(priv->iobase + AVE_MDIOCTR);
 287        writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
 288               priv->iobase + AVE_MDIOCTR);
 289
 290        ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
 291                                 !(mdiosr & AVE_MDIOSR_STS),
 292                                 AVE_MDIO_TIMEOUT_USEC);
 293        if (ret)
 294                pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
 295                       priv->phydev->dev->name, phyid, regnum);
 296
 297        return ret;
 298}
 299
 300static int ave_adjust_link(struct ave_private *priv)
 301{
 302        struct phy_device *phydev = priv->phydev;
 303        struct eth_pdata *pdata = dev_get_plat(phydev->dev);
 304        u32 val, txcr, rxcr, rxcr_org;
 305        u16 rmt_adv = 0, lcl_adv = 0;
 306        u8 cap;
 307
 308        /* set RGMII speed */
 309        val = readl(priv->iobase + AVE_TXCR);
 310        val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
 311
 312        if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
 313                val |= AVE_TXCR_TXSPD_1G;
 314        else if (phydev->speed == SPEED_100)
 315                val |= AVE_TXCR_TXSPD_100;
 316
 317        writel(val, priv->iobase + AVE_TXCR);
 318
 319        /* set RMII speed (100M/10M only)  */
 320        if (!phy_interface_is_rgmii(phydev)) {
 321                val = readl(priv->iobase + AVE_LINKSEL);
 322                if (phydev->speed == SPEED_10)
 323                        val &= ~AVE_LINKSEL_100M;
 324                else
 325                        val |= AVE_LINKSEL_100M;
 326                writel(val, priv->iobase + AVE_LINKSEL);
 327        }
 328
 329        /* check current RXCR/TXCR */
 330        rxcr = readl(priv->iobase + AVE_RXCR);
 331        txcr = readl(priv->iobase + AVE_TXCR);
 332        rxcr_org = rxcr;
 333
 334        if (phydev->duplex) {
 335                rxcr |= AVE_RXCR_FDUPEN;
 336
 337                if (phydev->pause)
 338                        rmt_adv |= LPA_PAUSE_CAP;
 339                if (phydev->asym_pause)
 340                        rmt_adv |= LPA_PAUSE_ASYM;
 341                if (phydev->advertising & ADVERTISED_Pause)
 342                        lcl_adv |= ADVERTISE_PAUSE_CAP;
 343                if (phydev->advertising & ADVERTISED_Asym_Pause)
 344                        lcl_adv |= ADVERTISE_PAUSE_ASYM;
 345
 346                cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
 347                if (cap & FLOW_CTRL_TX)
 348                        txcr |= AVE_TXCR_FLOCTR;
 349                else
 350                        txcr &= ~AVE_TXCR_FLOCTR;
 351                if (cap & FLOW_CTRL_RX)
 352                        rxcr |= AVE_RXCR_FLOCTR;
 353                else
 354                        rxcr &= ~AVE_RXCR_FLOCTR;
 355        } else {
 356                rxcr &= ~AVE_RXCR_FDUPEN;
 357                rxcr &= ~AVE_RXCR_FLOCTR;
 358                txcr &= ~AVE_TXCR_FLOCTR;
 359        }
 360
 361        if (rxcr_org != rxcr) {
 362                /* disable Rx mac */
 363                writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
 364                /* change and enable TX/Rx mac */
 365                writel(txcr, priv->iobase + AVE_TXCR);
 366                writel(rxcr, priv->iobase + AVE_RXCR);
 367        }
 368
 369        pr_notice("%s: phy:%s speed:%d mac:%pM\n",
 370                  phydev->dev->name, phydev->drv->name, phydev->speed,
 371                  pdata->enetaddr);
 372
 373        return phydev->link;
 374}
 375
 376static int ave_mdiobus_init(struct ave_private *priv, const char *name)
 377{
 378        struct mii_dev *bus = mdio_alloc();
 379
 380        if (!bus)
 381                return -ENOMEM;
 382
 383        bus->read = ave_mdiobus_read;
 384        bus->write = ave_mdiobus_write;
 385        snprintf(bus->name, sizeof(bus->name), "%s", name);
 386        bus->priv = priv;
 387
 388        return mdio_register(bus);
 389}
 390
 391static int ave_phy_init(struct ave_private *priv, void *dev)
 392{
 393        struct phy_device *phydev;
 394        int mask = GENMASK(31, 0), ret;
 395
 396        phydev = phy_find_by_mask(priv->bus, mask);
 397        if (!phydev)
 398                return -ENODEV;
 399
 400        phy_connect_dev(phydev, dev, priv->phy_mode);
 401
 402        phydev->supported &= PHY_GBIT_FEATURES;
 403        if (priv->max_speed) {
 404                ret = phy_set_supported(phydev, priv->max_speed);
 405                if (ret)
 406                        return ret;
 407        }
 408        phydev->advertising = phydev->supported;
 409
 410        priv->phydev = phydev;
 411        phy_config(phydev);
 412
 413        return 0;
 414}
 415
 416static void ave_stop(struct udevice *dev)
 417{
 418        struct ave_private *priv = dev_get_priv(dev);
 419        u32 val;
 420        int ret;
 421
 422        val = readl(priv->iobase + AVE_GRR);
 423        if (val)
 424                return;
 425
 426        val = readl(priv->iobase + AVE_RXCR);
 427        val &= ~AVE_RXCR_RXEN;
 428        writel(val, priv->iobase + AVE_RXCR);
 429
 430        writel(0, priv->iobase + AVE_DESCC);
 431        ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
 432                                 AVE_HALT_TIMEOUT_USEC);
 433        if (ret)
 434                pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
 435
 436        writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
 437
 438        phy_shutdown(priv->phydev);
 439}
 440
 441static void ave_reset(struct ave_private *priv)
 442{
 443        u32 val;
 444
 445        /* reset RMII register */
 446        val = readl(priv->iobase + AVE_RSTCTRL);
 447        val &= ~AVE_RSTCTRL_RMIIRST;
 448        writel(val, priv->iobase + AVE_RSTCTRL);
 449
 450        /* assert reset */
 451        writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
 452        mdelay(AVE_GRST_DELAY_MSEC);
 453
 454        /* 1st, negate PHY reset only */
 455        writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
 456        mdelay(AVE_GRST_DELAY_MSEC);
 457
 458        /* negate reset */
 459        writel(0, priv->iobase + AVE_GRR);
 460        mdelay(AVE_GRST_DELAY_MSEC);
 461
 462        /* negate RMII register */
 463        val = readl(priv->iobase + AVE_RSTCTRL);
 464        val |= AVE_RSTCTRL_RMIIRST;
 465        writel(val, priv->iobase + AVE_RSTCTRL);
 466}
 467
 468static int ave_start(struct udevice *dev)
 469{
 470        struct ave_private *priv = dev_get_priv(dev);
 471        uintptr_t paddr;
 472        u32 val;
 473        int i;
 474
 475        ave_reset(priv);
 476
 477        priv->rx_pos = 0;
 478        priv->rx_off = 2; /* RX data has 2byte offsets */
 479        priv->tx_num = 0;
 480        priv->tx_adj_buf =
 481                (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
 482                                PKTALIGN);
 483        priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
 484
 485        val = 0;
 486        if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII &&
 487            priv->phy_mode != PHY_INTERFACE_MODE_RGMII_ID &&
 488            priv->phy_mode != PHY_INTERFACE_MODE_RGMII_RXID &&
 489            priv->phy_mode != PHY_INTERFACE_MODE_RGMII_TXID)
 490                val |= AVE_CFGR_MII;
 491        writel(val, priv->iobase + AVE_CFGR);
 492
 493        /* use one descriptor for Tx */
 494        writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
 495        ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
 496        ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
 497
 498        /* use PKTBUFSRX descriptors for Rx */
 499        writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
 500        for (i = 0; i < PKTBUFSRX; i++) {
 501                paddr = (uintptr_t)net_rx_packets[i];
 502                ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
 503                ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
 504                ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
 505        }
 506
 507        writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
 508        writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
 509
 510        writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
 511               priv->iobase + AVE_RXCR);
 512        writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
 513
 514        phy_startup(priv->phydev);
 515        ave_adjust_link(priv);
 516
 517        return 0;
 518}
 519
 520static int ave_write_hwaddr(struct udevice *dev)
 521{
 522        struct ave_private *priv = dev_get_priv(dev);
 523        struct eth_pdata *pdata = dev_get_plat(dev);
 524        u8 *mac = pdata->enetaddr;
 525
 526        writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
 527               priv->iobase + AVE_RXMAC1R);
 528        writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
 529
 530        return 0;
 531}
 532
 533static int ave_send(struct udevice *dev, void *packet, int length)
 534{
 535        struct ave_private *priv = dev_get_priv(dev);
 536        u32 val;
 537        void *ptr = packet;
 538        int count;
 539
 540        /* adjust alignment for descriptor */
 541        if ((uintptr_t)ptr & 0x3) {
 542                memcpy(priv->tx_adj_buf, (const void *)ptr, length);
 543                ptr = priv->tx_adj_buf;
 544        }
 545
 546        /* padding for minimum length */
 547        if (length < AVE_MIN_XMITSIZE) {
 548                memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
 549                length = AVE_MIN_XMITSIZE;
 550        }
 551
 552        /* check ownership and wait for previous xmit done */
 553        count = AVE_SEND_TIMEOUT_COUNT;
 554        do {
 555                val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
 556        } while ((val & AVE_STS_OWN) && --count);
 557        if (!count)
 558                return -ETIMEDOUT;
 559
 560        ave_cache_flush((uintptr_t)ptr, length);
 561        ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
 562
 563        val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
 564                (length & AVE_STS_PKTLEN_TX_MASK);
 565        ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
 566        priv->tx_num++;
 567
 568        count = AVE_SEND_TIMEOUT_COUNT;
 569        do {
 570                val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
 571        } while ((val & AVE_STS_OWN) && --count);
 572        if (!count)
 573                return -ETIMEDOUT;
 574
 575        if (!(val & AVE_STS_OK))
 576                pr_warn("%s: bad send packet status:%08x\n",
 577                        priv->phydev->dev->name, le32_to_cpu(val));
 578
 579        return 0;
 580}
 581
 582static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
 583{
 584        struct ave_private *priv = dev_get_priv(dev);
 585        uchar *ptr;
 586        int length = 0;
 587        u32 cmdsts;
 588
 589        while (1) {
 590                cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
 591                                              priv->rx_pos);
 592                if (!(cmdsts & AVE_STS_OWN))
 593                        /* hardware ownership, no received packets */
 594                        return -EAGAIN;
 595
 596                ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
 597                if (cmdsts & AVE_STS_OK)
 598                        break;
 599
 600                pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
 601                        priv->phydev->dev->name, priv->rx_pos,
 602                        le32_to_cpu(cmdsts), ptr);
 603        }
 604
 605        length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
 606
 607        /* invalidate after DMA is done */
 608        ave_cache_invalidate((uintptr_t)ptr, length);
 609        *packetp = ptr;
 610
 611        return length;
 612}
 613
 614static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
 615{
 616        struct ave_private *priv = dev_get_priv(dev);
 617
 618        ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
 619                        priv->rx_siz + priv->rx_off);
 620
 621        ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
 622                              priv->rx_pos, priv->rx_siz);
 623
 624        if (++priv->rx_pos >= PKTBUFSRX)
 625                priv->rx_pos = 0;
 626
 627        return 0;
 628}
 629
 630static int ave_pro4_get_pinmode(struct ave_private *priv)
 631{
 632        u32 reg, mask, val = 0;
 633
 634        if (priv->regmap_arg > 0)
 635                return -EINVAL;
 636
 637        mask = SG_ETPINMODE_RMII(0);
 638
 639        switch (priv->phy_mode) {
 640        case PHY_INTERFACE_MODE_RMII:
 641                val = SG_ETPINMODE_RMII(0);
 642                break;
 643        case PHY_INTERFACE_MODE_MII:
 644        case PHY_INTERFACE_MODE_RGMII:
 645        case PHY_INTERFACE_MODE_RGMII_ID:
 646        case PHY_INTERFACE_MODE_RGMII_RXID:
 647        case PHY_INTERFACE_MODE_RGMII_TXID:
 648                break;
 649        default:
 650                return -EINVAL;
 651        }
 652
 653        regmap_read(priv->regmap, SG_ETPINMODE, &reg);
 654        reg &= ~mask;
 655        reg |= val;
 656        regmap_write(priv->regmap, SG_ETPINMODE, reg);
 657
 658        return 0;
 659}
 660
 661static int ave_ld11_get_pinmode(struct ave_private *priv)
 662{
 663        u32 reg, mask, val = 0;
 664
 665        if (priv->regmap_arg > 0)
 666                return -EINVAL;
 667
 668        mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
 669
 670        switch (priv->phy_mode) {
 671        case PHY_INTERFACE_MODE_INTERNAL:
 672                break;
 673        case PHY_INTERFACE_MODE_RMII:
 674                val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
 675                break;
 676        default:
 677                return -EINVAL;
 678        }
 679
 680        regmap_read(priv->regmap, SG_ETPINMODE, &reg);
 681        reg &= ~mask;
 682        reg |= val;
 683        regmap_write(priv->regmap, SG_ETPINMODE, reg);
 684
 685        return 0;
 686}
 687
 688static int ave_ld20_get_pinmode(struct ave_private *priv)
 689{
 690        u32 reg, mask, val = 0;
 691
 692        if (priv->regmap_arg > 0)
 693                return -EINVAL;
 694
 695        mask = SG_ETPINMODE_RMII(0);
 696
 697        switch (priv->phy_mode) {
 698        case PHY_INTERFACE_MODE_RMII:
 699                val  = SG_ETPINMODE_RMII(0);
 700                break;
 701        case PHY_INTERFACE_MODE_RGMII:
 702        case PHY_INTERFACE_MODE_RGMII_ID:
 703        case PHY_INTERFACE_MODE_RGMII_RXID:
 704        case PHY_INTERFACE_MODE_RGMII_TXID:
 705                break;
 706        default:
 707                return -EINVAL;
 708        }
 709
 710        regmap_read(priv->regmap, SG_ETPINMODE, &reg);
 711        reg &= ~mask;
 712        reg |= val;
 713        regmap_write(priv->regmap, SG_ETPINMODE, reg);
 714
 715        return 0;
 716}
 717
 718static int ave_pxs3_get_pinmode(struct ave_private *priv)
 719{
 720        u32 reg, mask, val = 0;
 721
 722        if (priv->regmap_arg > 1)
 723                return -EINVAL;
 724
 725        mask = SG_ETPINMODE_RMII(priv->regmap_arg);
 726
 727        switch (priv->phy_mode) {
 728        case PHY_INTERFACE_MODE_RMII:
 729                val = SG_ETPINMODE_RMII(priv->regmap_arg);
 730                break;
 731        case PHY_INTERFACE_MODE_RGMII:
 732        case PHY_INTERFACE_MODE_RGMII_ID:
 733        case PHY_INTERFACE_MODE_RGMII_RXID:
 734        case PHY_INTERFACE_MODE_RGMII_TXID:
 735                break;
 736        default:
 737                return -EINVAL;
 738        }
 739
 740        regmap_read(priv->regmap, SG_ETPINMODE, &reg);
 741        reg &= ~mask;
 742        reg |= val;
 743        regmap_write(priv->regmap, SG_ETPINMODE, reg);
 744
 745        return 0;
 746}
 747
 748static int ave_of_to_plat(struct udevice *dev)
 749{
 750        struct eth_pdata *pdata = dev_get_plat(dev);
 751        struct ave_private *priv = dev_get_priv(dev);
 752        struct ofnode_phandle_args args;
 753        const u32 *valp;
 754        int ret, nc, nr;
 755        const char *name;
 756
 757        priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
 758        if (!priv->data)
 759                return -EINVAL;
 760
 761        pdata->iobase = dev_read_addr(dev);
 762
 763        pdata->phy_interface = dev_read_phy_mode(dev);
 764        if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 765                return -EINVAL;
 766
 767        pdata->max_speed = 0;
 768        valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
 769                           NULL);
 770        if (valp)
 771                pdata->max_speed = fdt32_to_cpu(*valp);
 772
 773        for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
 774                name = priv->data->clock_names[nc];
 775                if (!name)
 776                        break;
 777                ret = clk_get_by_name(dev, name, &priv->clk[nc]);
 778                if (ret) {
 779                        dev_err(dev, "Failed to get clocks property: %d\n",
 780                                ret);
 781                        goto out_clk_free;
 782                }
 783                priv->nclks++;
 784        }
 785
 786        for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
 787                name = priv->data->reset_names[nr];
 788                if (!name)
 789                        break;
 790                ret = reset_get_by_name(dev, name, &priv->rst[nr]);
 791                if (ret) {
 792                        dev_err(dev, "Failed to get resets property: %d\n",
 793                                ret);
 794                        goto out_reset_free;
 795                }
 796                priv->nrsts++;
 797        }
 798
 799        ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
 800                                         NULL, 1, 0, &args);
 801        if (ret) {
 802                dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
 803                        ret);
 804                goto out_reset_free;
 805        }
 806
 807        priv->regmap = syscon_node_to_regmap(args.node);
 808        if (IS_ERR(priv->regmap)) {
 809                ret = PTR_ERR(priv->regmap);
 810                dev_err(dev, "can't get syscon: %d\n", ret);
 811                goto out_reset_free;
 812        }
 813
 814        if (args.args_count != 1) {
 815                ret = -EINVAL;
 816                dev_err(dev, "Invalid argument of syscon-phy-mode\n");
 817                goto out_reset_free;
 818        }
 819
 820        priv->regmap_arg = args.args[0];
 821
 822        return 0;
 823
 824out_reset_free:
 825        while (--nr >= 0)
 826                reset_free(&priv->rst[nr]);
 827out_clk_free:
 828        while (--nc >= 0)
 829                clk_free(&priv->clk[nc]);
 830
 831        return ret;
 832}
 833
 834static int ave_probe(struct udevice *dev)
 835{
 836        struct eth_pdata *pdata = dev_get_plat(dev);
 837        struct ave_private *priv = dev_get_priv(dev);
 838        int ret, nc, nr;
 839
 840        priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
 841        if (!priv->data)
 842                return -EINVAL;
 843
 844        priv->iobase = pdata->iobase;
 845        priv->phy_mode = pdata->phy_interface;
 846        priv->max_speed = pdata->max_speed;
 847
 848        ret = priv->data->get_pinmode(priv);
 849        if (ret) {
 850                dev_err(dev, "Invalid phy-mode\n");
 851                return -EINVAL;
 852        }
 853
 854        for (nc = 0; nc < priv->nclks; nc++) {
 855                ret = clk_enable(&priv->clk[nc]);
 856                if (ret) {
 857                        dev_err(dev, "Failed to enable clk: %d\n", ret);
 858                        goto out_clk_release;
 859                }
 860        }
 861
 862        for (nr = 0; nr < priv->nrsts; nr++) {
 863                ret = reset_deassert(&priv->rst[nr]);
 864                if (ret) {
 865                        dev_err(dev, "Failed to deassert reset: %d\n", ret);
 866                        goto out_reset_release;
 867                }
 868        }
 869
 870        ave_reset(priv);
 871
 872        ret = ave_mdiobus_init(priv, dev->name);
 873        if (ret) {
 874                dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
 875                goto out_reset_release;
 876        }
 877
 878        priv->bus = miiphy_get_dev_by_name(dev->name);
 879
 880        ret = ave_phy_init(priv, dev);
 881        if (ret) {
 882                dev_err(dev, "Failed to initialize phy: %d\n", ret);
 883                goto out_mdiobus_release;
 884        }
 885
 886        return 0;
 887
 888out_mdiobus_release:
 889        mdio_unregister(priv->bus);
 890        mdio_free(priv->bus);
 891out_reset_release:
 892        reset_release_all(priv->rst, nr);
 893out_clk_release:
 894        clk_release_all(priv->clk, nc);
 895
 896        return ret;
 897}
 898
 899static int ave_remove(struct udevice *dev)
 900{
 901        struct ave_private *priv = dev_get_priv(dev);
 902
 903        free(priv->phydev);
 904        mdio_unregister(priv->bus);
 905        mdio_free(priv->bus);
 906        reset_release_all(priv->rst, priv->nrsts);
 907        clk_release_all(priv->clk, priv->nclks);
 908
 909        return 0;
 910}
 911
 912static const struct eth_ops ave_ops = {
 913        .start        = ave_start,
 914        .stop         = ave_stop,
 915        .send         = ave_send,
 916        .recv         = ave_recv,
 917        .free_pkt     = ave_free_packet,
 918        .write_hwaddr = ave_write_hwaddr,
 919};
 920
 921static const struct ave_soc_data ave_pro4_data = {
 922        .is_desc_64bit = false,
 923        .clock_names = {
 924                "gio", "ether", "ether-gb", "ether-phy",
 925        },
 926        .reset_names = {
 927                "gio", "ether",
 928        },
 929        .get_pinmode = ave_pro4_get_pinmode,
 930};
 931
 932static const struct ave_soc_data ave_pxs2_data = {
 933        .is_desc_64bit = false,
 934        .clock_names = {
 935                "ether",
 936        },
 937        .reset_names = {
 938                "ether",
 939        },
 940        .get_pinmode = ave_pro4_get_pinmode,
 941};
 942
 943static const struct ave_soc_data ave_ld11_data = {
 944        .is_desc_64bit = false,
 945        .clock_names = {
 946                "ether",
 947        },
 948        .reset_names = {
 949                "ether",
 950        },
 951        .get_pinmode = ave_ld11_get_pinmode,
 952};
 953
 954static const struct ave_soc_data ave_ld20_data = {
 955        .is_desc_64bit = true,
 956        .clock_names = {
 957                "ether",
 958        },
 959        .reset_names = {
 960                "ether",
 961        },
 962        .get_pinmode = ave_ld20_get_pinmode,
 963};
 964
 965static const struct ave_soc_data ave_pxs3_data = {
 966        .is_desc_64bit = false,
 967        .clock_names = {
 968                "ether",
 969        },
 970        .reset_names = {
 971                "ether",
 972        },
 973        .get_pinmode = ave_pxs3_get_pinmode,
 974};
 975
 976static const struct udevice_id ave_ids[] = {
 977        {
 978                .compatible = "socionext,uniphier-pro4-ave4",
 979                .data = (ulong)&ave_pro4_data,
 980        },
 981        {
 982                .compatible = "socionext,uniphier-pxs2-ave4",
 983                .data = (ulong)&ave_pxs2_data,
 984        },
 985        {
 986                .compatible = "socionext,uniphier-ld11-ave4",
 987                .data = (ulong)&ave_ld11_data,
 988        },
 989        {
 990                .compatible = "socionext,uniphier-ld20-ave4",
 991                .data = (ulong)&ave_ld20_data,
 992        },
 993        {
 994                .compatible = "socionext,uniphier-pxs3-ave4",
 995                .data = (ulong)&ave_pxs3_data,
 996        },
 997        { /* Sentinel */ }
 998};
 999
1000U_BOOT_DRIVER(ave) = {
1001        .name     = "ave",
1002        .id       = UCLASS_ETH,
1003        .of_match = ave_ids,
1004        .probe    = ave_probe,
1005        .remove   = ave_remove,
1006        .of_to_plat = ave_of_to_plat,
1007        .ops      = &ave_ops,
1008        .priv_auto      = sizeof(struct ave_private),
1009        .plat_auto      = sizeof(struct eth_pdata),
1010};
1011