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14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/bitops.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
23#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
24
25#define CPU_ALL_GP(fn, sfx) \
26 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
30 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
35 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
46
47#define CPU_ALL_NOGP(fn) \
48 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
61 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
62 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
63 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
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70
71#define GPSR0_17 F_(SDA4, IP7_27_24)
72#define GPSR0_16 F_(SCL4, IP7_23_20)
73#define GPSR0_15 F_(D15, IP7_19_16)
74#define GPSR0_14 F_(D14, IP7_15_12)
75#define GPSR0_13 F_(D13, IP7_11_8)
76#define GPSR0_12 F_(D12, IP7_7_4)
77#define GPSR0_11 F_(D11, IP7_3_0)
78#define GPSR0_10 F_(D10, IP6_31_28)
79#define GPSR0_9 F_(D9, IP6_27_24)
80#define GPSR0_8 F_(D8, IP6_23_20)
81#define GPSR0_7 F_(D7, IP6_19_16)
82#define GPSR0_6 F_(D6, IP6_15_12)
83#define GPSR0_5 F_(D5, IP6_11_8)
84#define GPSR0_4 F_(D4, IP6_7_4)
85#define GPSR0_3 F_(D3, IP6_3_0)
86#define GPSR0_2 F_(D2, IP5_31_28)
87#define GPSR0_1 F_(D1, IP5_27_24)
88#define GPSR0_0 F_(D0, IP5_23_20)
89
90
91#define GPSR1_22 F_(WE0_N, IP5_19_16)
92#define GPSR1_21 F_(CS0_N, IP5_15_12)
93#define GPSR1_20 FM(CLKOUT)
94#define GPSR1_19 F_(A19, IP5_11_8)
95#define GPSR1_18 F_(A18, IP5_7_4)
96#define GPSR1_17 F_(A17, IP5_3_0)
97#define GPSR1_16 F_(A16, IP4_31_28)
98#define GPSR1_15 F_(A15, IP4_27_24)
99#define GPSR1_14 F_(A14, IP4_23_20)
100#define GPSR1_13 F_(A13, IP4_19_16)
101#define GPSR1_12 F_(A12, IP4_15_12)
102#define GPSR1_11 F_(A11, IP4_11_8)
103#define GPSR1_10 F_(A10, IP4_7_4)
104#define GPSR1_9 F_(A9, IP4_3_0)
105#define GPSR1_8 F_(A8, IP3_31_28)
106#define GPSR1_7 F_(A7, IP3_27_24)
107#define GPSR1_6 F_(A6, IP3_23_20)
108#define GPSR1_5 F_(A5, IP3_19_16)
109#define GPSR1_4 F_(A4, IP3_15_12)
110#define GPSR1_3 F_(A3, IP3_11_8)
111#define GPSR1_2 F_(A2, IP3_7_4)
112#define GPSR1_1 F_(A1, IP3_3_0)
113#define GPSR1_0 F_(A0, IP2_31_28)
114
115
116#define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
117#define GPSR2_24 F_(RD_WR_N, IP2_23_20)
118#define GPSR2_23 F_(RD_N, IP2_19_16)
119#define GPSR2_22 F_(BS_N, IP2_15_12)
120#define GPSR2_21 FM(AVB_PHY_INT)
121#define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
122#define GPSR2_19 FM(AVB_RD3)
123#define GPSR2_18 F_(AVB_RD2, IP1_31_28)
124#define GPSR2_17 F_(AVB_RD1, IP1_27_24)
125#define GPSR2_16 F_(AVB_RD0, IP1_23_20)
126#define GPSR2_15 FM(AVB_RXC)
127#define GPSR2_14 FM(AVB_RX_CTL)
128#define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
129#define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
130#define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
131#define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
132#define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
133#define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
134#define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
135#define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
136#define GPSR2_5 FM(QSPI0_SSL)
137#define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
138#define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
139#define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
140#define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
141#define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
142
143
144#define GPSR3_15 F_(SD1_WP, IP11_7_4)
145#define GPSR3_14 F_(SD1_CD, IP11_3_0)
146#define GPSR3_13 F_(SD0_WP, IP10_31_28)
147#define GPSR3_12 F_(SD0_CD, IP10_27_24)
148#define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
149#define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
150#define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
151#define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
152#define GPSR3_7 F_(SD1_CMD, IP8_27_24)
153#define GPSR3_6 F_(SD1_CLK, IP8_23_20)
154#define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
155#define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
156#define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
157#define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
158#define GPSR3_1 F_(SD0_CMD, IP8_3_0)
159#define GPSR3_0 F_(SD0_CLK, IP7_31_28)
160
161
162#define GPSR4_10 F_(SD3_DS, IP10_23_20)
163#define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
164#define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
165#define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
166#define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
167#define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
168#define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
169#define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
170#define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
171#define GPSR4_1 F_(SD3_CMD, IP9_19_16)
172#define GPSR4_0 F_(SD3_CLK, IP9_15_12)
173
174
175#define GPSR5_19 F_(MLB_DAT, IP13_23_20)
176#define GPSR5_18 F_(MLB_SIG, IP13_19_16)
177#define GPSR5_17 F_(MLB_CLK, IP13_15_12)
178#define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
179#define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
180#define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
181#define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
182#define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
183#define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
184#define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
185#define GPSR5_9 F_(RX2_A, IP12_15_12)
186#define GPSR5_8 F_(TX2_A, IP12_11_8)
187#define GPSR5_7 F_(SCK2_A, IP12_7_4)
188#define GPSR5_6 F_(TX1, IP12_3_0)
189#define GPSR5_5 F_(RX1, IP11_31_28)
190#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
191#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
192#define GPSR5_2 F_(TX0_A, IP11_15_12)
193#define GPSR5_1 F_(RX0_A, IP11_11_8)
194#define GPSR5_0 F_(SCK0_A, IP11_27_24)
195
196
197#define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
198#define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
199#define GPSR6_15 F_(SSI_WS6, IP15_15_12)
200#define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
201#define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
202#define GPSR6_12 F_(SSI_WS5, IP15_3_0)
203#define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
204#define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
205#define GPSR6_9 F_(USB30_OVC, IP15_31_28)
206#define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
207#define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
208#define GPSR6_6 F_(SSI_WS349, IP14_19_16)
209#define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
210#define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
211#define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
212#define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
213#define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
214#define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
215
216
217#define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249
250
251#define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
284
285#define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318
319#define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351
352#define PINMUX_GPSR \
353\
354 \
355 \
356 \
357 \
358 \
359 \
360 GPSR2_25 \
361 GPSR2_24 \
362 GPSR2_23 \
363 GPSR1_22 GPSR2_22 \
364 GPSR1_21 GPSR2_21 \
365 GPSR1_20 GPSR2_20 \
366 GPSR1_19 GPSR2_19 GPSR5_19 \
367 GPSR1_18 GPSR2_18 GPSR5_18 \
368GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
369GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
370GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
371GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
372GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
373GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
374GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
375GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
376GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
377GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
378GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
379GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
380GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
381GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
382GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
383GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
384GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
385GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
386
387#define PINMUX_IPSR \
388\
389FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
390FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
391FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
392FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
393FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
394FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
395FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
396FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
397\
398FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
399FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
400FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
401FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
402FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
403FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
404FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
405FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
406\
407FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
408FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
409FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
410FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
411FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
412FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
413FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
414FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
415\
416FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
417FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
418FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
419FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
420FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
421FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
422FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
423FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
424
425
426#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
427#define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
428
429
430#define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
431#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
432#define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
433#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
434#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
435#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
436#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
437#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
438#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
439#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
440#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
441#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
442#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
443#define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
444#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
445#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
446#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
447#define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
448#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
449#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
450#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
451#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
452
453
454#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
455#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
456#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
457#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
458#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
459#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
460#define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
461#define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
462#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
463#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
464#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
465#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
466#define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
467#define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
468#define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
469#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
470#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
471#define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
472#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
473
474#define PINMUX_MOD_SELS \
475\
476 MOD_SEL1_31 \
477MOD_SEL0_30_29 MOD_SEL1_30 \
478 MOD_SEL1_29 \
479MOD_SEL0_28 MOD_SEL1_28 \
480MOD_SEL0_27_26 \
481 MOD_SEL1_26 \
482MOD_SEL0_25 MOD_SEL1_25 \
483MOD_SEL0_24 MOD_SEL1_24_23_22 \
484MOD_SEL0_23 \
485MOD_SEL0_22 \
486MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
487MOD_SEL0_19_18_17 MOD_SEL1_18 \
488 MOD_SEL1_17 \
489MOD_SEL0_16 MOD_SEL1_16 \
490MOD_SEL0_15 MOD_SEL1_15 \
491MOD_SEL0_14 MOD_SEL1_14_13 \
492MOD_SEL0_13_12 \
493 MOD_SEL1_12_11 \
494MOD_SEL0_11_10 \
495 MOD_SEL1_10_9 \
496MOD_SEL0_9 \
497MOD_SEL0_8 MOD_SEL1_8 \
498MOD_SEL0_7 MOD_SEL1_7 \
499MOD_SEL0_6_5 MOD_SEL1_6_5 \
500MOD_SEL0_4 MOD_SEL1_4 \
501MOD_SEL0_3 \
502MOD_SEL0_2 \
503MOD_SEL0_1_0
504
505
506
507
508
509#define PINMUX_STATIC \
510 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
511 FM(AVB_TD3) \
512 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
513 FM(ASEBRK) \
514 FM(MLB_REF)
515
516enum {
517 PINMUX_RESERVED = 0,
518
519 PINMUX_DATA_BEGIN,
520 GP_ALL(DATA),
521 PINMUX_DATA_END,
522
523#define F_(x, y)
524#define FM(x) FN_##x,
525 PINMUX_FUNCTION_BEGIN,
526 GP_ALL(FN),
527 PINMUX_GPSR
528 PINMUX_IPSR
529 PINMUX_MOD_SELS
530 PINMUX_FUNCTION_END,
531#undef F_
532#undef FM
533
534#define F_(x, y)
535#define FM(x) x##_MARK,
536 PINMUX_MARK_BEGIN,
537 PINMUX_GPSR
538 PINMUX_IPSR
539 PINMUX_MOD_SELS
540 PINMUX_STATIC
541 PINMUX_MARK_END,
542#undef F_
543#undef FM
544};
545
546static const u16 pinmux_data[] = {
547 PINMUX_DATA_GP_ALL(),
548
549 PINMUX_SINGLE(CLKOUT),
550 PINMUX_SINGLE(AVB_PHY_INT),
551 PINMUX_SINGLE(AVB_RD3),
552 PINMUX_SINGLE(AVB_RXC),
553 PINMUX_SINGLE(AVB_RX_CTL),
554 PINMUX_SINGLE(QSPI0_SSL),
555
556
557 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
558 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
559
560 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
561 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
562
563 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
564 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
565
566 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
567 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
568
569 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
570 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
571
572 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
573 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
574 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
575 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
576
577 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
578 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
579 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
580 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
581
582 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
583 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
584 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
585 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
586
587
588 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
589 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
590 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
591 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
592
593 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
594 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
595 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
596 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
597
598 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
599 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
600 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
601 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
602
603 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
604 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
605 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
606 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
607
608 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
609 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
610 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
611 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
612
613 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
614
615 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
616
617 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
618
619
620 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
621
622 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
623
624 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
625
626 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
627 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
628 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
629 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
630 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
631 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
632
633 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
634 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
635 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
636 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
637 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
638 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
639 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
640
641 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
642 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
643 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
644 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
645 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
646 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
647 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
648
649 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
650 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
651 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
652 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
653 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
654 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
655
656 PINMUX_IPSR_GPSR(IP2_31_28, A0),
657 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
658 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
659 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
660 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
661 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
662 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
663 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
664 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
665
666
667 PINMUX_IPSR_GPSR(IP3_3_0, A1),
668 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
669 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
670 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
671 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
672 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
673 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
674 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
675 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
676
677 PINMUX_IPSR_GPSR(IP3_7_4, A2),
678 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
679 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
681 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
682 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
683 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
684 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
685
686 PINMUX_IPSR_GPSR(IP3_11_8, A3),
687 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
688 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
689 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
690 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
691 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
692 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
693 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
694
695 PINMUX_IPSR_GPSR(IP3_15_12, A4),
696 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
697 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
699 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
700 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
701 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
702
703 PINMUX_IPSR_GPSR(IP3_19_16, A5),
704 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
705 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
707 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
708 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
709 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
710
711 PINMUX_IPSR_GPSR(IP3_23_20, A6),
712 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
713 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
714 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
715 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
716
717 PINMUX_IPSR_GPSR(IP3_27_24, A7),
718 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
719 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
720 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
721 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
722
723 PINMUX_IPSR_GPSR(IP3_31_28, A8),
724 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
725 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
726 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
727 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
728 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
729 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
730 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
731
732
733 PINMUX_IPSR_GPSR(IP4_3_0, A9),
734 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
735 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
736 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
737 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
738 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
739 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
740
741 PINMUX_IPSR_GPSR(IP4_7_4, A10),
742 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
743 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
744 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
745 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
746 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
747 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
748 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
749
750 PINMUX_IPSR_GPSR(IP4_11_8, A11),
751 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
752 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
753 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
754 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
755 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
756 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
757
758 PINMUX_IPSR_GPSR(IP4_15_12, A12),
759 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
760 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
761 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
762 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
763 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
764 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
765
766 PINMUX_IPSR_GPSR(IP4_19_16, A13),
767 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
768 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
769 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
770 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
771 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
772 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
773
774 PINMUX_IPSR_GPSR(IP4_23_20, A14),
775 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
776 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
777 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
778 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
779 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
780 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
781
782 PINMUX_IPSR_GPSR(IP4_27_24, A15),
783 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
784 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
785 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
786 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
787 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
788 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
789
790 PINMUX_IPSR_GPSR(IP4_31_28, A16),
791 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
792 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
793 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
794 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
795 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
796 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
797
798
799 PINMUX_IPSR_GPSR(IP5_3_0, A17),
800 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
801 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
802 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
803 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
804 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
805
806 PINMUX_IPSR_GPSR(IP5_7_4, A18),
807 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
808 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
809 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
810 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
811 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
812 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
813
814 PINMUX_IPSR_GPSR(IP5_11_8, A19),
815 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
816 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
817 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
818 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
819 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
820 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
821
822 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
823 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
824 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
825 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
826 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
827
828 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
829 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
830 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
831 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
832 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
833
834 PINMUX_IPSR_GPSR(IP5_23_20, D0),
835 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
836 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
837 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
838 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
839
840 PINMUX_IPSR_GPSR(IP5_27_24, D1),
841 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
842 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
843 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
844 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
845 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
846 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
847 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
848
849 PINMUX_IPSR_GPSR(IP5_31_28, D2),
850 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
851 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
852 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
853 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
854 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
855 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
856
857
858 PINMUX_IPSR_GPSR(IP6_3_0, D3),
859 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
860 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
861 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
862 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
863 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
864 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
865
866 PINMUX_IPSR_GPSR(IP6_7_4, D4),
867 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
868 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
869 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
870 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
871 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
872 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
873
874 PINMUX_IPSR_GPSR(IP6_11_8, D5),
875 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
876 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
877 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
878 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
879 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
880
881 PINMUX_IPSR_GPSR(IP6_15_12, D6),
882 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
883 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
884 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
885 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
886 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
887
888 PINMUX_IPSR_GPSR(IP6_19_16, D7),
889 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
890 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
891 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
892 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
894
895 PINMUX_IPSR_GPSR(IP6_23_20, D8),
896 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
897 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
898 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
899 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
900 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
901 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
902 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
903
904 PINMUX_IPSR_GPSR(IP6_27_24, D9),
905 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
906 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
907 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
908 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
909 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
910 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
911
912 PINMUX_IPSR_GPSR(IP6_31_28, D10),
913 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
914 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
915 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
916 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
917 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
918 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
919
920
921 PINMUX_IPSR_GPSR(IP7_3_0, D11),
922 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
923 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
924 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
925 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
926 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
927 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
928
929 PINMUX_IPSR_GPSR(IP7_7_4, D12),
930 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
931 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
932 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
933 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
934 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
935
936 PINMUX_IPSR_GPSR(IP7_11_8, D13),
937 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
938 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
939 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
940 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
941 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
942 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
943
944 PINMUX_IPSR_GPSR(IP7_15_12, D14),
945 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
946 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
947 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
948 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
949 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
950
951 PINMUX_IPSR_GPSR(IP7_19_16, D15),
952 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
953 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
954 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
955 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
956 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
957
958 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
959 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
960 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
961 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
962 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
963 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
964
965 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
966 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
967 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
968 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
969 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
970
971 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
972 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
973 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
974 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
975 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
976 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
977
978
979 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
980 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
981 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
982 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
983
984 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
985 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
986 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
987 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
988
989 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
990 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
991 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
992 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
993 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
994
995 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
996 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
997 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
998 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
999 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
1000
1001 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
1002 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
1003 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
1004 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
1005 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
1006 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
1007
1008 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
1009 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
1012 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1013
1014 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
1015 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
1016
1017
1018 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
1019 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
1020
1021 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1022 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
1023
1024 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1025 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
1026
1027 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1028 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
1029
1030 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
1031 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1032
1033 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1034 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1035
1036 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1037 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1038
1039 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1040 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1041
1042
1043 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1044 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1045
1046 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1047 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1048
1049 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1050 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1051
1052 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1053 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1054
1055 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1056 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1057
1058 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1059 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1060
1061 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1062 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
1063 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1064 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1065 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1066 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1067 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1068 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1069
1070 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1071 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
1072 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1073 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1074 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1075 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1076 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1077 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1078
1079
1080 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1081 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
1082 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1083 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1084 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1085
1086 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1087 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
1088 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1089 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1090 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1091
1092 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1093 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1094 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1095 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1096 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1097
1098 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1099 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1100 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1101 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1102 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1103
1104 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1105 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
1106 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1107 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1108 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1109 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1110
1111 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
1112 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
1113 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1114 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1115 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1116 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1117
1118 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1119 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1120 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1121 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1122 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1123 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1124 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1125
1126 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1127 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1128 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1129 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1130
1131
1132 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1133 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1134 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1135 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1136
1137 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1138 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1139 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1140 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1141 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1142 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1143 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1144
1145 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1146 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1147 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1148 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1149 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1150 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1151
1152 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1153 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1154 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1155 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1156 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1157 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1158
1159 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1160 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1161
1162 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1163 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1164 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1165
1166 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1167 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1168 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1169
1170 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1171 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1172 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1173
1174
1175 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1176 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1177 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1178 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1179 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1180 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1181
1182 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1183 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1184 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1185 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1186 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1187 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1188
1189 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1190 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1191 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1192
1193 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1194 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1195 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1196 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1197 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1198 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1199
1200 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1201 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1202 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1203 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1204 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1205 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1206
1207 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1208 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1209 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1210 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1211
1212 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1213
1214 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1215
1216
1217 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1218
1219 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1220 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1221 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1222
1223 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1224 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1225 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1226 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1227
1228 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1229 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1230
1231 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1232 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1233
1234 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1235 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1236 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1237 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1238
1239 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1240 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1241 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1242
1243 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1244 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1245 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1246 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1247 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1248
1249
1250 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1251 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1252 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1253 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1254
1255 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1256 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1257 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1258 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1259
1260 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1261 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1262 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1263 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1264 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1265 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1266
1267 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1268 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1269 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1270 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1271 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1272 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1273 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1274
1275 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1276 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1277 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1278 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1279 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1280 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1281 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1282
1283 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1284
1285 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1286 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1287
1288 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1289 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1290
1291
1292
1293
1294
1295
1296
1297
1298#define FM(x) PINMUX_DATA(x##_MARK, 0),
1299 PINMUX_STATIC
1300#undef FM
1301};
1302
1303
1304
1305
1306enum {
1307 GP_ASSIGN_LAST(),
1308 NOGP_ALL(),
1309};
1310
1311static const struct sh_pfc_pin pinmux_pins[] = {
1312 PINMUX_GPIO_GP_ALL(),
1313 PINMUX_NOGP_ALL(),
1314};
1315
1316
1317static const unsigned int audio_clk_a_pins[] = {
1318
1319 RCAR_GP_PIN(6, 8),
1320};
1321
1322static const unsigned int audio_clk_a_mux[] = {
1323 AUDIO_CLKA_MARK,
1324};
1325
1326static const unsigned int audio_clk_b_a_pins[] = {
1327
1328 RCAR_GP_PIN(5, 7),
1329};
1330
1331static const unsigned int audio_clk_b_a_mux[] = {
1332 AUDIO_CLKB_A_MARK,
1333};
1334
1335static const unsigned int audio_clk_b_b_pins[] = {
1336
1337 RCAR_GP_PIN(6, 7),
1338};
1339
1340static const unsigned int audio_clk_b_b_mux[] = {
1341 AUDIO_CLKB_B_MARK,
1342};
1343
1344static const unsigned int audio_clk_b_c_pins[] = {
1345
1346 RCAR_GP_PIN(6, 13),
1347};
1348
1349static const unsigned int audio_clk_b_c_mux[] = {
1350 AUDIO_CLKB_C_MARK,
1351};
1352
1353static const unsigned int audio_clk_c_a_pins[] = {
1354
1355 RCAR_GP_PIN(5, 16),
1356};
1357
1358static const unsigned int audio_clk_c_a_mux[] = {
1359 AUDIO_CLKC_A_MARK,
1360};
1361
1362static const unsigned int audio_clk_c_b_pins[] = {
1363
1364 RCAR_GP_PIN(6, 3),
1365};
1366
1367static const unsigned int audio_clk_c_b_mux[] = {
1368 AUDIO_CLKC_B_MARK,
1369};
1370
1371static const unsigned int audio_clk_c_c_pins[] = {
1372
1373 RCAR_GP_PIN(6, 14),
1374};
1375
1376static const unsigned int audio_clk_c_c_mux[] = {
1377 AUDIO_CLKC_C_MARK,
1378};
1379
1380static const unsigned int audio_clkout_a_pins[] = {
1381
1382 RCAR_GP_PIN(5, 3),
1383};
1384
1385static const unsigned int audio_clkout_a_mux[] = {
1386 AUDIO_CLKOUT_A_MARK,
1387};
1388
1389static const unsigned int audio_clkout_b_pins[] = {
1390
1391 RCAR_GP_PIN(5, 13),
1392};
1393
1394static const unsigned int audio_clkout_b_mux[] = {
1395 AUDIO_CLKOUT_B_MARK,
1396};
1397
1398static const unsigned int audio_clkout1_a_pins[] = {
1399
1400 RCAR_GP_PIN(5, 4),
1401};
1402
1403static const unsigned int audio_clkout1_a_mux[] = {
1404 AUDIO_CLKOUT1_A_MARK,
1405};
1406
1407static const unsigned int audio_clkout1_b_pins[] = {
1408
1409 RCAR_GP_PIN(5, 5),
1410};
1411
1412static const unsigned int audio_clkout1_b_mux[] = {
1413 AUDIO_CLKOUT1_B_MARK,
1414};
1415
1416static const unsigned int audio_clkout1_c_pins[] = {
1417
1418 RCAR_GP_PIN(6, 7),
1419};
1420
1421static const unsigned int audio_clkout1_c_mux[] = {
1422 AUDIO_CLKOUT1_C_MARK,
1423};
1424
1425static const unsigned int audio_clkout2_a_pins[] = {
1426
1427 RCAR_GP_PIN(5, 8),
1428};
1429
1430static const unsigned int audio_clkout2_a_mux[] = {
1431 AUDIO_CLKOUT2_A_MARK,
1432};
1433
1434static const unsigned int audio_clkout2_b_pins[] = {
1435
1436 RCAR_GP_PIN(6, 4),
1437};
1438
1439static const unsigned int audio_clkout2_b_mux[] = {
1440 AUDIO_CLKOUT2_B_MARK,
1441};
1442
1443static const unsigned int audio_clkout2_c_pins[] = {
1444
1445 RCAR_GP_PIN(6, 15),
1446};
1447
1448static const unsigned int audio_clkout2_c_mux[] = {
1449 AUDIO_CLKOUT2_C_MARK,
1450};
1451
1452static const unsigned int audio_clkout3_a_pins[] = {
1453
1454 RCAR_GP_PIN(5, 9),
1455};
1456
1457static const unsigned int audio_clkout3_a_mux[] = {
1458 AUDIO_CLKOUT3_A_MARK,
1459};
1460
1461static const unsigned int audio_clkout3_b_pins[] = {
1462
1463 RCAR_GP_PIN(5, 6),
1464};
1465
1466static const unsigned int audio_clkout3_b_mux[] = {
1467 AUDIO_CLKOUT3_B_MARK,
1468};
1469
1470static const unsigned int audio_clkout3_c_pins[] = {
1471
1472 RCAR_GP_PIN(6, 16),
1473};
1474
1475static const unsigned int audio_clkout3_c_mux[] = {
1476 AUDIO_CLKOUT3_C_MARK,
1477};
1478
1479
1480static const unsigned int avb_link_pins[] = {
1481
1482 RCAR_GP_PIN(2, 23),
1483};
1484
1485static const unsigned int avb_link_mux[] = {
1486 AVB_LINK_MARK,
1487};
1488
1489static const unsigned int avb_magic_pins[] = {
1490
1491 RCAR_GP_PIN(2, 22),
1492};
1493
1494static const unsigned int avb_magic_mux[] = {
1495 AVB_MAGIC_MARK,
1496};
1497
1498static const unsigned int avb_phy_int_pins[] = {
1499
1500 RCAR_GP_PIN(2, 21),
1501};
1502
1503static const unsigned int avb_phy_int_mux[] = {
1504 AVB_PHY_INT_MARK,
1505};
1506
1507static const unsigned int avb_mii_pins[] = {
1508
1509
1510
1511
1512
1513 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1514 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1515 RCAR_GP_PIN(2, 20),
1516};
1517
1518static const unsigned int avb_mii_mux[] = {
1519 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1520 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1521 AVB_TXCREFCLK_MARK,
1522};
1523
1524static const unsigned int avb_avtp_pps_pins[] = {
1525
1526 RCAR_GP_PIN(1, 2),
1527};
1528
1529static const unsigned int avb_avtp_pps_mux[] = {
1530 AVB_AVTP_PPS_MARK,
1531};
1532
1533static const unsigned int avb_avtp_match_pins[] = {
1534
1535 RCAR_GP_PIN(2, 24),
1536};
1537
1538static const unsigned int avb_avtp_match_mux[] = {
1539 AVB_AVTP_MATCH_MARK,
1540};
1541
1542static const unsigned int avb_avtp_capture_pins[] = {
1543
1544 RCAR_GP_PIN(2, 25),
1545};
1546
1547static const unsigned int avb_avtp_capture_mux[] = {
1548 AVB_AVTP_CAPTURE_MARK,
1549};
1550
1551
1552static const unsigned int can0_data_pins[] = {
1553
1554 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1555};
1556
1557static const unsigned int can0_data_mux[] = {
1558 CAN0_TX_MARK, CAN0_RX_MARK,
1559};
1560
1561static const unsigned int can1_data_pins[] = {
1562
1563 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1564};
1565
1566static const unsigned int can1_data_mux[] = {
1567 CAN1_TX_MARK, CAN1_RX_MARK,
1568};
1569
1570
1571static const unsigned int can_clk_pins[] = {
1572
1573 RCAR_GP_PIN(0, 14),
1574};
1575
1576static const unsigned int can_clk_mux[] = {
1577 CAN_CLK_MARK,
1578};
1579
1580
1581static const unsigned int canfd0_data_pins[] = {
1582
1583 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1584};
1585
1586static const unsigned int canfd0_data_mux[] = {
1587 CANFD0_TX_MARK, CANFD0_RX_MARK,
1588};
1589
1590static const unsigned int canfd1_data_pins[] = {
1591
1592 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1593};
1594
1595static const unsigned int canfd1_data_mux[] = {
1596 CANFD1_TX_MARK, CANFD1_RX_MARK,
1597};
1598
1599#ifdef CONFIG_PINCTRL_PFC_R8A77990
1600
1601static const unsigned int drif0_ctrl_a_pins[] = {
1602
1603 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1604};
1605
1606static const unsigned int drif0_ctrl_a_mux[] = {
1607 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1608};
1609
1610static const unsigned int drif0_data0_a_pins[] = {
1611
1612 RCAR_GP_PIN(5, 17),
1613};
1614
1615static const unsigned int drif0_data0_a_mux[] = {
1616 RIF0_D0_A_MARK,
1617};
1618
1619static const unsigned int drif0_data1_a_pins[] = {
1620
1621 RCAR_GP_PIN(5, 18),
1622};
1623
1624static const unsigned int drif0_data1_a_mux[] = {
1625 RIF0_D1_A_MARK,
1626};
1627
1628static const unsigned int drif0_ctrl_b_pins[] = {
1629
1630 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1631};
1632
1633static const unsigned int drif0_ctrl_b_mux[] = {
1634 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1635};
1636
1637static const unsigned int drif0_data0_b_pins[] = {
1638
1639 RCAR_GP_PIN(3, 13),
1640};
1641
1642static const unsigned int drif0_data0_b_mux[] = {
1643 RIF0_D0_B_MARK,
1644};
1645
1646static const unsigned int drif0_data1_b_pins[] = {
1647
1648 RCAR_GP_PIN(3, 14),
1649};
1650
1651static const unsigned int drif0_data1_b_mux[] = {
1652 RIF0_D1_B_MARK,
1653};
1654
1655
1656static const unsigned int drif1_ctrl_pins[] = {
1657
1658 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1659};
1660
1661static const unsigned int drif1_ctrl_mux[] = {
1662 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1663};
1664
1665static const unsigned int drif1_data0_pins[] = {
1666
1667 RCAR_GP_PIN(5, 2),
1668};
1669
1670static const unsigned int drif1_data0_mux[] = {
1671 RIF1_D0_MARK,
1672};
1673
1674static const unsigned int drif1_data1_pins[] = {
1675
1676 RCAR_GP_PIN(5, 3),
1677};
1678
1679static const unsigned int drif1_data1_mux[] = {
1680 RIF1_D1_MARK,
1681};
1682
1683
1684static const unsigned int drif2_ctrl_a_pins[] = {
1685
1686 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1687};
1688
1689static const unsigned int drif2_ctrl_a_mux[] = {
1690 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1691};
1692
1693static const unsigned int drif2_data0_a_pins[] = {
1694
1695 RCAR_GP_PIN(2, 8),
1696};
1697
1698static const unsigned int drif2_data0_a_mux[] = {
1699 RIF2_D0_A_MARK,
1700};
1701
1702static const unsigned int drif2_data1_a_pins[] = {
1703
1704 RCAR_GP_PIN(2, 9),
1705};
1706
1707static const unsigned int drif2_data1_a_mux[] = {
1708 RIF2_D1_A_MARK,
1709};
1710
1711static const unsigned int drif2_ctrl_b_pins[] = {
1712
1713 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1714};
1715
1716static const unsigned int drif2_ctrl_b_mux[] = {
1717 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1718};
1719
1720static const unsigned int drif2_data0_b_pins[] = {
1721
1722 RCAR_GP_PIN(1, 6),
1723};
1724
1725static const unsigned int drif2_data0_b_mux[] = {
1726 RIF2_D0_B_MARK,
1727};
1728
1729static const unsigned int drif2_data1_b_pins[] = {
1730
1731 RCAR_GP_PIN(1, 7),
1732};
1733
1734static const unsigned int drif2_data1_b_mux[] = {
1735 RIF2_D1_B_MARK,
1736};
1737
1738
1739static const unsigned int drif3_ctrl_a_pins[] = {
1740
1741 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1742};
1743
1744static const unsigned int drif3_ctrl_a_mux[] = {
1745 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1746};
1747
1748static const unsigned int drif3_data0_a_pins[] = {
1749
1750 RCAR_GP_PIN(2, 12),
1751};
1752
1753static const unsigned int drif3_data0_a_mux[] = {
1754 RIF3_D0_A_MARK,
1755};
1756
1757static const unsigned int drif3_data1_a_pins[] = {
1758
1759 RCAR_GP_PIN(2, 13),
1760};
1761
1762static const unsigned int drif3_data1_a_mux[] = {
1763 RIF3_D1_A_MARK,
1764};
1765
1766static const unsigned int drif3_ctrl_b_pins[] = {
1767
1768 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1769};
1770
1771static const unsigned int drif3_ctrl_b_mux[] = {
1772 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1773};
1774
1775static const unsigned int drif3_data0_b_pins[] = {
1776
1777 RCAR_GP_PIN(0, 10),
1778};
1779
1780static const unsigned int drif3_data0_b_mux[] = {
1781 RIF3_D0_B_MARK,
1782};
1783
1784static const unsigned int drif3_data1_b_pins[] = {
1785
1786 RCAR_GP_PIN(0, 11),
1787};
1788
1789static const unsigned int drif3_data1_b_mux[] = {
1790 RIF3_D1_B_MARK,
1791};
1792#endif
1793
1794
1795static const unsigned int du_rgb666_pins[] = {
1796
1797 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1798 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1799 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1800 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1801 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1802 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1803};
1804static const unsigned int du_rgb666_mux[] = {
1805 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1806 DU_DR3_MARK, DU_DR2_MARK,
1807 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1808 DU_DG3_MARK, DU_DG2_MARK,
1809 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1810 DU_DB3_MARK, DU_DB2_MARK,
1811};
1812static const unsigned int du_rgb888_pins[] = {
1813
1814 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1815 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1816 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1817 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1818 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1819 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1820 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1821 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1822 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1823};
1824static const unsigned int du_rgb888_mux[] = {
1825 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1826 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1827 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1828 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1829 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1830 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1831};
1832static const unsigned int du_clk_in_0_pins[] = {
1833
1834 RCAR_GP_PIN(0, 16),
1835};
1836static const unsigned int du_clk_in_0_mux[] = {
1837 DU_DOTCLKIN0_MARK
1838};
1839static const unsigned int du_clk_in_1_pins[] = {
1840
1841 RCAR_GP_PIN(1, 1),
1842};
1843static const unsigned int du_clk_in_1_mux[] = {
1844 DU_DOTCLKIN1_MARK
1845};
1846static const unsigned int du_clk_out_0_pins[] = {
1847
1848 RCAR_GP_PIN(1, 3),
1849};
1850static const unsigned int du_clk_out_0_mux[] = {
1851 DU_DOTCLKOUT0_MARK
1852};
1853static const unsigned int du_sync_pins[] = {
1854
1855 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1856};
1857static const unsigned int du_sync_mux[] = {
1858 DU_VSYNC_MARK, DU_HSYNC_MARK
1859};
1860static const unsigned int du_disp_cde_pins[] = {
1861
1862 RCAR_GP_PIN(1, 1),
1863};
1864static const unsigned int du_disp_cde_mux[] = {
1865 DU_DISP_CDE_MARK,
1866};
1867static const unsigned int du_cde_pins[] = {
1868
1869 RCAR_GP_PIN(1, 0),
1870};
1871static const unsigned int du_cde_mux[] = {
1872 DU_CDE_MARK,
1873};
1874static const unsigned int du_disp_pins[] = {
1875
1876 RCAR_GP_PIN(1, 2),
1877};
1878static const unsigned int du_disp_mux[] = {
1879 DU_DISP_MARK,
1880};
1881
1882
1883static const unsigned int hscif0_data_a_pins[] = {
1884
1885 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1886};
1887
1888static const unsigned int hscif0_data_a_mux[] = {
1889 HRX0_A_MARK, HTX0_A_MARK,
1890};
1891
1892static const unsigned int hscif0_clk_a_pins[] = {
1893
1894 RCAR_GP_PIN(5, 7),
1895};
1896
1897static const unsigned int hscif0_clk_a_mux[] = {
1898 HSCK0_A_MARK,
1899};
1900
1901static const unsigned int hscif0_ctrl_a_pins[] = {
1902
1903 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1904};
1905
1906static const unsigned int hscif0_ctrl_a_mux[] = {
1907 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1908};
1909
1910static const unsigned int hscif0_data_b_pins[] = {
1911
1912 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1913};
1914
1915static const unsigned int hscif0_data_b_mux[] = {
1916 HRX0_B_MARK, HTX0_B_MARK,
1917};
1918
1919static const unsigned int hscif0_clk_b_pins[] = {
1920
1921 RCAR_GP_PIN(6, 13),
1922};
1923
1924static const unsigned int hscif0_clk_b_mux[] = {
1925 HSCK0_B_MARK,
1926};
1927
1928
1929static const unsigned int hscif1_data_a_pins[] = {
1930
1931 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1932};
1933
1934static const unsigned int hscif1_data_a_mux[] = {
1935 HRX1_A_MARK, HTX1_A_MARK,
1936};
1937
1938static const unsigned int hscif1_clk_a_pins[] = {
1939
1940 RCAR_GP_PIN(5, 0),
1941};
1942
1943static const unsigned int hscif1_clk_a_mux[] = {
1944 HSCK1_A_MARK,
1945};
1946
1947static const unsigned int hscif1_data_b_pins[] = {
1948
1949 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1950};
1951
1952static const unsigned int hscif1_data_b_mux[] = {
1953 HRX1_B_MARK, HTX1_B_MARK,
1954};
1955
1956static const unsigned int hscif1_clk_b_pins[] = {
1957
1958 RCAR_GP_PIN(3, 0),
1959};
1960
1961static const unsigned int hscif1_clk_b_mux[] = {
1962 HSCK1_B_MARK,
1963};
1964
1965static const unsigned int hscif1_ctrl_b_pins[] = {
1966
1967 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1968};
1969
1970static const unsigned int hscif1_ctrl_b_mux[] = {
1971 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1972};
1973
1974
1975static const unsigned int hscif2_data_a_pins[] = {
1976
1977 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1978};
1979
1980static const unsigned int hscif2_data_a_mux[] = {
1981 HRX2_A_MARK, HTX2_A_MARK,
1982};
1983
1984static const unsigned int hscif2_clk_a_pins[] = {
1985
1986 RCAR_GP_PIN(6, 14),
1987};
1988
1989static const unsigned int hscif2_clk_a_mux[] = {
1990 HSCK2_A_MARK,
1991};
1992
1993static const unsigned int hscif2_ctrl_a_pins[] = {
1994
1995 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1996};
1997
1998static const unsigned int hscif2_ctrl_a_mux[] = {
1999 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2000};
2001
2002static const unsigned int hscif2_data_b_pins[] = {
2003
2004 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2005};
2006
2007static const unsigned int hscif2_data_b_mux[] = {
2008 HRX2_B_MARK, HTX2_B_MARK,
2009};
2010
2011
2012static const unsigned int hscif3_data_a_pins[] = {
2013
2014 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2015};
2016
2017static const unsigned int hscif3_data_a_mux[] = {
2018 HRX3_A_MARK, HTX3_A_MARK,
2019};
2020
2021static const unsigned int hscif3_data_b_pins[] = {
2022
2023 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2024};
2025
2026static const unsigned int hscif3_data_b_mux[] = {
2027 HRX3_B_MARK, HTX3_B_MARK,
2028};
2029
2030static const unsigned int hscif3_clk_b_pins[] = {
2031
2032 RCAR_GP_PIN(0, 4),
2033};
2034
2035static const unsigned int hscif3_clk_b_mux[] = {
2036 HSCK3_B_MARK,
2037};
2038
2039static const unsigned int hscif3_data_c_pins[] = {
2040
2041 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2042};
2043
2044static const unsigned int hscif3_data_c_mux[] = {
2045 HRX3_C_MARK, HTX3_C_MARK,
2046};
2047
2048static const unsigned int hscif3_clk_c_pins[] = {
2049
2050 RCAR_GP_PIN(2, 11),
2051};
2052
2053static const unsigned int hscif3_clk_c_mux[] = {
2054 HSCK3_C_MARK,
2055};
2056
2057static const unsigned int hscif3_ctrl_c_pins[] = {
2058
2059 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2060};
2061
2062static const unsigned int hscif3_ctrl_c_mux[] = {
2063 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2064};
2065
2066static const unsigned int hscif3_data_d_pins[] = {
2067
2068 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2069};
2070
2071static const unsigned int hscif3_data_d_mux[] = {
2072 HRX3_D_MARK, HTX3_D_MARK,
2073};
2074
2075static const unsigned int hscif3_data_e_pins[] = {
2076
2077 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2078};
2079
2080static const unsigned int hscif3_data_e_mux[] = {
2081 HRX3_E_MARK, HTX3_E_MARK,
2082};
2083
2084static const unsigned int hscif3_ctrl_e_pins[] = {
2085
2086 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2087};
2088
2089static const unsigned int hscif3_ctrl_e_mux[] = {
2090 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2091};
2092
2093
2094static const unsigned int hscif4_data_a_pins[] = {
2095
2096 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2097};
2098
2099static const unsigned int hscif4_data_a_mux[] = {
2100 HRX4_A_MARK, HTX4_A_MARK,
2101};
2102
2103static const unsigned int hscif4_clk_a_pins[] = {
2104
2105 RCAR_GP_PIN(2, 0),
2106};
2107
2108static const unsigned int hscif4_clk_a_mux[] = {
2109 HSCK4_A_MARK,
2110};
2111
2112static const unsigned int hscif4_ctrl_a_pins[] = {
2113
2114 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2115};
2116
2117static const unsigned int hscif4_ctrl_a_mux[] = {
2118 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2119};
2120
2121static const unsigned int hscif4_data_b_pins[] = {
2122
2123 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2124};
2125
2126static const unsigned int hscif4_data_b_mux[] = {
2127 HRX4_B_MARK, HTX4_B_MARK,
2128};
2129
2130static const unsigned int hscif4_clk_b_pins[] = {
2131
2132 RCAR_GP_PIN(2, 6),
2133};
2134
2135static const unsigned int hscif4_clk_b_mux[] = {
2136 HSCK4_B_MARK,
2137};
2138
2139static const unsigned int hscif4_data_c_pins[] = {
2140
2141 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2142};
2143
2144static const unsigned int hscif4_data_c_mux[] = {
2145 HRX4_C_MARK, HTX4_C_MARK,
2146};
2147
2148static const unsigned int hscif4_data_d_pins[] = {
2149
2150 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2151};
2152
2153static const unsigned int hscif4_data_d_mux[] = {
2154 HRX4_D_MARK, HTX4_D_MARK,
2155};
2156
2157static const unsigned int hscif4_data_e_pins[] = {
2158
2159 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2160};
2161
2162static const unsigned int hscif4_data_e_mux[] = {
2163 HRX4_E_MARK, HTX4_E_MARK,
2164};
2165
2166
2167static const unsigned int i2c1_a_pins[] = {
2168
2169 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2170};
2171
2172static const unsigned int i2c1_a_mux[] = {
2173 SCL1_A_MARK, SDA1_A_MARK,
2174};
2175
2176static const unsigned int i2c1_b_pins[] = {
2177
2178 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2179};
2180
2181static const unsigned int i2c1_b_mux[] = {
2182 SCL1_B_MARK, SDA1_B_MARK,
2183};
2184
2185static const unsigned int i2c1_c_pins[] = {
2186
2187 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2188};
2189
2190static const unsigned int i2c1_c_mux[] = {
2191 SCL1_C_MARK, SDA1_C_MARK,
2192};
2193
2194static const unsigned int i2c1_d_pins[] = {
2195
2196 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2197};
2198
2199static const unsigned int i2c1_d_mux[] = {
2200 SCL1_D_MARK, SDA1_D_MARK,
2201};
2202
2203static const unsigned int i2c2_a_pins[] = {
2204
2205 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2206};
2207
2208static const unsigned int i2c2_a_mux[] = {
2209 SCL2_A_MARK, SDA2_A_MARK,
2210};
2211
2212static const unsigned int i2c2_b_pins[] = {
2213
2214 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2215};
2216
2217static const unsigned int i2c2_b_mux[] = {
2218 SCL2_B_MARK, SDA2_B_MARK,
2219};
2220
2221static const unsigned int i2c2_c_pins[] = {
2222
2223 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2224};
2225
2226static const unsigned int i2c2_c_mux[] = {
2227 SCL2_C_MARK, SDA2_C_MARK,
2228};
2229
2230static const unsigned int i2c2_d_pins[] = {
2231
2232 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2233};
2234
2235static const unsigned int i2c2_d_mux[] = {
2236 SCL2_D_MARK, SDA2_D_MARK,
2237};
2238
2239static const unsigned int i2c2_e_pins[] = {
2240
2241 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2242};
2243
2244static const unsigned int i2c2_e_mux[] = {
2245 SCL2_E_MARK, SDA2_E_MARK,
2246};
2247
2248static const unsigned int i2c4_pins[] = {
2249
2250 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2251};
2252
2253static const unsigned int i2c4_mux[] = {
2254 SCL4_MARK, SDA4_MARK,
2255};
2256
2257static const unsigned int i2c5_pins[] = {
2258
2259 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2260};
2261
2262static const unsigned int i2c5_mux[] = {
2263 SCL5_MARK, SDA5_MARK,
2264};
2265
2266static const unsigned int i2c6_a_pins[] = {
2267
2268 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2269};
2270
2271static const unsigned int i2c6_a_mux[] = {
2272 SCL6_A_MARK, SDA6_A_MARK,
2273};
2274
2275static const unsigned int i2c6_b_pins[] = {
2276
2277 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2278};
2279
2280static const unsigned int i2c6_b_mux[] = {
2281 SCL6_B_MARK, SDA6_B_MARK,
2282};
2283
2284static const unsigned int i2c7_a_pins[] = {
2285
2286 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2287};
2288
2289static const unsigned int i2c7_a_mux[] = {
2290 SCL7_A_MARK, SDA7_A_MARK,
2291};
2292
2293static const unsigned int i2c7_b_pins[] = {
2294
2295 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2296};
2297
2298static const unsigned int i2c7_b_mux[] = {
2299 SCL7_B_MARK, SDA7_B_MARK,
2300};
2301
2302
2303static const unsigned int intc_ex_irq0_pins[] = {
2304
2305 RCAR_GP_PIN(1, 0),
2306};
2307static const unsigned int intc_ex_irq0_mux[] = {
2308 IRQ0_MARK,
2309};
2310static const unsigned int intc_ex_irq1_pins[] = {
2311
2312 RCAR_GP_PIN(1, 1),
2313};
2314static const unsigned int intc_ex_irq1_mux[] = {
2315 IRQ1_MARK,
2316};
2317static const unsigned int intc_ex_irq2_pins[] = {
2318
2319 RCAR_GP_PIN(1, 2),
2320};
2321static const unsigned int intc_ex_irq2_mux[] = {
2322 IRQ2_MARK,
2323};
2324static const unsigned int intc_ex_irq3_pins[] = {
2325
2326 RCAR_GP_PIN(1, 9),
2327};
2328static const unsigned int intc_ex_irq3_mux[] = {
2329 IRQ3_MARK,
2330};
2331static const unsigned int intc_ex_irq4_pins[] = {
2332
2333 RCAR_GP_PIN(1, 10),
2334};
2335static const unsigned int intc_ex_irq4_mux[] = {
2336 IRQ4_MARK,
2337};
2338static const unsigned int intc_ex_irq5_pins[] = {
2339
2340 RCAR_GP_PIN(0, 7),
2341};
2342static const unsigned int intc_ex_irq5_mux[] = {
2343 IRQ5_MARK,
2344};
2345
2346#ifdef CONFIG_PINCTRL_PFC_R8A77990
2347
2348static const unsigned int mlb_3pin_pins[] = {
2349 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2350};
2351static const unsigned int mlb_3pin_mux[] = {
2352 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2353};
2354#endif
2355
2356
2357static const unsigned int msiof0_clk_pins[] = {
2358
2359 RCAR_GP_PIN(5, 10),
2360};
2361
2362static const unsigned int msiof0_clk_mux[] = {
2363 MSIOF0_SCK_MARK,
2364};
2365
2366static const unsigned int msiof0_sync_pins[] = {
2367
2368 RCAR_GP_PIN(5, 13),
2369};
2370
2371static const unsigned int msiof0_sync_mux[] = {
2372 MSIOF0_SYNC_MARK,
2373};
2374
2375static const unsigned int msiof0_ss1_pins[] = {
2376
2377 RCAR_GP_PIN(5, 14),
2378};
2379
2380static const unsigned int msiof0_ss1_mux[] = {
2381 MSIOF0_SS1_MARK,
2382};
2383
2384static const unsigned int msiof0_ss2_pins[] = {
2385
2386 RCAR_GP_PIN(5, 15),
2387};
2388
2389static const unsigned int msiof0_ss2_mux[] = {
2390 MSIOF0_SS2_MARK,
2391};
2392
2393static const unsigned int msiof0_txd_pins[] = {
2394
2395 RCAR_GP_PIN(5, 12),
2396};
2397
2398static const unsigned int msiof0_txd_mux[] = {
2399 MSIOF0_TXD_MARK,
2400};
2401
2402static const unsigned int msiof0_rxd_pins[] = {
2403
2404 RCAR_GP_PIN(5, 11),
2405};
2406
2407static const unsigned int msiof0_rxd_mux[] = {
2408 MSIOF0_RXD_MARK,
2409};
2410
2411
2412static const unsigned int msiof1_clk_pins[] = {
2413
2414 RCAR_GP_PIN(1, 19),
2415};
2416
2417static const unsigned int msiof1_clk_mux[] = {
2418 MSIOF1_SCK_MARK,
2419};
2420
2421static const unsigned int msiof1_sync_pins[] = {
2422
2423 RCAR_GP_PIN(1, 16),
2424};
2425
2426static const unsigned int msiof1_sync_mux[] = {
2427 MSIOF1_SYNC_MARK,
2428};
2429
2430static const unsigned int msiof1_ss1_pins[] = {
2431
2432 RCAR_GP_PIN(1, 14),
2433};
2434
2435static const unsigned int msiof1_ss1_mux[] = {
2436 MSIOF1_SS1_MARK,
2437};
2438
2439static const unsigned int msiof1_ss2_pins[] = {
2440
2441 RCAR_GP_PIN(1, 15),
2442};
2443
2444static const unsigned int msiof1_ss2_mux[] = {
2445 MSIOF1_SS2_MARK,
2446};
2447
2448static const unsigned int msiof1_txd_pins[] = {
2449
2450 RCAR_GP_PIN(1, 18),
2451};
2452
2453static const unsigned int msiof1_txd_mux[] = {
2454 MSIOF1_TXD_MARK,
2455};
2456
2457static const unsigned int msiof1_rxd_pins[] = {
2458
2459 RCAR_GP_PIN(1, 17),
2460};
2461
2462static const unsigned int msiof1_rxd_mux[] = {
2463 MSIOF1_RXD_MARK,
2464};
2465
2466
2467static const unsigned int msiof2_clk_a_pins[] = {
2468
2469 RCAR_GP_PIN(0, 8),
2470};
2471
2472static const unsigned int msiof2_clk_a_mux[] = {
2473 MSIOF2_SCK_A_MARK,
2474};
2475
2476static const unsigned int msiof2_sync_a_pins[] = {
2477
2478 RCAR_GP_PIN(0, 9),
2479};
2480
2481static const unsigned int msiof2_sync_a_mux[] = {
2482 MSIOF2_SYNC_A_MARK,
2483};
2484
2485static const unsigned int msiof2_ss1_a_pins[] = {
2486
2487 RCAR_GP_PIN(0, 15),
2488};
2489
2490static const unsigned int msiof2_ss1_a_mux[] = {
2491 MSIOF2_SS1_A_MARK,
2492};
2493
2494static const unsigned int msiof2_ss2_a_pins[] = {
2495
2496 RCAR_GP_PIN(0, 14),
2497};
2498
2499static const unsigned int msiof2_ss2_a_mux[] = {
2500 MSIOF2_SS2_A_MARK,
2501};
2502
2503static const unsigned int msiof2_txd_a_pins[] = {
2504
2505 RCAR_GP_PIN(0, 11),
2506};
2507
2508static const unsigned int msiof2_txd_a_mux[] = {
2509 MSIOF2_TXD_A_MARK,
2510};
2511
2512static const unsigned int msiof2_rxd_a_pins[] = {
2513
2514 RCAR_GP_PIN(0, 10),
2515};
2516
2517static const unsigned int msiof2_rxd_a_mux[] = {
2518 MSIOF2_RXD_A_MARK,
2519};
2520
2521static const unsigned int msiof2_clk_b_pins[] = {
2522
2523 RCAR_GP_PIN(1, 13),
2524};
2525
2526static const unsigned int msiof2_clk_b_mux[] = {
2527 MSIOF2_SCK_B_MARK,
2528};
2529
2530static const unsigned int msiof2_sync_b_pins[] = {
2531
2532 RCAR_GP_PIN(1, 10),
2533};
2534
2535static const unsigned int msiof2_sync_b_mux[] = {
2536 MSIOF2_SYNC_B_MARK,
2537};
2538
2539static const unsigned int msiof2_ss1_b_pins[] = {
2540
2541 RCAR_GP_PIN(1, 16),
2542};
2543
2544static const unsigned int msiof2_ss1_b_mux[] = {
2545 MSIOF2_SS1_B_MARK,
2546};
2547
2548static const unsigned int msiof2_ss2_b_pins[] = {
2549
2550 RCAR_GP_PIN(1, 12),
2551};
2552
2553static const unsigned int msiof2_ss2_b_mux[] = {
2554 MSIOF2_SS2_B_MARK,
2555};
2556
2557static const unsigned int msiof2_txd_b_pins[] = {
2558
2559 RCAR_GP_PIN(1, 15),
2560};
2561
2562static const unsigned int msiof2_txd_b_mux[] = {
2563 MSIOF2_TXD_B_MARK,
2564};
2565
2566static const unsigned int msiof2_rxd_b_pins[] = {
2567
2568 RCAR_GP_PIN(1, 14),
2569};
2570
2571static const unsigned int msiof2_rxd_b_mux[] = {
2572 MSIOF2_RXD_B_MARK,
2573};
2574
2575
2576static const unsigned int msiof3_clk_a_pins[] = {
2577
2578 RCAR_GP_PIN(0, 0),
2579};
2580
2581static const unsigned int msiof3_clk_a_mux[] = {
2582 MSIOF3_SCK_A_MARK,
2583};
2584
2585static const unsigned int msiof3_sync_a_pins[] = {
2586
2587 RCAR_GP_PIN(0, 1),
2588};
2589
2590static const unsigned int msiof3_sync_a_mux[] = {
2591 MSIOF3_SYNC_A_MARK,
2592};
2593
2594static const unsigned int msiof3_ss1_a_pins[] = {
2595
2596 RCAR_GP_PIN(0, 15),
2597};
2598
2599static const unsigned int msiof3_ss1_a_mux[] = {
2600 MSIOF3_SS1_A_MARK,
2601};
2602
2603static const unsigned int msiof3_ss2_a_pins[] = {
2604
2605 RCAR_GP_PIN(0, 4),
2606};
2607
2608static const unsigned int msiof3_ss2_a_mux[] = {
2609 MSIOF3_SS2_A_MARK,
2610};
2611
2612static const unsigned int msiof3_txd_a_pins[] = {
2613
2614 RCAR_GP_PIN(0, 3),
2615};
2616
2617static const unsigned int msiof3_txd_a_mux[] = {
2618 MSIOF3_TXD_A_MARK,
2619};
2620
2621static const unsigned int msiof3_rxd_a_pins[] = {
2622
2623 RCAR_GP_PIN(0, 2),
2624};
2625
2626static const unsigned int msiof3_rxd_a_mux[] = {
2627 MSIOF3_RXD_A_MARK,
2628};
2629
2630static const unsigned int msiof3_clk_b_pins[] = {
2631
2632 RCAR_GP_PIN(1, 5),
2633};
2634
2635static const unsigned int msiof3_clk_b_mux[] = {
2636 MSIOF3_SCK_B_MARK,
2637};
2638
2639static const unsigned int msiof3_sync_b_pins[] = {
2640
2641 RCAR_GP_PIN(1, 4),
2642};
2643
2644static const unsigned int msiof3_sync_b_mux[] = {
2645 MSIOF3_SYNC_B_MARK,
2646};
2647
2648static const unsigned int msiof3_ss1_b_pins[] = {
2649
2650 RCAR_GP_PIN(1, 0),
2651};
2652
2653static const unsigned int msiof3_ss1_b_mux[] = {
2654 MSIOF3_SS1_B_MARK,
2655};
2656
2657static const unsigned int msiof3_txd_b_pins[] = {
2658
2659 RCAR_GP_PIN(1, 7),
2660};
2661
2662static const unsigned int msiof3_txd_b_mux[] = {
2663 MSIOF3_TXD_B_MARK,
2664};
2665
2666static const unsigned int msiof3_rxd_b_pins[] = {
2667
2668 RCAR_GP_PIN(1, 6),
2669};
2670
2671static const unsigned int msiof3_rxd_b_mux[] = {
2672 MSIOF3_RXD_B_MARK,
2673};
2674
2675
2676static const unsigned int pwm0_a_pins[] = {
2677
2678 RCAR_GP_PIN(2, 22),
2679};
2680
2681static const unsigned int pwm0_a_mux[] = {
2682 PWM0_A_MARK,
2683};
2684
2685static const unsigned int pwm0_b_pins[] = {
2686
2687 RCAR_GP_PIN(6, 3),
2688};
2689
2690static const unsigned int pwm0_b_mux[] = {
2691 PWM0_B_MARK,
2692};
2693
2694
2695static const unsigned int pwm1_a_pins[] = {
2696
2697 RCAR_GP_PIN(2, 23),
2698};
2699
2700static const unsigned int pwm1_a_mux[] = {
2701 PWM1_A_MARK,
2702};
2703
2704static const unsigned int pwm1_b_pins[] = {
2705
2706 RCAR_GP_PIN(6, 4),
2707};
2708
2709static const unsigned int pwm1_b_mux[] = {
2710 PWM1_B_MARK,
2711};
2712
2713
2714static const unsigned int pwm2_a_pins[] = {
2715
2716 RCAR_GP_PIN(1, 0),
2717};
2718
2719static const unsigned int pwm2_a_mux[] = {
2720 PWM2_A_MARK,
2721};
2722
2723static const unsigned int pwm2_b_pins[] = {
2724
2725 RCAR_GP_PIN(1, 4),
2726};
2727
2728static const unsigned int pwm2_b_mux[] = {
2729 PWM2_B_MARK,
2730};
2731
2732static const unsigned int pwm2_c_pins[] = {
2733
2734 RCAR_GP_PIN(6, 5),
2735};
2736
2737static const unsigned int pwm2_c_mux[] = {
2738 PWM2_C_MARK,
2739};
2740
2741
2742static const unsigned int pwm3_a_pins[] = {
2743
2744 RCAR_GP_PIN(1, 1),
2745};
2746
2747static const unsigned int pwm3_a_mux[] = {
2748 PWM3_A_MARK,
2749};
2750
2751static const unsigned int pwm3_b_pins[] = {
2752
2753 RCAR_GP_PIN(1, 5),
2754};
2755
2756static const unsigned int pwm3_b_mux[] = {
2757 PWM3_B_MARK,
2758};
2759
2760static const unsigned int pwm3_c_pins[] = {
2761
2762 RCAR_GP_PIN(6, 6),
2763};
2764
2765static const unsigned int pwm3_c_mux[] = {
2766 PWM3_C_MARK,
2767};
2768
2769
2770static const unsigned int pwm4_a_pins[] = {
2771
2772 RCAR_GP_PIN(1, 3),
2773};
2774
2775static const unsigned int pwm4_a_mux[] = {
2776 PWM4_A_MARK,
2777};
2778
2779static const unsigned int pwm4_b_pins[] = {
2780
2781 RCAR_GP_PIN(6, 7),
2782};
2783
2784static const unsigned int pwm4_b_mux[] = {
2785 PWM4_B_MARK,
2786};
2787
2788
2789static const unsigned int pwm5_a_pins[] = {
2790
2791 RCAR_GP_PIN(2, 24),
2792};
2793
2794static const unsigned int pwm5_a_mux[] = {
2795 PWM5_A_MARK,
2796};
2797
2798static const unsigned int pwm5_b_pins[] = {
2799
2800 RCAR_GP_PIN(6, 10),
2801};
2802
2803static const unsigned int pwm5_b_mux[] = {
2804 PWM5_B_MARK,
2805};
2806
2807
2808static const unsigned int pwm6_a_pins[] = {
2809
2810 RCAR_GP_PIN(2, 25),
2811};
2812
2813static const unsigned int pwm6_a_mux[] = {
2814 PWM6_A_MARK,
2815};
2816
2817static const unsigned int pwm6_b_pins[] = {
2818
2819 RCAR_GP_PIN(6, 11),
2820};
2821
2822static const unsigned int pwm6_b_mux[] = {
2823 PWM6_B_MARK,
2824};
2825
2826
2827static const unsigned int qspi0_ctrl_pins[] = {
2828
2829 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
2830};
2831static const unsigned int qspi0_ctrl_mux[] = {
2832 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2833};
2834
2835static const unsigned int qspi1_ctrl_pins[] = {
2836
2837 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
2838};
2839static const unsigned int qspi1_ctrl_mux[] = {
2840 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2841};
2842
2843
2844static const unsigned int rpc_clk_pins[] = {
2845
2846
2847 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6),
2848};
2849static const unsigned int rpc_clk_mux[] = {
2850 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
2851};
2852static const unsigned int rpc_ctrl_pins[] = {
2853
2854
2855 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11),
2856};
2857static const unsigned int rpc_ctrl_mux[] = {
2858 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
2859};
2860static const unsigned int rpc_data_pins[] = {
2861
2862 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2863 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
2864 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2865 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2866};
2867static const unsigned int rpc_data_mux[] = {
2868 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2869 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
2870 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2871 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
2872};
2873static const unsigned int rpc_reset_pins[] = {
2874
2875 RCAR_GP_PIN(2, 13),
2876};
2877static const unsigned int rpc_reset_mux[] = {
2878 RPC_RESET_N_MARK,
2879};
2880static const unsigned int rpc_int_pins[] = {
2881
2882 RCAR_GP_PIN(2, 12),
2883};
2884static const unsigned int rpc_int_mux[] = {
2885 RPC_INT_N_MARK,
2886};
2887
2888
2889static const unsigned int scif0_data_a_pins[] = {
2890
2891 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2892};
2893
2894static const unsigned int scif0_data_a_mux[] = {
2895 RX0_A_MARK, TX0_A_MARK,
2896};
2897
2898static const unsigned int scif0_clk_a_pins[] = {
2899
2900 RCAR_GP_PIN(5, 0),
2901};
2902
2903static const unsigned int scif0_clk_a_mux[] = {
2904 SCK0_A_MARK,
2905};
2906
2907static const unsigned int scif0_ctrl_a_pins[] = {
2908
2909 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2910};
2911
2912static const unsigned int scif0_ctrl_a_mux[] = {
2913 RTS0_N_A_MARK, CTS0_N_A_MARK,
2914};
2915
2916static const unsigned int scif0_data_b_pins[] = {
2917
2918 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2919};
2920
2921static const unsigned int scif0_data_b_mux[] = {
2922 RX0_B_MARK, TX0_B_MARK,
2923};
2924
2925static const unsigned int scif0_clk_b_pins[] = {
2926
2927 RCAR_GP_PIN(5, 18),
2928};
2929
2930static const unsigned int scif0_clk_b_mux[] = {
2931 SCK0_B_MARK,
2932};
2933
2934
2935static const unsigned int scif1_data_pins[] = {
2936
2937 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2938};
2939
2940static const unsigned int scif1_data_mux[] = {
2941 RX1_MARK, TX1_MARK,
2942};
2943
2944static const unsigned int scif1_clk_pins[] = {
2945
2946 RCAR_GP_PIN(5, 16),
2947};
2948
2949static const unsigned int scif1_clk_mux[] = {
2950 SCK1_MARK,
2951};
2952
2953static const unsigned int scif1_ctrl_pins[] = {
2954
2955 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2956};
2957
2958static const unsigned int scif1_ctrl_mux[] = {
2959 RTS1_N_MARK, CTS1_N_MARK,
2960};
2961
2962
2963static const unsigned int scif2_data_a_pins[] = {
2964
2965 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2966};
2967
2968static const unsigned int scif2_data_a_mux[] = {
2969 RX2_A_MARK, TX2_A_MARK,
2970};
2971
2972static const unsigned int scif2_clk_a_pins[] = {
2973
2974 RCAR_GP_PIN(5, 7),
2975};
2976
2977static const unsigned int scif2_clk_a_mux[] = {
2978 SCK2_A_MARK,
2979};
2980
2981static const unsigned int scif2_data_b_pins[] = {
2982
2983 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2984};
2985
2986static const unsigned int scif2_data_b_mux[] = {
2987 RX2_B_MARK, TX2_B_MARK,
2988};
2989
2990
2991static const unsigned int scif3_data_a_pins[] = {
2992
2993 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2994};
2995
2996static const unsigned int scif3_data_a_mux[] = {
2997 RX3_A_MARK, TX3_A_MARK,
2998};
2999
3000static const unsigned int scif3_clk_a_pins[] = {
3001
3002 RCAR_GP_PIN(0, 1),
3003};
3004
3005static const unsigned int scif3_clk_a_mux[] = {
3006 SCK3_A_MARK,
3007};
3008
3009static const unsigned int scif3_ctrl_a_pins[] = {
3010
3011 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
3012};
3013
3014static const unsigned int scif3_ctrl_a_mux[] = {
3015 RTS3_N_A_MARK, CTS3_N_A_MARK,
3016};
3017
3018static const unsigned int scif3_data_b_pins[] = {
3019
3020 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3021};
3022
3023static const unsigned int scif3_data_b_mux[] = {
3024 RX3_B_MARK, TX3_B_MARK,
3025};
3026
3027static const unsigned int scif3_data_c_pins[] = {
3028
3029 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3030};
3031
3032static const unsigned int scif3_data_c_mux[] = {
3033 RX3_C_MARK, TX3_C_MARK,
3034};
3035
3036static const unsigned int scif3_clk_c_pins[] = {
3037
3038 RCAR_GP_PIN(2, 24),
3039};
3040
3041static const unsigned int scif3_clk_c_mux[] = {
3042 SCK3_C_MARK,
3043};
3044
3045
3046static const unsigned int scif4_data_a_pins[] = {
3047
3048 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3049};
3050
3051static const unsigned int scif4_data_a_mux[] = {
3052 RX4_A_MARK, TX4_A_MARK,
3053};
3054
3055static const unsigned int scif4_clk_a_pins[] = {
3056
3057 RCAR_GP_PIN(1, 5),
3058};
3059
3060static const unsigned int scif4_clk_a_mux[] = {
3061 SCK4_A_MARK,
3062};
3063
3064static const unsigned int scif4_ctrl_a_pins[] = {
3065
3066 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
3067};
3068
3069static const unsigned int scif4_ctrl_a_mux[] = {
3070 RTS4_N_A_MARK, CTS4_N_A_MARK,
3071};
3072
3073static const unsigned int scif4_data_b_pins[] = {
3074
3075 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
3076};
3077
3078static const unsigned int scif4_data_b_mux[] = {
3079 RX4_B_MARK, TX4_B_MARK,
3080};
3081
3082static const unsigned int scif4_clk_b_pins[] = {
3083
3084 RCAR_GP_PIN(0, 8),
3085};
3086
3087static const unsigned int scif4_clk_b_mux[] = {
3088 SCK4_B_MARK,
3089};
3090
3091static const unsigned int scif4_data_c_pins[] = {
3092
3093 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3094};
3095
3096static const unsigned int scif4_data_c_mux[] = {
3097 RX4_C_MARK, TX4_C_MARK,
3098};
3099
3100static const unsigned int scif4_ctrl_c_pins[] = {
3101
3102 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3103};
3104
3105static const unsigned int scif4_ctrl_c_mux[] = {
3106 RTS4_N_C_MARK, CTS4_N_C_MARK,
3107};
3108
3109
3110static const unsigned int scif5_data_a_pins[] = {
3111
3112 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3113};
3114
3115static const unsigned int scif5_data_a_mux[] = {
3116 RX5_A_MARK, TX5_A_MARK,
3117};
3118
3119static const unsigned int scif5_clk_a_pins[] = {
3120
3121 RCAR_GP_PIN(1, 13),
3122};
3123
3124static const unsigned int scif5_clk_a_mux[] = {
3125 SCK5_A_MARK,
3126};
3127
3128static const unsigned int scif5_data_b_pins[] = {
3129
3130 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3131};
3132
3133static const unsigned int scif5_data_b_mux[] = {
3134 RX5_B_MARK, TX5_B_MARK,
3135};
3136
3137static const unsigned int scif5_data_c_pins[] = {
3138
3139 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3140};
3141
3142static const unsigned int scif5_data_c_mux[] = {
3143 RX5_C_MARK, TX5_C_MARK,
3144};
3145
3146
3147static const unsigned int scif_clk_a_pins[] = {
3148
3149 RCAR_GP_PIN(5, 3),
3150};
3151
3152static const unsigned int scif_clk_a_mux[] = {
3153 SCIF_CLK_A_MARK,
3154};
3155
3156static const unsigned int scif_clk_b_pins[] = {
3157
3158 RCAR_GP_PIN(5, 7),
3159};
3160
3161static const unsigned int scif_clk_b_mux[] = {
3162 SCIF_CLK_B_MARK,
3163};
3164
3165
3166static const unsigned int sdhi0_data_pins[] = {
3167
3168 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3169 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3170};
3171
3172static const unsigned int sdhi0_data_mux[] = {
3173 SD0_DAT0_MARK, SD0_DAT1_MARK,
3174 SD0_DAT2_MARK, SD0_DAT3_MARK,
3175};
3176
3177static const unsigned int sdhi0_ctrl_pins[] = {
3178
3179 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3180};
3181
3182static const unsigned int sdhi0_ctrl_mux[] = {
3183 SD0_CLK_MARK, SD0_CMD_MARK,
3184};
3185
3186static const unsigned int sdhi0_cd_pins[] = {
3187
3188 RCAR_GP_PIN(3, 12),
3189};
3190
3191static const unsigned int sdhi0_cd_mux[] = {
3192 SD0_CD_MARK,
3193};
3194
3195static const unsigned int sdhi0_wp_pins[] = {
3196
3197 RCAR_GP_PIN(3, 13),
3198};
3199
3200static const unsigned int sdhi0_wp_mux[] = {
3201 SD0_WP_MARK,
3202};
3203
3204
3205static const unsigned int sdhi1_data_pins[] = {
3206
3207 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3208 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3209};
3210
3211static const unsigned int sdhi1_data_mux[] = {
3212 SD1_DAT0_MARK, SD1_DAT1_MARK,
3213 SD1_DAT2_MARK, SD1_DAT3_MARK,
3214};
3215
3216static const unsigned int sdhi1_ctrl_pins[] = {
3217
3218 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3219};
3220
3221static const unsigned int sdhi1_ctrl_mux[] = {
3222 SD1_CLK_MARK, SD1_CMD_MARK,
3223};
3224
3225static const unsigned int sdhi1_cd_pins[] = {
3226
3227 RCAR_GP_PIN(3, 14),
3228};
3229
3230static const unsigned int sdhi1_cd_mux[] = {
3231 SD1_CD_MARK,
3232};
3233
3234static const unsigned int sdhi1_wp_pins[] = {
3235
3236 RCAR_GP_PIN(3, 15),
3237};
3238
3239static const unsigned int sdhi1_wp_mux[] = {
3240 SD1_WP_MARK,
3241};
3242
3243
3244static const unsigned int sdhi3_data_pins[] = {
3245
3246 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3247 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3248 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3249 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3250};
3251
3252static const unsigned int sdhi3_data_mux[] = {
3253 SD3_DAT0_MARK, SD3_DAT1_MARK,
3254 SD3_DAT2_MARK, SD3_DAT3_MARK,
3255 SD3_DAT4_MARK, SD3_DAT5_MARK,
3256 SD3_DAT6_MARK, SD3_DAT7_MARK,
3257};
3258
3259static const unsigned int sdhi3_ctrl_pins[] = {
3260
3261 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3262};
3263
3264static const unsigned int sdhi3_ctrl_mux[] = {
3265 SD3_CLK_MARK, SD3_CMD_MARK,
3266};
3267
3268static const unsigned int sdhi3_cd_pins[] = {
3269
3270 RCAR_GP_PIN(3, 12),
3271};
3272
3273static const unsigned int sdhi3_cd_mux[] = {
3274 SD3_CD_MARK,
3275};
3276
3277static const unsigned int sdhi3_wp_pins[] = {
3278
3279 RCAR_GP_PIN(3, 13),
3280};
3281
3282static const unsigned int sdhi3_wp_mux[] = {
3283 SD3_WP_MARK,
3284};
3285
3286static const unsigned int sdhi3_ds_pins[] = {
3287
3288 RCAR_GP_PIN(4, 10),
3289};
3290
3291static const unsigned int sdhi3_ds_mux[] = {
3292 SD3_DS_MARK,
3293};
3294
3295
3296static const unsigned int ssi0_data_pins[] = {
3297
3298 RCAR_GP_PIN(6, 2),
3299};
3300
3301static const unsigned int ssi0_data_mux[] = {
3302 SSI_SDATA0_MARK,
3303};
3304
3305static const unsigned int ssi01239_ctrl_pins[] = {
3306
3307 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3308};
3309
3310static const unsigned int ssi01239_ctrl_mux[] = {
3311 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3312};
3313
3314static const unsigned int ssi1_data_pins[] = {
3315
3316 RCAR_GP_PIN(6, 3),
3317};
3318
3319static const unsigned int ssi1_data_mux[] = {
3320 SSI_SDATA1_MARK,
3321};
3322
3323static const unsigned int ssi1_ctrl_pins[] = {
3324
3325 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3326};
3327
3328static const unsigned int ssi1_ctrl_mux[] = {
3329 SSI_SCK1_MARK, SSI_WS1_MARK,
3330};
3331
3332static const unsigned int ssi2_data_pins[] = {
3333
3334 RCAR_GP_PIN(6, 4),
3335};
3336
3337static const unsigned int ssi2_data_mux[] = {
3338 SSI_SDATA2_MARK,
3339};
3340
3341static const unsigned int ssi2_ctrl_a_pins[] = {
3342
3343 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3344};
3345
3346static const unsigned int ssi2_ctrl_a_mux[] = {
3347 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3348};
3349
3350static const unsigned int ssi2_ctrl_b_pins[] = {
3351
3352 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3353};
3354
3355static const unsigned int ssi2_ctrl_b_mux[] = {
3356 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3357};
3358
3359static const unsigned int ssi3_data_pins[] = {
3360
3361 RCAR_GP_PIN(6, 7),
3362};
3363
3364static const unsigned int ssi3_data_mux[] = {
3365 SSI_SDATA3_MARK,
3366};
3367
3368static const unsigned int ssi349_ctrl_pins[] = {
3369
3370 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3371};
3372
3373static const unsigned int ssi349_ctrl_mux[] = {
3374 SSI_SCK349_MARK, SSI_WS349_MARK,
3375};
3376
3377static const unsigned int ssi4_data_pins[] = {
3378
3379 RCAR_GP_PIN(6, 10),
3380};
3381
3382static const unsigned int ssi4_data_mux[] = {
3383 SSI_SDATA4_MARK,
3384};
3385
3386static const unsigned int ssi4_ctrl_pins[] = {
3387
3388 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3389};
3390
3391static const unsigned int ssi4_ctrl_mux[] = {
3392 SSI_SCK4_MARK, SSI_WS4_MARK,
3393};
3394
3395static const unsigned int ssi5_data_pins[] = {
3396
3397 RCAR_GP_PIN(6, 13),
3398};
3399
3400static const unsigned int ssi5_data_mux[] = {
3401 SSI_SDATA5_MARK,
3402};
3403
3404static const unsigned int ssi5_ctrl_pins[] = {
3405
3406 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3407};
3408
3409static const unsigned int ssi5_ctrl_mux[] = {
3410 SSI_SCK5_MARK, SSI_WS5_MARK,
3411};
3412
3413static const unsigned int ssi6_data_pins[] = {
3414
3415 RCAR_GP_PIN(6, 16),
3416};
3417
3418static const unsigned int ssi6_data_mux[] = {
3419 SSI_SDATA6_MARK,
3420};
3421
3422static const unsigned int ssi6_ctrl_pins[] = {
3423
3424 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3425};
3426
3427static const unsigned int ssi6_ctrl_mux[] = {
3428 SSI_SCK6_MARK, SSI_WS6_MARK,
3429};
3430
3431static const unsigned int ssi7_data_pins[] = {
3432
3433 RCAR_GP_PIN(5, 12),
3434};
3435
3436static const unsigned int ssi7_data_mux[] = {
3437 SSI_SDATA7_MARK,
3438};
3439
3440static const unsigned int ssi78_ctrl_pins[] = {
3441
3442 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3443};
3444
3445static const unsigned int ssi78_ctrl_mux[] = {
3446 SSI_SCK78_MARK, SSI_WS78_MARK,
3447};
3448
3449static const unsigned int ssi8_data_pins[] = {
3450
3451 RCAR_GP_PIN(5, 13),
3452};
3453
3454static const unsigned int ssi8_data_mux[] = {
3455 SSI_SDATA8_MARK,
3456};
3457
3458static const unsigned int ssi9_data_pins[] = {
3459
3460 RCAR_GP_PIN(5, 16),
3461};
3462
3463static const unsigned int ssi9_data_mux[] = {
3464 SSI_SDATA9_MARK,
3465};
3466
3467static const unsigned int ssi9_ctrl_a_pins[] = {
3468
3469 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3470};
3471
3472static const unsigned int ssi9_ctrl_a_mux[] = {
3473 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3474};
3475
3476static const unsigned int ssi9_ctrl_b_pins[] = {
3477
3478 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3479};
3480
3481static const unsigned int ssi9_ctrl_b_mux[] = {
3482 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3483};
3484
3485
3486static const unsigned int tmu_tclk1_a_pins[] = {
3487
3488 RCAR_GP_PIN(3, 12),
3489};
3490
3491static const unsigned int tmu_tclk1_a_mux[] = {
3492 TCLK1_A_MARK,
3493};
3494
3495static const unsigned int tmu_tclk1_b_pins[] = {
3496
3497 RCAR_GP_PIN(5, 17),
3498};
3499
3500static const unsigned int tmu_tclk1_b_mux[] = {
3501 TCLK1_B_MARK,
3502};
3503
3504static const unsigned int tmu_tclk2_a_pins[] = {
3505
3506 RCAR_GP_PIN(3, 13),
3507};
3508
3509static const unsigned int tmu_tclk2_a_mux[] = {
3510 TCLK2_A_MARK,
3511};
3512
3513static const unsigned int tmu_tclk2_b_pins[] = {
3514
3515 RCAR_GP_PIN(5, 18),
3516};
3517
3518static const unsigned int tmu_tclk2_b_mux[] = {
3519 TCLK2_B_MARK,
3520};
3521
3522
3523static const unsigned int usb0_a_pins[] = {
3524
3525 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3526};
3527
3528static const unsigned int usb0_a_mux[] = {
3529 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3530};
3531
3532static const unsigned int usb0_b_pins[] = {
3533
3534 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3535};
3536
3537static const unsigned int usb0_b_mux[] = {
3538 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3539};
3540
3541static const unsigned int usb0_id_pins[] = {
3542
3543 RCAR_GP_PIN(5, 0)
3544};
3545
3546static const unsigned int usb0_id_mux[] = {
3547 USB0_ID_MARK,
3548};
3549
3550
3551static const unsigned int usb30_pins[] = {
3552
3553 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3554};
3555
3556static const unsigned int usb30_mux[] = {
3557 USB30_PWEN_MARK, USB30_OVC_MARK,
3558};
3559
3560static const unsigned int usb30_id_pins[] = {
3561
3562 RCAR_GP_PIN(5, 0),
3563};
3564
3565static const unsigned int usb30_id_mux[] = {
3566 USB3HS0_ID_MARK,
3567};
3568
3569
3570static const unsigned int vin4_data18_a_pins[] = {
3571 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3572 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3573 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3574 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3575 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3576 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3577 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3578 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3579 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3580};
3581
3582static const unsigned int vin4_data18_a_mux[] = {
3583 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3584 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3585 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3586 VI4_DATA10_MARK, VI4_DATA11_MARK,
3587 VI4_DATA12_MARK, VI4_DATA13_MARK,
3588 VI4_DATA14_MARK, VI4_DATA15_MARK,
3589 VI4_DATA18_MARK, VI4_DATA19_MARK,
3590 VI4_DATA20_MARK, VI4_DATA21_MARK,
3591 VI4_DATA22_MARK, VI4_DATA23_MARK,
3592};
3593
3594static const unsigned int vin4_data_a_pins[] = {
3595 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3596 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3597 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3598 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3599 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3600 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3601 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3602 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3603 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3604 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3605 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3606 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3607};
3608
3609static const unsigned int vin4_data_a_mux[] = {
3610 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3611 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3612 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3613 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3614 VI4_DATA8_MARK, VI4_DATA9_MARK,
3615 VI4_DATA10_MARK, VI4_DATA11_MARK,
3616 VI4_DATA12_MARK, VI4_DATA13_MARK,
3617 VI4_DATA14_MARK, VI4_DATA15_MARK,
3618 VI4_DATA16_MARK, VI4_DATA17_MARK,
3619 VI4_DATA18_MARK, VI4_DATA19_MARK,
3620 VI4_DATA20_MARK, VI4_DATA21_MARK,
3621 VI4_DATA22_MARK, VI4_DATA23_MARK,
3622};
3623
3624static const unsigned int vin4_data18_b_pins[] = {
3625 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3626 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3627 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3628 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3629 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3630 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3631 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3632 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3633 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3634};
3635
3636static const unsigned int vin4_data18_b_mux[] = {
3637 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3638 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3639 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3640 VI4_DATA10_MARK, VI4_DATA11_MARK,
3641 VI4_DATA12_MARK, VI4_DATA13_MARK,
3642 VI4_DATA14_MARK, VI4_DATA15_MARK,
3643 VI4_DATA18_MARK, VI4_DATA19_MARK,
3644 VI4_DATA20_MARK, VI4_DATA21_MARK,
3645 VI4_DATA22_MARK, VI4_DATA23_MARK,
3646};
3647
3648static const unsigned int vin4_data_b_pins[] = {
3649 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3650 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3651 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3652 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3653 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3654 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3655 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3656 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3657 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3658 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3659 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3660 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3661};
3662
3663static const unsigned int vin4_data_b_mux[] = {
3664 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3665 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3666 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3667 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3668 VI4_DATA8_MARK, VI4_DATA9_MARK,
3669 VI4_DATA10_MARK, VI4_DATA11_MARK,
3670 VI4_DATA12_MARK, VI4_DATA13_MARK,
3671 VI4_DATA14_MARK, VI4_DATA15_MARK,
3672 VI4_DATA16_MARK, VI4_DATA17_MARK,
3673 VI4_DATA18_MARK, VI4_DATA19_MARK,
3674 VI4_DATA20_MARK, VI4_DATA21_MARK,
3675 VI4_DATA22_MARK, VI4_DATA23_MARK,
3676};
3677
3678static const unsigned int vin4_sync_pins[] = {
3679
3680 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3681};
3682
3683static const unsigned int vin4_sync_mux[] = {
3684 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3685};
3686
3687static const unsigned int vin4_field_pins[] = {
3688 RCAR_GP_PIN(2, 23),
3689};
3690
3691static const unsigned int vin4_field_mux[] = {
3692 VI4_FIELD_MARK,
3693};
3694
3695static const unsigned int vin4_clkenb_pins[] = {
3696 RCAR_GP_PIN(1, 2),
3697};
3698
3699static const unsigned int vin4_clkenb_mux[] = {
3700 VI4_CLKENB_MARK,
3701};
3702
3703static const unsigned int vin4_clk_pins[] = {
3704 RCAR_GP_PIN(2, 22),
3705};
3706
3707static const unsigned int vin4_clk_mux[] = {
3708 VI4_CLK_MARK,
3709};
3710
3711
3712static const unsigned int vin5_data_a_pins[] = {
3713 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3714 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3715 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3716 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3717 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3718 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3719 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3720 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3721};
3722
3723static const unsigned int vin5_data_a_mux[] = {
3724 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3725 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3726 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3727 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3728 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3729 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3730 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3731 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3732};
3733
3734static const unsigned int vin5_data8_b_pins[] = {
3735 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3736 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3737 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3738 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3739};
3740
3741static const unsigned int vin5_data8_b_mux[] = {
3742 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3743 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3744 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3745 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3746};
3747
3748static const unsigned int vin5_sync_a_pins[] = {
3749
3750 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3751};
3752
3753static const unsigned int vin5_sync_a_mux[] = {
3754 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3755};
3756
3757static const unsigned int vin5_field_a_pins[] = {
3758 RCAR_GP_PIN(1, 10),
3759};
3760
3761static const unsigned int vin5_field_a_mux[] = {
3762 VI5_FIELD_A_MARK,
3763};
3764
3765static const unsigned int vin5_clkenb_a_pins[] = {
3766 RCAR_GP_PIN(0, 1),
3767};
3768
3769static const unsigned int vin5_clkenb_a_mux[] = {
3770 VI5_CLKENB_A_MARK,
3771};
3772
3773static const unsigned int vin5_clk_a_pins[] = {
3774 RCAR_GP_PIN(1, 0),
3775};
3776
3777static const unsigned int vin5_clk_a_mux[] = {
3778 VI5_CLK_A_MARK,
3779};
3780
3781static const unsigned int vin5_clk_b_pins[] = {
3782 RCAR_GP_PIN(2, 22),
3783};
3784
3785static const unsigned int vin5_clk_b_mux[] = {
3786 VI5_CLK_B_MARK,
3787};
3788
3789static const struct {
3790 struct sh_pfc_pin_group common[261];
3791#ifdef CONFIG_PINCTRL_PFC_R8A77990
3792 struct sh_pfc_pin_group automotive[22];
3793#endif
3794} pinmux_groups = {
3795 .common = {
3796 SH_PFC_PIN_GROUP(audio_clk_a),
3797 SH_PFC_PIN_GROUP(audio_clk_b_a),
3798 SH_PFC_PIN_GROUP(audio_clk_b_b),
3799 SH_PFC_PIN_GROUP(audio_clk_b_c),
3800 SH_PFC_PIN_GROUP(audio_clk_c_a),
3801 SH_PFC_PIN_GROUP(audio_clk_c_b),
3802 SH_PFC_PIN_GROUP(audio_clk_c_c),
3803 SH_PFC_PIN_GROUP(audio_clkout_a),
3804 SH_PFC_PIN_GROUP(audio_clkout_b),
3805 SH_PFC_PIN_GROUP(audio_clkout1_a),
3806 SH_PFC_PIN_GROUP(audio_clkout1_b),
3807 SH_PFC_PIN_GROUP(audio_clkout1_c),
3808 SH_PFC_PIN_GROUP(audio_clkout2_a),
3809 SH_PFC_PIN_GROUP(audio_clkout2_b),
3810 SH_PFC_PIN_GROUP(audio_clkout2_c),
3811 SH_PFC_PIN_GROUP(audio_clkout3_a),
3812 SH_PFC_PIN_GROUP(audio_clkout3_b),
3813 SH_PFC_PIN_GROUP(audio_clkout3_c),
3814 SH_PFC_PIN_GROUP(avb_link),
3815 SH_PFC_PIN_GROUP(avb_magic),
3816 SH_PFC_PIN_GROUP(avb_phy_int),
3817 SH_PFC_PIN_GROUP(avb_mii),
3818 SH_PFC_PIN_GROUP(avb_avtp_pps),
3819 SH_PFC_PIN_GROUP(avb_avtp_match),
3820 SH_PFC_PIN_GROUP(avb_avtp_capture),
3821 SH_PFC_PIN_GROUP(can0_data),
3822 SH_PFC_PIN_GROUP(can1_data),
3823 SH_PFC_PIN_GROUP(can_clk),
3824 SH_PFC_PIN_GROUP(canfd0_data),
3825 SH_PFC_PIN_GROUP(canfd1_data),
3826 SH_PFC_PIN_GROUP(du_rgb666),
3827 SH_PFC_PIN_GROUP(du_rgb888),
3828 SH_PFC_PIN_GROUP(du_clk_in_0),
3829 SH_PFC_PIN_GROUP(du_clk_in_1),
3830 SH_PFC_PIN_GROUP(du_clk_out_0),
3831 SH_PFC_PIN_GROUP(du_sync),
3832 SH_PFC_PIN_GROUP(du_disp_cde),
3833 SH_PFC_PIN_GROUP(du_cde),
3834 SH_PFC_PIN_GROUP(du_disp),
3835 SH_PFC_PIN_GROUP(hscif0_data_a),
3836 SH_PFC_PIN_GROUP(hscif0_clk_a),
3837 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3838 SH_PFC_PIN_GROUP(hscif0_data_b),
3839 SH_PFC_PIN_GROUP(hscif0_clk_b),
3840 SH_PFC_PIN_GROUP(hscif1_data_a),
3841 SH_PFC_PIN_GROUP(hscif1_clk_a),
3842 SH_PFC_PIN_GROUP(hscif1_data_b),
3843 SH_PFC_PIN_GROUP(hscif1_clk_b),
3844 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3845 SH_PFC_PIN_GROUP(hscif2_data_a),
3846 SH_PFC_PIN_GROUP(hscif2_clk_a),
3847 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3848 SH_PFC_PIN_GROUP(hscif2_data_b),
3849 SH_PFC_PIN_GROUP(hscif3_data_a),
3850 SH_PFC_PIN_GROUP(hscif3_data_b),
3851 SH_PFC_PIN_GROUP(hscif3_clk_b),
3852 SH_PFC_PIN_GROUP(hscif3_data_c),
3853 SH_PFC_PIN_GROUP(hscif3_clk_c),
3854 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3855 SH_PFC_PIN_GROUP(hscif3_data_d),
3856 SH_PFC_PIN_GROUP(hscif3_data_e),
3857 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3858 SH_PFC_PIN_GROUP(hscif4_data_a),
3859 SH_PFC_PIN_GROUP(hscif4_clk_a),
3860 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3861 SH_PFC_PIN_GROUP(hscif4_data_b),
3862 SH_PFC_PIN_GROUP(hscif4_clk_b),
3863 SH_PFC_PIN_GROUP(hscif4_data_c),
3864 SH_PFC_PIN_GROUP(hscif4_data_d),
3865 SH_PFC_PIN_GROUP(hscif4_data_e),
3866 SH_PFC_PIN_GROUP(i2c1_a),
3867 SH_PFC_PIN_GROUP(i2c1_b),
3868 SH_PFC_PIN_GROUP(i2c1_c),
3869 SH_PFC_PIN_GROUP(i2c1_d),
3870 SH_PFC_PIN_GROUP(i2c2_a),
3871 SH_PFC_PIN_GROUP(i2c2_b),
3872 SH_PFC_PIN_GROUP(i2c2_c),
3873 SH_PFC_PIN_GROUP(i2c2_d),
3874 SH_PFC_PIN_GROUP(i2c2_e),
3875 SH_PFC_PIN_GROUP(i2c4),
3876 SH_PFC_PIN_GROUP(i2c5),
3877 SH_PFC_PIN_GROUP(i2c6_a),
3878 SH_PFC_PIN_GROUP(i2c6_b),
3879 SH_PFC_PIN_GROUP(i2c7_a),
3880 SH_PFC_PIN_GROUP(i2c7_b),
3881 SH_PFC_PIN_GROUP(intc_ex_irq0),
3882 SH_PFC_PIN_GROUP(intc_ex_irq1),
3883 SH_PFC_PIN_GROUP(intc_ex_irq2),
3884 SH_PFC_PIN_GROUP(intc_ex_irq3),
3885 SH_PFC_PIN_GROUP(intc_ex_irq4),
3886 SH_PFC_PIN_GROUP(intc_ex_irq5),
3887 SH_PFC_PIN_GROUP(msiof0_clk),
3888 SH_PFC_PIN_GROUP(msiof0_sync),
3889 SH_PFC_PIN_GROUP(msiof0_ss1),
3890 SH_PFC_PIN_GROUP(msiof0_ss2),
3891 SH_PFC_PIN_GROUP(msiof0_txd),
3892 SH_PFC_PIN_GROUP(msiof0_rxd),
3893 SH_PFC_PIN_GROUP(msiof1_clk),
3894 SH_PFC_PIN_GROUP(msiof1_sync),
3895 SH_PFC_PIN_GROUP(msiof1_ss1),
3896 SH_PFC_PIN_GROUP(msiof1_ss2),
3897 SH_PFC_PIN_GROUP(msiof1_txd),
3898 SH_PFC_PIN_GROUP(msiof1_rxd),
3899 SH_PFC_PIN_GROUP(msiof2_clk_a),
3900 SH_PFC_PIN_GROUP(msiof2_sync_a),
3901 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3902 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3903 SH_PFC_PIN_GROUP(msiof2_txd_a),
3904 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3905 SH_PFC_PIN_GROUP(msiof2_clk_b),
3906 SH_PFC_PIN_GROUP(msiof2_sync_b),
3907 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3908 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3909 SH_PFC_PIN_GROUP(msiof2_txd_b),
3910 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3911 SH_PFC_PIN_GROUP(msiof3_clk_a),
3912 SH_PFC_PIN_GROUP(msiof3_sync_a),
3913 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3914 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3915 SH_PFC_PIN_GROUP(msiof3_txd_a),
3916 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3917 SH_PFC_PIN_GROUP(msiof3_clk_b),
3918 SH_PFC_PIN_GROUP(msiof3_sync_b),
3919 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3920 SH_PFC_PIN_GROUP(msiof3_txd_b),
3921 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3922 SH_PFC_PIN_GROUP(pwm0_a),
3923 SH_PFC_PIN_GROUP(pwm0_b),
3924 SH_PFC_PIN_GROUP(pwm1_a),
3925 SH_PFC_PIN_GROUP(pwm1_b),
3926 SH_PFC_PIN_GROUP(pwm2_a),
3927 SH_PFC_PIN_GROUP(pwm2_b),
3928 SH_PFC_PIN_GROUP(pwm2_c),
3929 SH_PFC_PIN_GROUP(pwm3_a),
3930 SH_PFC_PIN_GROUP(pwm3_b),
3931 SH_PFC_PIN_GROUP(pwm3_c),
3932 SH_PFC_PIN_GROUP(pwm4_a),
3933 SH_PFC_PIN_GROUP(pwm4_b),
3934 SH_PFC_PIN_GROUP(pwm5_a),
3935 SH_PFC_PIN_GROUP(pwm5_b),
3936 SH_PFC_PIN_GROUP(pwm6_a),
3937 SH_PFC_PIN_GROUP(pwm6_b),
3938 SH_PFC_PIN_GROUP(qspi0_ctrl),
3939 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
3940 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
3941 SH_PFC_PIN_GROUP(qspi1_ctrl),
3942 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
3943 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
3944 BUS_DATA_PIN_GROUP(rpc_clk, 1),
3945 BUS_DATA_PIN_GROUP(rpc_clk, 2),
3946 SH_PFC_PIN_GROUP(rpc_ctrl),
3947 SH_PFC_PIN_GROUP(rpc_data),
3948 SH_PFC_PIN_GROUP(rpc_reset),
3949 SH_PFC_PIN_GROUP(rpc_int),
3950 SH_PFC_PIN_GROUP(scif0_data_a),
3951 SH_PFC_PIN_GROUP(scif0_clk_a),
3952 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3953 SH_PFC_PIN_GROUP(scif0_data_b),
3954 SH_PFC_PIN_GROUP(scif0_clk_b),
3955 SH_PFC_PIN_GROUP(scif1_data),
3956 SH_PFC_PIN_GROUP(scif1_clk),
3957 SH_PFC_PIN_GROUP(scif1_ctrl),
3958 SH_PFC_PIN_GROUP(scif2_data_a),
3959 SH_PFC_PIN_GROUP(scif2_clk_a),
3960 SH_PFC_PIN_GROUP(scif2_data_b),
3961 SH_PFC_PIN_GROUP(scif3_data_a),
3962 SH_PFC_PIN_GROUP(scif3_clk_a),
3963 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3964 SH_PFC_PIN_GROUP(scif3_data_b),
3965 SH_PFC_PIN_GROUP(scif3_data_c),
3966 SH_PFC_PIN_GROUP(scif3_clk_c),
3967 SH_PFC_PIN_GROUP(scif4_data_a),
3968 SH_PFC_PIN_GROUP(scif4_clk_a),
3969 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3970 SH_PFC_PIN_GROUP(scif4_data_b),
3971 SH_PFC_PIN_GROUP(scif4_clk_b),
3972 SH_PFC_PIN_GROUP(scif4_data_c),
3973 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3974 SH_PFC_PIN_GROUP(scif5_data_a),
3975 SH_PFC_PIN_GROUP(scif5_clk_a),
3976 SH_PFC_PIN_GROUP(scif5_data_b),
3977 SH_PFC_PIN_GROUP(scif5_data_c),
3978 SH_PFC_PIN_GROUP(scif_clk_a),
3979 SH_PFC_PIN_GROUP(scif_clk_b),
3980 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
3981 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
3982 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3983 SH_PFC_PIN_GROUP(sdhi0_cd),
3984 SH_PFC_PIN_GROUP(sdhi0_wp),
3985 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
3986 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
3987 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3988 SH_PFC_PIN_GROUP(sdhi1_cd),
3989 SH_PFC_PIN_GROUP(sdhi1_wp),
3990 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
3991 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
3992 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
3993 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3994 SH_PFC_PIN_GROUP(sdhi3_cd),
3995 SH_PFC_PIN_GROUP(sdhi3_wp),
3996 SH_PFC_PIN_GROUP(sdhi3_ds),
3997 SH_PFC_PIN_GROUP(ssi0_data),
3998 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3999 SH_PFC_PIN_GROUP(ssi1_data),
4000 SH_PFC_PIN_GROUP(ssi1_ctrl),
4001 SH_PFC_PIN_GROUP(ssi2_data),
4002 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4003 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4004 SH_PFC_PIN_GROUP(ssi3_data),
4005 SH_PFC_PIN_GROUP(ssi349_ctrl),
4006 SH_PFC_PIN_GROUP(ssi4_data),
4007 SH_PFC_PIN_GROUP(ssi4_ctrl),
4008 SH_PFC_PIN_GROUP(ssi5_data),
4009 SH_PFC_PIN_GROUP(ssi5_ctrl),
4010 SH_PFC_PIN_GROUP(ssi6_data),
4011 SH_PFC_PIN_GROUP(ssi6_ctrl),
4012 SH_PFC_PIN_GROUP(ssi7_data),
4013 SH_PFC_PIN_GROUP(ssi78_ctrl),
4014 SH_PFC_PIN_GROUP(ssi8_data),
4015 SH_PFC_PIN_GROUP(ssi9_data),
4016 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4017 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4018 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4019 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4020 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4021 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4022 SH_PFC_PIN_GROUP(usb0_a),
4023 SH_PFC_PIN_GROUP(usb0_b),
4024 SH_PFC_PIN_GROUP(usb0_id),
4025 SH_PFC_PIN_GROUP(usb30),
4026 SH_PFC_PIN_GROUP(usb30_id),
4027 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4028 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4029 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4030 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4031 SH_PFC_PIN_GROUP(vin4_data18_a),
4032 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4033 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4034 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4035 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4036 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4037 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4038 SH_PFC_PIN_GROUP(vin4_data18_b),
4039 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4040 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4041 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4042 SH_PFC_PIN_GROUP(vin4_sync),
4043 SH_PFC_PIN_GROUP(vin4_field),
4044 SH_PFC_PIN_GROUP(vin4_clkenb),
4045 SH_PFC_PIN_GROUP(vin4_clk),
4046 BUS_DATA_PIN_GROUP(vin5_data, 8, _a),
4047 BUS_DATA_PIN_GROUP(vin5_data, 10, _a),
4048 BUS_DATA_PIN_GROUP(vin5_data, 12, _a),
4049 BUS_DATA_PIN_GROUP(vin5_data, 16, _a),
4050 SH_PFC_PIN_GROUP(vin5_data8_b),
4051 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8),
4052 SH_PFC_PIN_GROUP(vin5_sync_a),
4053 SH_PFC_PIN_GROUP(vin5_field_a),
4054 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4055 SH_PFC_PIN_GROUP(vin5_clk_a),
4056 SH_PFC_PIN_GROUP(vin5_clk_b),
4057 },
4058#ifdef CONFIG_PINCTRL_PFC_R8A77990
4059 .automotive = {
4060 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4061 SH_PFC_PIN_GROUP(drif0_data0_a),
4062 SH_PFC_PIN_GROUP(drif0_data1_a),
4063 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4064 SH_PFC_PIN_GROUP(drif0_data0_b),
4065 SH_PFC_PIN_GROUP(drif0_data1_b),
4066 SH_PFC_PIN_GROUP(drif1_ctrl),
4067 SH_PFC_PIN_GROUP(drif1_data0),
4068 SH_PFC_PIN_GROUP(drif1_data1),
4069 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4070 SH_PFC_PIN_GROUP(drif2_data0_a),
4071 SH_PFC_PIN_GROUP(drif2_data1_a),
4072 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4073 SH_PFC_PIN_GROUP(drif2_data0_b),
4074 SH_PFC_PIN_GROUP(drif2_data1_b),
4075 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4076 SH_PFC_PIN_GROUP(drif3_data0_a),
4077 SH_PFC_PIN_GROUP(drif3_data1_a),
4078 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4079 SH_PFC_PIN_GROUP(drif3_data0_b),
4080 SH_PFC_PIN_GROUP(drif3_data1_b),
4081 SH_PFC_PIN_GROUP(mlb_3pin),
4082 }
4083#endif
4084};
4085
4086static const char * const audio_clk_groups[] = {
4087 "audio_clk_a",
4088 "audio_clk_b_a",
4089 "audio_clk_b_b",
4090 "audio_clk_b_c",
4091 "audio_clk_c_a",
4092 "audio_clk_c_b",
4093 "audio_clk_c_c",
4094 "audio_clkout_a",
4095 "audio_clkout_b",
4096 "audio_clkout1_a",
4097 "audio_clkout1_b",
4098 "audio_clkout1_c",
4099 "audio_clkout2_a",
4100 "audio_clkout2_b",
4101 "audio_clkout2_c",
4102 "audio_clkout3_a",
4103 "audio_clkout3_b",
4104 "audio_clkout3_c",
4105};
4106
4107static const char * const avb_groups[] = {
4108 "avb_link",
4109 "avb_magic",
4110 "avb_phy_int",
4111 "avb_mii",
4112 "avb_avtp_pps",
4113 "avb_avtp_match",
4114 "avb_avtp_capture",
4115};
4116
4117static const char * const can0_groups[] = {
4118 "can0_data",
4119};
4120
4121static const char * const can1_groups[] = {
4122 "can1_data",
4123};
4124
4125static const char * const can_clk_groups[] = {
4126 "can_clk",
4127};
4128
4129static const char * const canfd0_groups[] = {
4130 "canfd0_data",
4131};
4132
4133static const char * const canfd1_groups[] = {
4134 "canfd1_data",
4135};
4136
4137#ifdef CONFIG_PINCTRL_PFC_R8A77990
4138static const char * const drif0_groups[] = {
4139 "drif0_ctrl_a",
4140 "drif0_data0_a",
4141 "drif0_data1_a",
4142 "drif0_ctrl_b",
4143 "drif0_data0_b",
4144 "drif0_data1_b",
4145};
4146
4147static const char * const drif1_groups[] = {
4148 "drif1_ctrl",
4149 "drif1_data0",
4150 "drif1_data1",
4151};
4152
4153static const char * const drif2_groups[] = {
4154 "drif2_ctrl_a",
4155 "drif2_data0_a",
4156 "drif2_data1_a",
4157 "drif2_ctrl_b",
4158 "drif2_data0_b",
4159 "drif2_data1_b",
4160};
4161
4162static const char * const drif3_groups[] = {
4163 "drif3_ctrl_a",
4164 "drif3_data0_a",
4165 "drif3_data1_a",
4166 "drif3_ctrl_b",
4167 "drif3_data0_b",
4168 "drif3_data1_b",
4169};
4170#endif
4171
4172static const char * const du_groups[] = {
4173 "du_rgb666",
4174 "du_rgb888",
4175 "du_clk_in_0",
4176 "du_clk_in_1",
4177 "du_clk_out_0",
4178 "du_sync",
4179 "du_disp_cde",
4180 "du_cde",
4181 "du_disp",
4182};
4183
4184static const char * const hscif0_groups[] = {
4185 "hscif0_data_a",
4186 "hscif0_clk_a",
4187 "hscif0_ctrl_a",
4188 "hscif0_data_b",
4189 "hscif0_clk_b",
4190};
4191
4192static const char * const hscif1_groups[] = {
4193 "hscif1_data_a",
4194 "hscif1_clk_a",
4195 "hscif1_data_b",
4196 "hscif1_clk_b",
4197 "hscif1_ctrl_b",
4198};
4199
4200static const char * const hscif2_groups[] = {
4201 "hscif2_data_a",
4202 "hscif2_clk_a",
4203 "hscif2_ctrl_a",
4204 "hscif2_data_b",
4205};
4206
4207static const char * const hscif3_groups[] = {
4208 "hscif3_data_a",
4209 "hscif3_data_b",
4210 "hscif3_clk_b",
4211 "hscif3_data_c",
4212 "hscif3_clk_c",
4213 "hscif3_ctrl_c",
4214 "hscif3_data_d",
4215 "hscif3_data_e",
4216 "hscif3_ctrl_e",
4217};
4218
4219static const char * const hscif4_groups[] = {
4220 "hscif4_data_a",
4221 "hscif4_clk_a",
4222 "hscif4_ctrl_a",
4223 "hscif4_data_b",
4224 "hscif4_clk_b",
4225 "hscif4_data_c",
4226 "hscif4_data_d",
4227 "hscif4_data_e",
4228};
4229
4230static const char * const i2c1_groups[] = {
4231 "i2c1_a",
4232 "i2c1_b",
4233 "i2c1_c",
4234 "i2c1_d",
4235};
4236
4237static const char * const i2c2_groups[] = {
4238 "i2c2_a",
4239 "i2c2_b",
4240 "i2c2_c",
4241 "i2c2_d",
4242 "i2c2_e",
4243};
4244
4245static const char * const i2c4_groups[] = {
4246 "i2c4",
4247};
4248
4249static const char * const i2c5_groups[] = {
4250 "i2c5",
4251};
4252
4253static const char * const i2c6_groups[] = {
4254 "i2c6_a",
4255 "i2c6_b",
4256};
4257
4258static const char * const i2c7_groups[] = {
4259 "i2c7_a",
4260 "i2c7_b",
4261};
4262
4263static const char * const intc_ex_groups[] = {
4264 "intc_ex_irq0",
4265 "intc_ex_irq1",
4266 "intc_ex_irq2",
4267 "intc_ex_irq3",
4268 "intc_ex_irq4",
4269 "intc_ex_irq5",
4270};
4271
4272#ifdef CONFIG_PINCTRL_PFC_R8A77990
4273static const char * const mlb_3pin_groups[] = {
4274 "mlb_3pin",
4275};
4276#endif
4277
4278static const char * const msiof0_groups[] = {
4279 "msiof0_clk",
4280 "msiof0_sync",
4281 "msiof0_ss1",
4282 "msiof0_ss2",
4283 "msiof0_txd",
4284 "msiof0_rxd",
4285};
4286
4287static const char * const msiof1_groups[] = {
4288 "msiof1_clk",
4289 "msiof1_sync",
4290 "msiof1_ss1",
4291 "msiof1_ss2",
4292 "msiof1_txd",
4293 "msiof1_rxd",
4294};
4295
4296static const char * const msiof2_groups[] = {
4297 "msiof2_clk_a",
4298 "msiof2_sync_a",
4299 "msiof2_ss1_a",
4300 "msiof2_ss2_a",
4301 "msiof2_txd_a",
4302 "msiof2_rxd_a",
4303 "msiof2_clk_b",
4304 "msiof2_sync_b",
4305 "msiof2_ss1_b",
4306 "msiof2_ss2_b",
4307 "msiof2_txd_b",
4308 "msiof2_rxd_b",
4309};
4310
4311static const char * const msiof3_groups[] = {
4312 "msiof3_clk_a",
4313 "msiof3_sync_a",
4314 "msiof3_ss1_a",
4315 "msiof3_ss2_a",
4316 "msiof3_txd_a",
4317 "msiof3_rxd_a",
4318 "msiof3_clk_b",
4319 "msiof3_sync_b",
4320 "msiof3_ss1_b",
4321 "msiof3_txd_b",
4322 "msiof3_rxd_b",
4323};
4324
4325static const char * const pwm0_groups[] = {
4326 "pwm0_a",
4327 "pwm0_b",
4328};
4329
4330static const char * const pwm1_groups[] = {
4331 "pwm1_a",
4332 "pwm1_b",
4333};
4334
4335static const char * const pwm2_groups[] = {
4336 "pwm2_a",
4337 "pwm2_b",
4338 "pwm2_c",
4339};
4340
4341static const char * const pwm3_groups[] = {
4342 "pwm3_a",
4343 "pwm3_b",
4344 "pwm3_c",
4345};
4346
4347static const char * const pwm4_groups[] = {
4348 "pwm4_a",
4349 "pwm4_b",
4350};
4351
4352static const char * const pwm5_groups[] = {
4353 "pwm5_a",
4354 "pwm5_b",
4355};
4356
4357static const char * const pwm6_groups[] = {
4358 "pwm6_a",
4359 "pwm6_b",
4360};
4361
4362static const char * const qspi0_groups[] = {
4363 "qspi0_ctrl",
4364 "qspi0_data2",
4365 "qspi0_data4",
4366};
4367
4368static const char * const qspi1_groups[] = {
4369 "qspi1_ctrl",
4370 "qspi1_data2",
4371 "qspi1_data4",
4372};
4373
4374static const char * const rpc_groups[] = {
4375 "rpc_clk1",
4376 "rpc_clk2",
4377 "rpc_ctrl",
4378 "rpc_data",
4379 "rpc_reset",
4380 "rpc_int",
4381};
4382
4383static const char * const scif0_groups[] = {
4384 "scif0_data_a",
4385 "scif0_clk_a",
4386 "scif0_ctrl_a",
4387 "scif0_data_b",
4388 "scif0_clk_b",
4389};
4390
4391static const char * const scif1_groups[] = {
4392 "scif1_data",
4393 "scif1_clk",
4394 "scif1_ctrl",
4395};
4396
4397static const char * const scif2_groups[] = {
4398 "scif2_data_a",
4399 "scif2_clk_a",
4400 "scif2_data_b",
4401};
4402
4403static const char * const scif3_groups[] = {
4404 "scif3_data_a",
4405 "scif3_clk_a",
4406 "scif3_ctrl_a",
4407 "scif3_data_b",
4408 "scif3_data_c",
4409 "scif3_clk_c",
4410};
4411
4412static const char * const scif4_groups[] = {
4413 "scif4_data_a",
4414 "scif4_clk_a",
4415 "scif4_ctrl_a",
4416 "scif4_data_b",
4417 "scif4_clk_b",
4418 "scif4_data_c",
4419 "scif4_ctrl_c",
4420};
4421
4422static const char * const scif5_groups[] = {
4423 "scif5_data_a",
4424 "scif5_clk_a",
4425 "scif5_data_b",
4426 "scif5_data_c",
4427};
4428
4429static const char * const scif_clk_groups[] = {
4430 "scif_clk_a",
4431 "scif_clk_b",
4432};
4433
4434static const char * const sdhi0_groups[] = {
4435 "sdhi0_data1",
4436 "sdhi0_data4",
4437 "sdhi0_ctrl",
4438 "sdhi0_cd",
4439 "sdhi0_wp",
4440};
4441
4442static const char * const sdhi1_groups[] = {
4443 "sdhi1_data1",
4444 "sdhi1_data4",
4445 "sdhi1_ctrl",
4446 "sdhi1_cd",
4447 "sdhi1_wp",
4448};
4449
4450static const char * const sdhi3_groups[] = {
4451 "sdhi3_data1",
4452 "sdhi3_data4",
4453 "sdhi3_data8",
4454 "sdhi3_ctrl",
4455 "sdhi3_cd",
4456 "sdhi3_wp",
4457 "sdhi3_ds",
4458};
4459
4460static const char * const ssi_groups[] = {
4461 "ssi0_data",
4462 "ssi01239_ctrl",
4463 "ssi1_data",
4464 "ssi1_ctrl",
4465 "ssi2_data",
4466 "ssi2_ctrl_a",
4467 "ssi2_ctrl_b",
4468 "ssi3_data",
4469 "ssi349_ctrl",
4470 "ssi4_data",
4471 "ssi4_ctrl",
4472 "ssi5_data",
4473 "ssi5_ctrl",
4474 "ssi6_data",
4475 "ssi6_ctrl",
4476 "ssi7_data",
4477 "ssi78_ctrl",
4478 "ssi8_data",
4479 "ssi9_data",
4480 "ssi9_ctrl_a",
4481 "ssi9_ctrl_b",
4482};
4483
4484static const char * const tmu_groups[] = {
4485 "tmu_tclk1_a",
4486 "tmu_tclk1_b",
4487 "tmu_tclk2_a",
4488 "tmu_tclk2_b",
4489};
4490
4491static const char * const usb0_groups[] = {
4492 "usb0_a",
4493 "usb0_b",
4494 "usb0_id",
4495};
4496
4497static const char * const usb30_groups[] = {
4498 "usb30",
4499 "usb30_id",
4500};
4501
4502static const char * const vin4_groups[] = {
4503 "vin4_data8_a",
4504 "vin4_data10_a",
4505 "vin4_data12_a",
4506 "vin4_data16_a",
4507 "vin4_data18_a",
4508 "vin4_data20_a",
4509 "vin4_data24_a",
4510 "vin4_data8_b",
4511 "vin4_data10_b",
4512 "vin4_data12_b",
4513 "vin4_data16_b",
4514 "vin4_data18_b",
4515 "vin4_data20_b",
4516 "vin4_data24_b",
4517 "vin4_g8",
4518 "vin4_sync",
4519 "vin4_field",
4520 "vin4_clkenb",
4521 "vin4_clk",
4522};
4523
4524static const char * const vin5_groups[] = {
4525 "vin5_data8_a",
4526 "vin5_data10_a",
4527 "vin5_data12_a",
4528 "vin5_data16_a",
4529 "vin5_data8_b",
4530 "vin5_high8",
4531 "vin5_sync_a",
4532 "vin5_field_a",
4533 "vin5_clkenb_a",
4534 "vin5_clk_a",
4535 "vin5_clk_b",
4536};
4537
4538static const struct {
4539 struct sh_pfc_function common[50];
4540#ifdef CONFIG_PINCTRL_PFC_R8A77990
4541 struct sh_pfc_function automotive[5];
4542#endif
4543} pinmux_functions = {
4544 .common = {
4545 SH_PFC_FUNCTION(audio_clk),
4546 SH_PFC_FUNCTION(avb),
4547 SH_PFC_FUNCTION(can0),
4548 SH_PFC_FUNCTION(can1),
4549 SH_PFC_FUNCTION(can_clk),
4550 SH_PFC_FUNCTION(canfd0),
4551 SH_PFC_FUNCTION(canfd1),
4552 SH_PFC_FUNCTION(du),
4553 SH_PFC_FUNCTION(hscif0),
4554 SH_PFC_FUNCTION(hscif1),
4555 SH_PFC_FUNCTION(hscif2),
4556 SH_PFC_FUNCTION(hscif3),
4557 SH_PFC_FUNCTION(hscif4),
4558 SH_PFC_FUNCTION(i2c1),
4559 SH_PFC_FUNCTION(i2c2),
4560 SH_PFC_FUNCTION(i2c4),
4561 SH_PFC_FUNCTION(i2c5),
4562 SH_PFC_FUNCTION(i2c6),
4563 SH_PFC_FUNCTION(i2c7),
4564 SH_PFC_FUNCTION(intc_ex),
4565 SH_PFC_FUNCTION(msiof0),
4566 SH_PFC_FUNCTION(msiof1),
4567 SH_PFC_FUNCTION(msiof2),
4568 SH_PFC_FUNCTION(msiof3),
4569 SH_PFC_FUNCTION(pwm0),
4570 SH_PFC_FUNCTION(pwm1),
4571 SH_PFC_FUNCTION(pwm2),
4572 SH_PFC_FUNCTION(pwm3),
4573 SH_PFC_FUNCTION(pwm4),
4574 SH_PFC_FUNCTION(pwm5),
4575 SH_PFC_FUNCTION(pwm6),
4576 SH_PFC_FUNCTION(qspi0),
4577 SH_PFC_FUNCTION(qspi1),
4578 SH_PFC_FUNCTION(rpc),
4579 SH_PFC_FUNCTION(scif0),
4580 SH_PFC_FUNCTION(scif1),
4581 SH_PFC_FUNCTION(scif2),
4582 SH_PFC_FUNCTION(scif3),
4583 SH_PFC_FUNCTION(scif4),
4584 SH_PFC_FUNCTION(scif5),
4585 SH_PFC_FUNCTION(scif_clk),
4586 SH_PFC_FUNCTION(sdhi0),
4587 SH_PFC_FUNCTION(sdhi1),
4588 SH_PFC_FUNCTION(sdhi3),
4589 SH_PFC_FUNCTION(ssi),
4590 SH_PFC_FUNCTION(tmu),
4591 SH_PFC_FUNCTION(usb0),
4592 SH_PFC_FUNCTION(usb30),
4593 SH_PFC_FUNCTION(vin4),
4594 SH_PFC_FUNCTION(vin5),
4595 },
4596#ifdef CONFIG_PINCTRL_PFC_R8A77990
4597 .automotive = {
4598 SH_PFC_FUNCTION(drif0),
4599 SH_PFC_FUNCTION(drif1),
4600 SH_PFC_FUNCTION(drif2),
4601 SH_PFC_FUNCTION(drif3),
4602 SH_PFC_FUNCTION(mlb_3pin),
4603 }
4604#endif
4605};
4606
4607static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4608#define F_(x, y) FN_##y
4609#define FM(x) FN_##x
4610 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
4611 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4612 1, 1, 1, 1, 1, 1, 1),
4613 GROUP(
4614
4615 GP_0_17_FN, GPSR0_17,
4616 GP_0_16_FN, GPSR0_16,
4617 GP_0_15_FN, GPSR0_15,
4618 GP_0_14_FN, GPSR0_14,
4619 GP_0_13_FN, GPSR0_13,
4620 GP_0_12_FN, GPSR0_12,
4621 GP_0_11_FN, GPSR0_11,
4622 GP_0_10_FN, GPSR0_10,
4623 GP_0_9_FN, GPSR0_9,
4624 GP_0_8_FN, GPSR0_8,
4625 GP_0_7_FN, GPSR0_7,
4626 GP_0_6_FN, GPSR0_6,
4627 GP_0_5_FN, GPSR0_5,
4628 GP_0_4_FN, GPSR0_4,
4629 GP_0_3_FN, GPSR0_3,
4630 GP_0_2_FN, GPSR0_2,
4631 GP_0_1_FN, GPSR0_1,
4632 GP_0_0_FN, GPSR0_0, ))
4633 },
4634 { PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32,
4635 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4636 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
4637 GROUP(
4638
4639 GP_1_22_FN, GPSR1_22,
4640 GP_1_21_FN, GPSR1_21,
4641 GP_1_20_FN, GPSR1_20,
4642 GP_1_19_FN, GPSR1_19,
4643 GP_1_18_FN, GPSR1_18,
4644 GP_1_17_FN, GPSR1_17,
4645 GP_1_16_FN, GPSR1_16,
4646 GP_1_15_FN, GPSR1_15,
4647 GP_1_14_FN, GPSR1_14,
4648 GP_1_13_FN, GPSR1_13,
4649 GP_1_12_FN, GPSR1_12,
4650 GP_1_11_FN, GPSR1_11,
4651 GP_1_10_FN, GPSR1_10,
4652 GP_1_9_FN, GPSR1_9,
4653 GP_1_8_FN, GPSR1_8,
4654 GP_1_7_FN, GPSR1_7,
4655 GP_1_6_FN, GPSR1_6,
4656 GP_1_5_FN, GPSR1_5,
4657 GP_1_4_FN, GPSR1_4,
4658 GP_1_3_FN, GPSR1_3,
4659 GP_1_2_FN, GPSR1_2,
4660 GP_1_1_FN, GPSR1_1,
4661 GP_1_0_FN, GPSR1_0, ))
4662 },
4663 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4664 0, 0,
4665 0, 0,
4666 0, 0,
4667 0, 0,
4668 0, 0,
4669 0, 0,
4670 GP_2_25_FN, GPSR2_25,
4671 GP_2_24_FN, GPSR2_24,
4672 GP_2_23_FN, GPSR2_23,
4673 GP_2_22_FN, GPSR2_22,
4674 GP_2_21_FN, GPSR2_21,
4675 GP_2_20_FN, GPSR2_20,
4676 GP_2_19_FN, GPSR2_19,
4677 GP_2_18_FN, GPSR2_18,
4678 GP_2_17_FN, GPSR2_17,
4679 GP_2_16_FN, GPSR2_16,
4680 GP_2_15_FN, GPSR2_15,
4681 GP_2_14_FN, GPSR2_14,
4682 GP_2_13_FN, GPSR2_13,
4683 GP_2_12_FN, GPSR2_12,
4684 GP_2_11_FN, GPSR2_11,
4685 GP_2_10_FN, GPSR2_10,
4686 GP_2_9_FN, GPSR2_9,
4687 GP_2_8_FN, GPSR2_8,
4688 GP_2_7_FN, GPSR2_7,
4689 GP_2_6_FN, GPSR2_6,
4690 GP_2_5_FN, GPSR2_5,
4691 GP_2_4_FN, GPSR2_4,
4692 GP_2_3_FN, GPSR2_3,
4693 GP_2_2_FN, GPSR2_2,
4694 GP_2_1_FN, GPSR2_1,
4695 GP_2_0_FN, GPSR2_0, ))
4696 },
4697 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
4698 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4699 1, 1, 1, 1, 1),
4700 GROUP(
4701
4702 GP_3_15_FN, GPSR3_15,
4703 GP_3_14_FN, GPSR3_14,
4704 GP_3_13_FN, GPSR3_13,
4705 GP_3_12_FN, GPSR3_12,
4706 GP_3_11_FN, GPSR3_11,
4707 GP_3_10_FN, GPSR3_10,
4708 GP_3_9_FN, GPSR3_9,
4709 GP_3_8_FN, GPSR3_8,
4710 GP_3_7_FN, GPSR3_7,
4711 GP_3_6_FN, GPSR3_6,
4712 GP_3_5_FN, GPSR3_5,
4713 GP_3_4_FN, GPSR3_4,
4714 GP_3_3_FN, GPSR3_3,
4715 GP_3_2_FN, GPSR3_2,
4716 GP_3_1_FN, GPSR3_1,
4717 GP_3_0_FN, GPSR3_0, ))
4718 },
4719 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
4720 GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
4721 GROUP(
4722
4723 GP_4_10_FN, GPSR4_10,
4724 GP_4_9_FN, GPSR4_9,
4725 GP_4_8_FN, GPSR4_8,
4726 GP_4_7_FN, GPSR4_7,
4727 GP_4_6_FN, GPSR4_6,
4728 GP_4_5_FN, GPSR4_5,
4729 GP_4_4_FN, GPSR4_4,
4730 GP_4_3_FN, GPSR4_3,
4731 GP_4_2_FN, GPSR4_2,
4732 GP_4_1_FN, GPSR4_1,
4733 GP_4_0_FN, GPSR4_0, ))
4734 },
4735 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
4736 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4737 1, 1, 1, 1, 1, 1, 1, 1, 1),
4738 GROUP(
4739
4740 GP_5_19_FN, GPSR5_19,
4741 GP_5_18_FN, GPSR5_18,
4742 GP_5_17_FN, GPSR5_17,
4743 GP_5_16_FN, GPSR5_16,
4744 GP_5_15_FN, GPSR5_15,
4745 GP_5_14_FN, GPSR5_14,
4746 GP_5_13_FN, GPSR5_13,
4747 GP_5_12_FN, GPSR5_12,
4748 GP_5_11_FN, GPSR5_11,
4749 GP_5_10_FN, GPSR5_10,
4750 GP_5_9_FN, GPSR5_9,
4751 GP_5_8_FN, GPSR5_8,
4752 GP_5_7_FN, GPSR5_7,
4753 GP_5_6_FN, GPSR5_6,
4754 GP_5_5_FN, GPSR5_5,
4755 GP_5_4_FN, GPSR5_4,
4756 GP_5_3_FN, GPSR5_3,
4757 GP_5_2_FN, GPSR5_2,
4758 GP_5_1_FN, GPSR5_1,
4759 GP_5_0_FN, GPSR5_0, ))
4760 },
4761 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
4762 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4763 1, 1, 1, 1, 1, 1, 1),
4764 GROUP(
4765
4766 GP_6_17_FN, GPSR6_17,
4767 GP_6_16_FN, GPSR6_16,
4768 GP_6_15_FN, GPSR6_15,
4769 GP_6_14_FN, GPSR6_14,
4770 GP_6_13_FN, GPSR6_13,
4771 GP_6_12_FN, GPSR6_12,
4772 GP_6_11_FN, GPSR6_11,
4773 GP_6_10_FN, GPSR6_10,
4774 GP_6_9_FN, GPSR6_9,
4775 GP_6_8_FN, GPSR6_8,
4776 GP_6_7_FN, GPSR6_7,
4777 GP_6_6_FN, GPSR6_6,
4778 GP_6_5_FN, GPSR6_5,
4779 GP_6_4_FN, GPSR6_4,
4780 GP_6_3_FN, GPSR6_3,
4781 GP_6_2_FN, GPSR6_2,
4782 GP_6_1_FN, GPSR6_1,
4783 GP_6_0_FN, GPSR6_0, ))
4784 },
4785#undef F_
4786#undef FM
4787
4788#define F_(x, y) x,
4789#define FM(x) FN_##x,
4790 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4791 IP0_31_28
4792 IP0_27_24
4793 IP0_23_20
4794 IP0_19_16
4795 IP0_15_12
4796 IP0_11_8
4797 IP0_7_4
4798 IP0_3_0 ))
4799 },
4800 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4801 IP1_31_28
4802 IP1_27_24
4803 IP1_23_20
4804 IP1_19_16
4805 IP1_15_12
4806 IP1_11_8
4807 IP1_7_4
4808 IP1_3_0 ))
4809 },
4810 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4811 IP2_31_28
4812 IP2_27_24
4813 IP2_23_20
4814 IP2_19_16
4815 IP2_15_12
4816 IP2_11_8
4817 IP2_7_4
4818 IP2_3_0 ))
4819 },
4820 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4821 IP3_31_28
4822 IP3_27_24
4823 IP3_23_20
4824 IP3_19_16
4825 IP3_15_12
4826 IP3_11_8
4827 IP3_7_4
4828 IP3_3_0 ))
4829 },
4830 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4831 IP4_31_28
4832 IP4_27_24
4833 IP4_23_20
4834 IP4_19_16
4835 IP4_15_12
4836 IP4_11_8
4837 IP4_7_4
4838 IP4_3_0 ))
4839 },
4840 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4841 IP5_31_28
4842 IP5_27_24
4843 IP5_23_20
4844 IP5_19_16
4845 IP5_15_12
4846 IP5_11_8
4847 IP5_7_4
4848 IP5_3_0 ))
4849 },
4850 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4851 IP6_31_28
4852 IP6_27_24
4853 IP6_23_20
4854 IP6_19_16
4855 IP6_15_12
4856 IP6_11_8
4857 IP6_7_4
4858 IP6_3_0 ))
4859 },
4860 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4861 IP7_31_28
4862 IP7_27_24
4863 IP7_23_20
4864 IP7_19_16
4865 IP7_15_12
4866 IP7_11_8
4867 IP7_7_4
4868 IP7_3_0 ))
4869 },
4870 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4871 IP8_31_28
4872 IP8_27_24
4873 IP8_23_20
4874 IP8_19_16
4875 IP8_15_12
4876 IP8_11_8
4877 IP8_7_4
4878 IP8_3_0 ))
4879 },
4880 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4881 IP9_31_28
4882 IP9_27_24
4883 IP9_23_20
4884 IP9_19_16
4885 IP9_15_12
4886 IP9_11_8
4887 IP9_7_4
4888 IP9_3_0 ))
4889 },
4890 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4891 IP10_31_28
4892 IP10_27_24
4893 IP10_23_20
4894 IP10_19_16
4895 IP10_15_12
4896 IP10_11_8
4897 IP10_7_4
4898 IP10_3_0 ))
4899 },
4900 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4901 IP11_31_28
4902 IP11_27_24
4903 IP11_23_20
4904 IP11_19_16
4905 IP11_15_12
4906 IP11_11_8
4907 IP11_7_4
4908 IP11_3_0 ))
4909 },
4910 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4911 IP12_31_28
4912 IP12_27_24
4913 IP12_23_20
4914 IP12_19_16
4915 IP12_15_12
4916 IP12_11_8
4917 IP12_7_4
4918 IP12_3_0 ))
4919 },
4920 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4921 IP13_31_28
4922 IP13_27_24
4923 IP13_23_20
4924 IP13_19_16
4925 IP13_15_12
4926 IP13_11_8
4927 IP13_7_4
4928 IP13_3_0 ))
4929 },
4930 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4931 IP14_31_28
4932 IP14_27_24
4933 IP14_23_20
4934 IP14_19_16
4935 IP14_15_12
4936 IP14_11_8
4937 IP14_7_4
4938 IP14_3_0 ))
4939 },
4940 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4941 IP15_31_28
4942 IP15_27_24
4943 IP15_23_20
4944 IP15_19_16
4945 IP15_15_12
4946 IP15_11_8
4947 IP15_7_4
4948 IP15_3_0 ))
4949 },
4950#undef F_
4951#undef FM
4952
4953#define F_(x, y) x,
4954#define FM(x) FN_##x,
4955 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4956 GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4957 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4958 GROUP(
4959
4960 MOD_SEL0_30_29
4961 MOD_SEL0_28
4962 MOD_SEL0_27_26
4963 MOD_SEL0_25
4964 MOD_SEL0_24
4965 MOD_SEL0_23
4966 MOD_SEL0_22
4967 MOD_SEL0_21_20
4968 MOD_SEL0_19_18_17
4969 MOD_SEL0_16
4970 MOD_SEL0_15
4971 MOD_SEL0_14
4972 MOD_SEL0_13_12
4973 MOD_SEL0_11_10
4974 MOD_SEL0_9
4975 MOD_SEL0_8
4976 MOD_SEL0_7
4977 MOD_SEL0_6_5
4978 MOD_SEL0_4
4979 MOD_SEL0_3
4980 MOD_SEL0_2
4981 MOD_SEL0_1_0 ))
4982 },
4983 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4984 GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1,
4985 1, 2, 2, 2, 1, 1, 2, 1, -4),
4986 GROUP(
4987 MOD_SEL1_31
4988 MOD_SEL1_30
4989 MOD_SEL1_29
4990 MOD_SEL1_28
4991
4992 MOD_SEL1_26
4993 MOD_SEL1_25
4994 MOD_SEL1_24_23_22
4995 MOD_SEL1_21_20_19
4996 MOD_SEL1_18
4997 MOD_SEL1_17
4998 MOD_SEL1_16
4999 MOD_SEL1_15
5000 MOD_SEL1_14_13
5001 MOD_SEL1_12_11
5002 MOD_SEL1_10_9
5003 MOD_SEL1_8
5004 MOD_SEL1_7
5005 MOD_SEL1_6_5
5006 MOD_SEL1_4
5007 ))
5008 },
5009 { },
5010};
5011
5012static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5013 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5014 { RCAR_GP_PIN(3, 0), 18, 2 },
5015 { RCAR_GP_PIN(3, 1), 15, 2 },
5016 { RCAR_GP_PIN(3, 2), 12, 2 },
5017 { RCAR_GP_PIN(3, 3), 9, 2 },
5018 { RCAR_GP_PIN(3, 4), 6, 2 },
5019 { RCAR_GP_PIN(3, 5), 3, 2 },
5020 { RCAR_GP_PIN(3, 6), 0, 2 },
5021 } },
5022 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5023 { RCAR_GP_PIN(3, 7), 29, 2 },
5024 { RCAR_GP_PIN(3, 8), 26, 2 },
5025 { RCAR_GP_PIN(3, 9), 23, 2 },
5026 { RCAR_GP_PIN(3, 10), 20, 2 },
5027 { RCAR_GP_PIN(3, 11), 17, 2 },
5028 { RCAR_GP_PIN(4, 0), 14, 2 },
5029 { RCAR_GP_PIN(4, 1), 11, 2 },
5030 { RCAR_GP_PIN(4, 2), 8, 2 },
5031 { RCAR_GP_PIN(4, 3), 5, 2 },
5032 { RCAR_GP_PIN(4, 4), 2, 2 },
5033 } },
5034 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5035 { RCAR_GP_PIN(4, 5), 29, 2 },
5036 { RCAR_GP_PIN(4, 6), 26, 2 },
5037 { RCAR_GP_PIN(4, 7), 23, 2 },
5038 { RCAR_GP_PIN(4, 8), 20, 2 },
5039 { RCAR_GP_PIN(4, 9), 17, 2 },
5040 { RCAR_GP_PIN(4, 10), 14, 2 },
5041 } },
5042 { },
5043};
5044
5045enum ioctrl_regs {
5046 POCCTRL0,
5047 TDSELCTRL,
5048};
5049
5050static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5051 [POCCTRL0] = { 0xe6060380, },
5052 [TDSELCTRL] = { 0xe60603c0, },
5053 { },
5054};
5055
5056static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5057{
5058 int bit = -EINVAL;
5059
5060 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5061
5062 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5063 bit = pin & 0x1f;
5064
5065 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5066 bit = (pin & 0x1f) + 19;
5067
5068 return bit;
5069}
5070
5071static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5072 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5073 [0] = RCAR_GP_PIN(2, 23),
5074 [1] = RCAR_GP_PIN(2, 22),
5075 [2] = RCAR_GP_PIN(2, 21),
5076 [3] = PIN_AVB_MDC,
5077 [4] = PIN_AVB_MDIO,
5078 [5] = RCAR_GP_PIN(2, 20),
5079 [6] = PIN_AVB_TD3,
5080 [7] = PIN_AVB_TD2,
5081 [8] = PIN_AVB_TD1,
5082 [9] = PIN_AVB_TD0,
5083 [10] = PIN_AVB_TXC,
5084 [11] = PIN_AVB_TX_CTL,
5085 [12] = RCAR_GP_PIN(2, 19),
5086 [13] = RCAR_GP_PIN(2, 18),
5087 [14] = RCAR_GP_PIN(2, 17),
5088 [15] = RCAR_GP_PIN(2, 16),
5089 [16] = RCAR_GP_PIN(2, 15),
5090 [17] = RCAR_GP_PIN(2, 14),
5091 [18] = RCAR_GP_PIN(2, 13),
5092 [19] = RCAR_GP_PIN(2, 12),
5093 [20] = RCAR_GP_PIN(2, 11),
5094 [21] = RCAR_GP_PIN(2, 10),
5095 [22] = RCAR_GP_PIN(2, 9),
5096 [23] = RCAR_GP_PIN(2, 8),
5097 [24] = RCAR_GP_PIN(2, 7),
5098 [25] = RCAR_GP_PIN(2, 6),
5099 [26] = RCAR_GP_PIN(2, 5),
5100 [27] = RCAR_GP_PIN(2, 4),
5101 [28] = RCAR_GP_PIN(2, 3),
5102 [29] = RCAR_GP_PIN(2, 2),
5103 [30] = RCAR_GP_PIN(2, 1),
5104 [31] = RCAR_GP_PIN(2, 0),
5105 } },
5106 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5107 [0] = RCAR_GP_PIN(0, 4),
5108 [1] = RCAR_GP_PIN(0, 3),
5109 [2] = RCAR_GP_PIN(0, 2),
5110 [3] = RCAR_GP_PIN(0, 1),
5111 [4] = RCAR_GP_PIN(0, 0),
5112 [5] = RCAR_GP_PIN(1, 22),
5113 [6] = RCAR_GP_PIN(1, 21),
5114 [7] = RCAR_GP_PIN(1, 20),
5115 [8] = RCAR_GP_PIN(1, 19),
5116 [9] = RCAR_GP_PIN(1, 18),
5117 [10] = RCAR_GP_PIN(1, 17),
5118 [11] = RCAR_GP_PIN(1, 16),
5119 [12] = RCAR_GP_PIN(1, 15),
5120 [13] = RCAR_GP_PIN(1, 14),
5121 [14] = RCAR_GP_PIN(1, 13),
5122 [15] = RCAR_GP_PIN(1, 12),
5123 [16] = RCAR_GP_PIN(1, 11),
5124 [17] = RCAR_GP_PIN(1, 10),
5125 [18] = RCAR_GP_PIN(1, 9),
5126 [19] = RCAR_GP_PIN(1, 8),
5127 [20] = RCAR_GP_PIN(1, 7),
5128 [21] = RCAR_GP_PIN(1, 6),
5129 [22] = RCAR_GP_PIN(1, 5),
5130 [23] = RCAR_GP_PIN(1, 4),
5131 [24] = RCAR_GP_PIN(1, 3),
5132 [25] = RCAR_GP_PIN(1, 2),
5133 [26] = RCAR_GP_PIN(1, 1),
5134 [27] = RCAR_GP_PIN(1, 0),
5135 [28] = SH_PFC_PIN_NONE,
5136 [29] = SH_PFC_PIN_NONE,
5137 [30] = RCAR_GP_PIN(2, 25),
5138 [31] = RCAR_GP_PIN(2, 24),
5139 } },
5140 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5141 [0] = RCAR_GP_PIN(3, 1),
5142 [1] = RCAR_GP_PIN(3, 0),
5143 [2] = PIN_ASEBRK,
5144 [3] = SH_PFC_PIN_NONE,
5145 [4] = PIN_TDI,
5146 [5] = PIN_TMS,
5147 [6] = PIN_TCK,
5148 [7] = PIN_TRST_N,
5149 [8] = SH_PFC_PIN_NONE,
5150 [9] = SH_PFC_PIN_NONE,
5151 [10] = SH_PFC_PIN_NONE,
5152 [11] = SH_PFC_PIN_NONE,
5153 [12] = SH_PFC_PIN_NONE,
5154 [13] = SH_PFC_PIN_NONE,
5155 [14] = SH_PFC_PIN_NONE,
5156 [15] = PIN_FSCLKST_N,
5157 [16] = RCAR_GP_PIN(0, 17),
5158 [17] = RCAR_GP_PIN(0, 16),
5159 [18] = SH_PFC_PIN_NONE,
5160 [19] = SH_PFC_PIN_NONE,
5161 [20] = PIN_PRESETOUT_N,
5162 [21] = RCAR_GP_PIN(0, 15),
5163 [22] = RCAR_GP_PIN(0, 14),
5164 [23] = RCAR_GP_PIN(0, 13),
5165 [24] = RCAR_GP_PIN(0, 12),
5166 [25] = RCAR_GP_PIN(0, 11),
5167 [26] = RCAR_GP_PIN(0, 10),
5168 [27] = RCAR_GP_PIN(0, 9),
5169 [28] = RCAR_GP_PIN(0, 8),
5170 [29] = RCAR_GP_PIN(0, 7),
5171 [30] = RCAR_GP_PIN(0, 6),
5172 [31] = RCAR_GP_PIN(0, 5),
5173 } },
5174 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5175 [0] = RCAR_GP_PIN(5, 0),
5176 [1] = RCAR_GP_PIN(5, 4),
5177 [2] = RCAR_GP_PIN(5, 3),
5178 [3] = RCAR_GP_PIN(5, 2),
5179 [4] = RCAR_GP_PIN(5, 1),
5180 [5] = SH_PFC_PIN_NONE,
5181 [6] = SH_PFC_PIN_NONE,
5182 [7] = RCAR_GP_PIN(3, 15),
5183 [8] = RCAR_GP_PIN(3, 14),
5184 [9] = RCAR_GP_PIN(3, 13),
5185 [10] = RCAR_GP_PIN(3, 12),
5186 [11] = RCAR_GP_PIN(4, 10),
5187 [12] = RCAR_GP_PIN(4, 9),
5188 [13] = RCAR_GP_PIN(4, 8),
5189 [14] = RCAR_GP_PIN(4, 7),
5190 [15] = RCAR_GP_PIN(4, 6),
5191 [16] = RCAR_GP_PIN(4, 5),
5192 [17] = RCAR_GP_PIN(4, 4),
5193 [18] = RCAR_GP_PIN(4, 3),
5194 [19] = RCAR_GP_PIN(4, 2),
5195 [20] = RCAR_GP_PIN(4, 1),
5196 [21] = RCAR_GP_PIN(4, 0),
5197 [22] = RCAR_GP_PIN(3, 11),
5198 [23] = RCAR_GP_PIN(3, 10),
5199 [24] = RCAR_GP_PIN(3, 9),
5200 [25] = RCAR_GP_PIN(3, 8),
5201 [26] = RCAR_GP_PIN(3, 7),
5202 [27] = RCAR_GP_PIN(3, 6),
5203 [28] = RCAR_GP_PIN(3, 5),
5204 [29] = RCAR_GP_PIN(3, 4),
5205 [30] = RCAR_GP_PIN(3, 3),
5206 [31] = RCAR_GP_PIN(3, 2),
5207 } },
5208 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5209 [0] = RCAR_GP_PIN(6, 8),
5210 [1] = RCAR_GP_PIN(6, 16),
5211 [2] = RCAR_GP_PIN(6, 15),
5212 [3] = RCAR_GP_PIN(6, 14),
5213 [4] = RCAR_GP_PIN(6, 13),
5214 [5] = RCAR_GP_PIN(6, 12),
5215 [6] = RCAR_GP_PIN(6, 11),
5216 [7] = RCAR_GP_PIN(6, 10),
5217 [8] = RCAR_GP_PIN(6, 7),
5218 [9] = RCAR_GP_PIN(6, 6),
5219 [10] = RCAR_GP_PIN(6, 5),
5220 [11] = RCAR_GP_PIN(6, 4),
5221 [12] = RCAR_GP_PIN(6, 3),
5222 [13] = RCAR_GP_PIN(6, 2),
5223 [14] = RCAR_GP_PIN(6, 1),
5224 [15] = RCAR_GP_PIN(6, 0),
5225 [16] = PIN_MLB_REF,
5226 [17] = RCAR_GP_PIN(5, 19),
5227 [18] = RCAR_GP_PIN(5, 18),
5228 [19] = RCAR_GP_PIN(5, 17),
5229 [20] = RCAR_GP_PIN(5, 16),
5230 [21] = RCAR_GP_PIN(5, 15),
5231 [22] = RCAR_GP_PIN(5, 14),
5232 [23] = RCAR_GP_PIN(5, 13),
5233 [24] = RCAR_GP_PIN(5, 12),
5234 [25] = RCAR_GP_PIN(5, 11),
5235 [26] = RCAR_GP_PIN(5, 10),
5236 [27] = RCAR_GP_PIN(5, 9),
5237 [28] = RCAR_GP_PIN(5, 8),
5238 [29] = RCAR_GP_PIN(5, 7),
5239 [30] = RCAR_GP_PIN(5, 6),
5240 [31] = RCAR_GP_PIN(5, 5),
5241 } },
5242 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5243 [0] = SH_PFC_PIN_NONE,
5244 [1] = SH_PFC_PIN_NONE,
5245 [2] = SH_PFC_PIN_NONE,
5246 [3] = SH_PFC_PIN_NONE,
5247 [4] = SH_PFC_PIN_NONE,
5248 [5] = SH_PFC_PIN_NONE,
5249 [6] = SH_PFC_PIN_NONE,
5250 [7] = SH_PFC_PIN_NONE,
5251 [8] = SH_PFC_PIN_NONE,
5252 [9] = SH_PFC_PIN_NONE,
5253 [10] = SH_PFC_PIN_NONE,
5254 [11] = SH_PFC_PIN_NONE,
5255 [12] = SH_PFC_PIN_NONE,
5256 [13] = SH_PFC_PIN_NONE,
5257 [14] = SH_PFC_PIN_NONE,
5258 [15] = SH_PFC_PIN_NONE,
5259 [16] = SH_PFC_PIN_NONE,
5260 [17] = SH_PFC_PIN_NONE,
5261 [18] = SH_PFC_PIN_NONE,
5262 [19] = SH_PFC_PIN_NONE,
5263 [20] = SH_PFC_PIN_NONE,
5264 [21] = SH_PFC_PIN_NONE,
5265 [22] = SH_PFC_PIN_NONE,
5266 [23] = SH_PFC_PIN_NONE,
5267 [24] = SH_PFC_PIN_NONE,
5268 [25] = SH_PFC_PIN_NONE,
5269 [26] = SH_PFC_PIN_NONE,
5270 [27] = SH_PFC_PIN_NONE,
5271 [28] = SH_PFC_PIN_NONE,
5272 [29] = SH_PFC_PIN_NONE,
5273 [30] = RCAR_GP_PIN(6, 9),
5274 [31] = RCAR_GP_PIN(6, 17),
5275 } },
5276 { },
5277};
5278
5279static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
5280 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5281 .get_bias = rcar_pinmux_get_bias,
5282 .set_bias = rcar_pinmux_set_bias,
5283};
5284
5285#ifdef CONFIG_PINCTRL_PFC_R8A774C0
5286const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5287 .name = "r8a774c0_pfc",
5288 .ops = &r8a77990_pfc_ops,
5289 .unlock_reg = 0xe6060000,
5290
5291 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5292
5293 .pins = pinmux_pins,
5294 .nr_pins = ARRAY_SIZE(pinmux_pins),
5295 .groups = pinmux_groups.common,
5296 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5297 .functions = pinmux_functions.common,
5298 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5299
5300 .cfg_regs = pinmux_config_regs,
5301 .drive_regs = pinmux_drive_regs,
5302 .bias_regs = pinmux_bias_regs,
5303 .ioctrl_regs = pinmux_ioctrl_regs,
5304
5305 .pinmux_data = pinmux_data,
5306 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5307};
5308#endif
5309
5310#ifdef CONFIG_PINCTRL_PFC_R8A77990
5311const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5312 .name = "r8a77990_pfc",
5313 .ops = &r8a77990_pfc_ops,
5314 .unlock_reg = 0xe6060000,
5315
5316 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5317
5318 .pins = pinmux_pins,
5319 .nr_pins = ARRAY_SIZE(pinmux_pins),
5320 .groups = pinmux_groups.common,
5321 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5322 ARRAY_SIZE(pinmux_groups.automotive),
5323 .functions = pinmux_functions.common,
5324 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5325 ARRAY_SIZE(pinmux_functions.automotive),
5326
5327 .cfg_regs = pinmux_config_regs,
5328 .drive_regs = pinmux_drive_regs,
5329 .bias_regs = pinmux_bias_regs,
5330 .ioctrl_regs = pinmux_ioctrl_regs,
5331
5332 .pinmux_data = pinmux_data,
5333 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5334};
5335#endif
5336
