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6#include <common.h>
7#include <dm.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11
12#include "pinctrl-rockchip.h"
13#include <dt-bindings/pinctrl/rockchip.h>
14
15static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
16{
17 struct rockchip_pinctrl_priv *priv = bank->priv;
18 struct regmap *regmap;
19 int iomux_num = (pin / 8);
20 int reg, ret, mask;
21 u8 bit;
22 u32 data;
23
24 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
25
26 regmap = priv->regmap_base;
27 reg = bank->iomux[iomux_num].offset;
28 if ((pin % 8) >= 4)
29 reg += 0x4;
30 bit = (pin % 4) * 4;
31 mask = 0xf;
32
33 if (bank->bank_num == 0) {
34 if (pin >= RK_PB4 && pin <= RK_PD7) {
35 if (mux < 8) {
36 reg += 0x4000 - 0xC;
37 data = (mask << (bit + 16));
38 data |= (mux & mask) << bit;
39 ret = regmap_write(regmap, reg, data);
40 } else {
41 u32 reg0 = 0;
42
43 reg0 = reg + 0x4000 - 0xC;
44 data = (mask << (bit + 16));
45 data |= 8 << bit;
46 ret = regmap_write(regmap, reg0, data);
47
48 reg0 = reg + 0x8000;
49 data = (mask << (bit + 16));
50 data |= mux << bit;
51 regmap = priv->regmap_base;
52 regmap_write(regmap, reg0, data);
53 }
54 } else {
55 data = (mask << (bit + 16));
56 data |= (mux & mask) << bit;
57 ret = regmap_write(regmap, reg, data);
58 }
59 return ret;
60 } else if (bank->bank_num > 0) {
61 reg += 0x8000;
62 }
63
64 data = (mask << (bit + 16));
65 data |= (mux & mask) << bit;
66
67 return regmap_write(regmap, reg, data);
68}
69
70#define RK3588_PMU1_IOC_REG (0x0000)
71#define RK3588_PMU2_IOC_REG (0x4000)
72#define RK3588_BUS_IOC_REG (0x8000)
73#define RK3588_VCCIO1_4_IOC_REG (0x9000)
74#define RK3588_VCCIO3_5_IOC_REG (0xA000)
75#define RK3588_VCCIO2_IOC_REG (0xB000)
76#define RK3588_VCCIO6_IOC_REG (0xC000)
77#define RK3588_EMMC_IOC_REG (0xD000)
78
79static const u32 rk3588_ds_regs[][2] = {
80 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
81 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
82 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
83 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
84 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
85 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
86 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
87 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
88 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
89 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
90 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
91 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
92 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
93 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
94 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
95 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
96 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
97 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
98 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
99 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
100 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
101 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
102 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
103 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
104 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
105 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
106 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
107 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
108 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
109 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
110 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
111 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
112 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
113 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
114 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
115 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
116 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
117 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
118 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
119 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
120 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
121};
122
123static const u32 rk3588_p_regs[][2] = {
124 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
125 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
126 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
127 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
128 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
129 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
130 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
131 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
132 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
133 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
134 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
135 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
136 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
137 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
138 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
139 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
140 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
141 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
142 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
143 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
144 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
145 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
146 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
147};
148
149static const u32 rk3588_smt_regs[][2] = {
150 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
151 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
152 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
153 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
154 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
155 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
156 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
157 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
158 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
159 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
160 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
161 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
162 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
163 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
164 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
165 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
166 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
167 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
168 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
169 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
170 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
171 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
172 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
173};
174
175#define RK3588_PULL_BITS_PER_PIN 2
176#define RK3588_PULL_PINS_PER_REG 8
177
178static void rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
179 int pin_num, struct regmap **regmap,
180 int *reg, u8 *bit)
181{
182 struct rockchip_pinctrl_priv *info = bank->priv;
183 u8 bank_num = bank->bank_num;
184 u32 pin = bank_num * 32 + pin_num;
185 int i;
186
187 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
188 if (pin >= rk3588_p_regs[i][0]) {
189 *reg = rk3588_p_regs[i][1];
190 break;
191 }
192 }
193
194 assert(i >= 0);
195
196 *regmap = info->regmap_base;
197 *bit = pin_num % RK3588_PULL_PINS_PER_REG;
198 *bit *= RK3588_PULL_BITS_PER_PIN;
199}
200
201#define RK3588_DRV_BITS_PER_PIN 4
202#define RK3588_DRV_PINS_PER_REG 4
203
204static void rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
205 int pin_num, struct regmap **regmap,
206 int *reg, u8 *bit)
207{
208 struct rockchip_pinctrl_priv *info = bank->priv;
209 u8 bank_num = bank->bank_num;
210 u32 pin = bank_num * 32 + pin_num;
211 int i;
212
213 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
214 if (pin >= rk3588_ds_regs[i][0]) {
215 *reg = rk3588_ds_regs[i][1];
216 break;
217 }
218 }
219
220 assert(i >= 0);
221
222 *regmap = info->regmap_base;
223 *bit = pin_num % RK3588_DRV_PINS_PER_REG;
224 *bit *= RK3588_DRV_BITS_PER_PIN;
225}
226
227#define RK3588_SMT_BITS_PER_PIN 1
228#define RK3588_SMT_PINS_PER_REG 8
229
230static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
231 int pin_num, struct regmap **regmap,
232 int *reg, u8 *bit)
233{
234 struct rockchip_pinctrl_priv *info = bank->priv;
235 u8 bank_num = bank->bank_num;
236 u32 pin = bank_num * 32 + pin_num;
237 int i;
238
239 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
240 if (pin >= rk3588_smt_regs[i][0]) {
241 *reg = rk3588_smt_regs[i][1];
242 break;
243 }
244 }
245
246 assert(i >= 0);
247
248 *regmap = info->regmap_base;
249 *bit = pin_num % RK3588_SMT_PINS_PER_REG;
250 *bit *= RK3588_SMT_BITS_PER_PIN;
251
252 return 0;
253}
254
255static int rk3588_set_pull(struct rockchip_pin_bank *bank,
256 int pin_num, int pull)
257{
258 struct regmap *regmap;
259 int reg, translated_pull;
260 u8 bit, type;
261 u32 data;
262
263 rk3588_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
264 type = bank->pull_type[pin_num / 8];
265 translated_pull = rockchip_translate_pull_value(type, pull);
266 if (translated_pull < 0) {
267 debug("unsupported pull setting %d\n", pull);
268 return -EINVAL;
269 }
270
271
272 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
273 data |= (translated_pull << bit);
274
275 return regmap_write(regmap, reg, data);
276}
277
278static int rk3588_set_drive(struct rockchip_pin_bank *bank,
279 int pin_num, int strength)
280{
281 struct regmap *regmap;
282 int reg;
283 u32 data;
284 u8 bit;
285
286 rk3588_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
287
288
289 data = ((1 << RK3588_DRV_BITS_PER_PIN) - 1) << (bit + 16);
290 data |= (strength << bit);
291
292 return regmap_write(regmap, reg, data);
293}
294
295static int rk3588_set_schmitt(struct rockchip_pin_bank *bank,
296 int pin_num, int enable)
297{
298 struct regmap *regmap;
299 int reg;
300 u32 data;
301 u8 bit;
302
303 rk3588_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
304
305
306 data = ((1 << RK3588_SMT_BITS_PER_PIN) - 1) << (bit + 16);
307 data |= (enable << bit);
308
309 return regmap_write(regmap, reg, data);
310}
311
312static struct rockchip_pin_bank rk3588_pin_banks[] = {
313 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
314 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
315 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
316 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
317 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
318 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
319 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
320 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
321 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
322 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
323};
324
325static const struct rockchip_pin_ctrl rk3588_pin_ctrl = {
326 .pin_banks = rk3588_pin_banks,
327 .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
328 .nr_pins = 160,
329 .set_mux = rk3588_set_mux,
330 .set_pull = rk3588_set_pull,
331 .set_drive = rk3588_set_drive,
332 .set_schmitt = rk3588_set_schmitt,
333};
334
335static const struct udevice_id rk3588_pinctrl_ids[] = {
336 {
337 .compatible = "rockchip,rk3588-pinctrl",
338 .data = (ulong)&rk3588_pin_ctrl
339 },
340 { }
341};
342
343U_BOOT_DRIVER(pinctrl_rk3588) = {
344 .name = "rockchip_rk3588_pinctrl",
345 .id = UCLASS_PINCTRL,
346 .of_match = rk3588_pinctrl_ids,
347 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
348 .ops = &rockchip_pinctrl_ops,
349#if CONFIG_IS_ENABLED(OF_REAL)
350 .bind = dm_scan_fdt_dev,
351#endif
352 .probe = rockchip_pinctrl_probe,
353};
354
