LXR uboot/drivers/pwm/pwm-aspeed.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2022 Aspeed Technology Inc.
   4 *
   5 * PWM controller driver for Aspeed ast2600 SoCs.
   6 * This drivers doesn't support earlier version of the IP.
   7 *
   8 * The formula of pwm period duration:
   9 * period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
  10 *
  11 * The formula of pwm duty cycle duration:
  12 * duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
  13 * = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
  14 *
  15 * The software driver fixes the period to 255, which causes the high-frequency
  16 * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
  17 *
  18 * Register usage:
  19 * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
  20 * Use to determine whether the PWM channel is enabled or disabled
  21 * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
  22 * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
  23 * and duty and the value will apply when CLK_ENABLE be set again.
  24 * Use to determine whether duty_cycle bigger than 0.
  25 * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
  26 * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
  27 * values are equal it means the duty cycle = 100%.
  28 *
  29 * Limitations:
  30 * - When changing both duty cycle and period, we cannot prevent in
  31 *   software that the output might produce a period with mixed
  32 *   settings.
  33 * - Disabling the PWM doesn't complete the current period.
  34 *
  35 * Improvements:
  36 * - When only changing one of duty cycle or period, our pwm controller will not
  37 *   generate the glitch, the configure will change at next cycle of pwm.
  38 *   This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
  39 */
  40
  41#include <common.h>
  42#include <div64.h>
  43#include <dm.h>
  44#include <pwm.h>
  45#include <clk.h>
  46#include <reset.h>
  47#include <regmap.h>
  48#include <syscon.h>
  49#include <dm/device_compat.h>
  50#include <linux/math64.h>
  51#include <linux/bitfield.h>
  52#include <asm/io.h>
  53
  54/* The channel number of Aspeed pwm controller */
  55#define PWM_ASPEED_NR_PWMS 16
  56
  57/* PWM Control Register */
  58#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
  59#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
  60#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
  61#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
  62#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
  63#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
  64#define PWM_ASPEED_CTRL_INVERSE BIT(14)
  65#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
  66#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
  67#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
  68#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
  69
  70/* PWM Duty Cycle Register */
  71#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
  72#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
  73#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
  74#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
  75#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
  76
  77/* PWM fixed value */
  78#define PWM_ASPEED_FIXED_PERIOD 0xff
  79
  80#define NSEC_PER_SEC                    1000000000L
  81
  82struct aspeed_pwm_priv {
  83        struct clk clk;
  84        struct regmap *regmap;
  85        struct reset_ctl reset;
  86};
  87
  88static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  89{
  90        struct aspeed_pwm_priv *priv = dev_get_priv(dev);
  91
  92        if (channel >= PWM_ASPEED_NR_PWMS)
  93                return -EINVAL;
  94
  95        regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
  96                           PWM_ASPEED_CTRL_INVERSE,
  97                           FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
  98                                      polarity));
  99        return 0;
 100}
 101
 102static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 103{
 104        struct aspeed_pwm_priv *priv = dev_get_priv(dev);
 105
 106        if (channel >= PWM_ASPEED_NR_PWMS)
 107                return -EINVAL;
 108
 109        regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
 110                           PWM_ASPEED_CTRL_PIN_ENABLE,
 111                           enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
 112        return 0;
 113}
 114
 115static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
 116                                 uint period_ns, uint duty_ns)
 117{
 118        struct aspeed_pwm_priv *priv = dev_get_priv(dev);
 119        u32 duty_pt;
 120        unsigned long rate;
 121        u64 div_h, div_l, divisor;
 122        bool clk_en;
 123
 124        if (channel >= PWM_ASPEED_NR_PWMS)
 125                return -EINVAL;
 126        dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
 127                duty_ns);
 128
 129        rate = clk_get_rate(&priv->clk);
 130        /*
 131         * Pick the smallest value for div_h so that div_l can be the biggest
 132         * which results in a finer resolution near the target period value.
 133         */
 134        divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
 135                  (PWM_ASPEED_CTRL_CLK_DIV_L + 1);
 136        div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
 137        if (div_h > 0xf)
 138                div_h = 0xf;
 139
 140        divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
 141        div_l = div64_u64((u64)rate * period_ns, divisor);
 142
 143        if (div_l == 0)
 144                return -ERANGE;
 145
 146        div_l -= 1;
 147
 148        if (div_l > 255)
 149                div_l = 255;
 150
 151        dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
 152                div_l);
 153        /* duty_pt = duty_cycle * (PERIOD + 1) / period */
 154        duty_pt = div64_u64(duty_ns * (u64)rate,
 155                            (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
 156        dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
 157                duty_pt);
 158
 159        if (duty_pt == 0) {
 160                clk_en = 0;
 161        } else {
 162                clk_en = 1;
 163                if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
 164                        duty_pt = 0;
 165                /*
 166                 * Fixed DUTY_CYCLE_PERIOD to its max value to get a
 167                 * fine-grained resolution for duty_cycle at the expense of a
 168                 * coarser period resolution.
 169                 */
 170                regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
 171                                   PWM_ASPEED_DUTY_CYCLE_PERIOD |
 172                                       PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
 173                                       PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
 174                                   FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
 175                                              PWM_ASPEED_FIXED_PERIOD) |
 176                                       FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
 177                                                  duty_pt));
 178        }
 179
 180        regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
 181                           PWM_ASPEED_CTRL_CLK_DIV_H |
 182                               PWM_ASPEED_CTRL_CLK_DIV_L |
 183                               PWM_ASPEED_CTRL_CLK_ENABLE,
 184                           FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
 185                               FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
 186                               FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
 187        return 0;
 188}
 189
 190static int aspeed_pwm_probe(struct udevice *dev)
 191{
 192        int ret;
 193        struct aspeed_pwm_priv *priv = dev_get_priv(dev);
 194        struct udevice *parent_dev = dev_get_parent(dev);
 195
 196        priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
 197        if (IS_ERR(priv->regmap)) {
 198                dev_err(dev, "Couldn't get regmap\n");
 199                return PTR_ERR(priv->regmap);
 200        }
 201
 202        ret = clk_get_by_index(parent_dev, 0, &priv->clk);
 203        if (ret < 0) {
 204                dev_err(dev, "get clock failed\n");
 205                return ret;
 206        }
 207
 208        ret = reset_get_by_index(parent_dev, 0, &priv->reset);
 209        if (ret) {
 210                dev_err(dev, "get reset failed\n");
 211                return ret;
 212        }
 213        ret = reset_deassert(&priv->reset);
 214        if (ret) {
 215                dev_err(dev, "cannot deassert reset control: %pe\n",
 216                        ERR_PTR(ret));
 217                return ret;
 218        }
 219
 220        return 0;
 221}
 222
 223static int aspeed_pwm_remove(struct udevice *dev)
 224{
 225        struct aspeed_pwm_priv *priv = dev_get_priv(dev);
 226
 227        reset_assert(&priv->reset);
 228
 229        return 0;
 230}
 231
 232static const struct pwm_ops aspeed_pwm_ops = {
 233        .set_invert     = aspeed_pwm_set_invert,
 234        .set_config     = aspeed_pwm_set_config,
 235        .set_enable     = aspeed_pwm_set_enable,
 236};
 237
 238static const struct udevice_id aspeed_pwm_ids[] = {
 239        { .compatible = "aspeed,ast2600-pwm" },
 240        { }
 241};
 242
 243U_BOOT_DRIVER(aspeed_pwm) = {
 244        .name = "aspeed_pwm",
 245        .id = UCLASS_PWM,
 246        .of_match = aspeed_pwm_ids,
 247        .ops = &aspeed_pwm_ops,
 248        .probe = aspeed_pwm_probe,
 249        .remove = aspeed_pwm_remove,
 250        .priv_auto = sizeof(struct aspeed_pwm_priv),
 251};
 252