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16#include <common.h>
17#include <clk.h>
18#include <cpu_func.h>
19#include <malloc.h>
20#include <dwc3-uboot.h>
21#include <dm/device_compat.h>
22#include <dm/devres.h>
23#include <linux/bug.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/err.h>
27#include <linux/ioport.h>
28#include <dm.h>
29#include <generic-phy.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/bitfield.h>
33#include <linux/math64.h>
34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "linux-compat.h"
40
41#define NSEC_PER_SEC 1000000000L
42
43static LIST_HEAD(dwc3_list);
44
45
46static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
51 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
52 reg |= DWC3_GCTL_PRTCAPDIR(mode);
53 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
54}
55
56
57
58
59
60static int dwc3_core_soft_reset(struct dwc3 *dwc)
61{
62 u32 reg;
63
64
65 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
66 reg |= DWC3_GCTL_CORESOFTRESET;
67 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
68
69
70 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
71 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
72 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
73
74
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
76 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
78
79 mdelay(100);
80
81
82 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
83 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
84 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
85
86
87 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
88 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
89 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
90
91 mdelay(100);
92
93
94 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
95 reg &= ~DWC3_GCTL_CORESOFTRESET;
96 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
97
98 return 0;
99}
100
101
102
103
104
105
106static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
107{
108 u32 reg;
109
110 if (dwc->revision < DWC3_REVISION_250A)
111 return;
112
113 if (fladj == 0)
114 return;
115
116 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
117 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
118 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
119 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
120}
121
122
123
124
125
126
127
128
129
130
131static void dwc3_ref_clk_period(struct dwc3 *dwc)
132{
133 unsigned long period;
134 unsigned long fladj;
135 unsigned long decr;
136 unsigned long rate;
137 u32 reg;
138
139 if (dwc->ref_clk) {
140 rate = clk_get_rate(dwc->ref_clk);
141 if (!rate)
142 return;
143 period = NSEC_PER_SEC / rate;
144 } else {
145 return;
146 }
147
148 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
149 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
150 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
151 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
152
153 if (dwc->revision <= DWC3_REVISION_250A)
154 return;
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
172 fladj -= 125000;
173
174
175
176
177 decr = 480000000 / rate;
178
179 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
180 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
181 & ~DWC3_GFLADJ_240MHZDECR
182 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
183 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
184 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
185 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
186 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
187}
188
189
190
191
192
193
194static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
195 struct dwc3_event_buffer *evt)
196{
197 dma_free_coherent(evt->buf);
198}
199
200
201
202
203
204
205
206
207
208static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
209 unsigned length)
210{
211 struct dwc3_event_buffer *evt;
212
213 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
214 GFP_KERNEL);
215 if (!evt)
216 return ERR_PTR(-ENOMEM);
217
218 evt->dwc = dwc;
219 evt->length = length;
220 evt->buf = dma_alloc_coherent(length,
221 (unsigned long *)&evt->dma);
222 if (!evt->buf)
223 return ERR_PTR(-ENOMEM);
224
225 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
226
227 return evt;
228}
229
230
231
232
233
234static void dwc3_free_event_buffers(struct dwc3 *dwc)
235{
236 struct dwc3_event_buffer *evt;
237 int i;
238
239 for (i = 0; i < dwc->num_event_buffers; i++) {
240 evt = dwc->ev_buffs[i];
241 if (evt)
242 dwc3_free_one_event_buffer(dwc, evt);
243 }
244}
245
246
247
248
249
250
251
252
253
254static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
255{
256 int num;
257 int i;
258
259 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
260 dwc->num_event_buffers = num;
261
262 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
263 sizeof(*dwc->ev_buffs) * num);
264 if (!dwc->ev_buffs)
265 return -ENOMEM;
266
267 for (i = 0; i < num; i++) {
268 struct dwc3_event_buffer *evt;
269
270 evt = dwc3_alloc_one_event_buffer(dwc, length);
271 if (IS_ERR(evt)) {
272 dev_err(dwc->dev, "can't allocate event buffer\n");
273 return PTR_ERR(evt);
274 }
275 dwc->ev_buffs[i] = evt;
276 }
277
278 return 0;
279}
280
281
282
283
284
285
286
287static int dwc3_event_buffers_setup(struct dwc3 *dwc)
288{
289 struct dwc3_event_buffer *evt;
290 int n;
291
292 for (n = 0; n < dwc->num_event_buffers; n++) {
293 evt = dwc->ev_buffs[n];
294 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
295 evt->buf, (unsigned long long) evt->dma,
296 evt->length);
297
298 evt->lpos = 0;
299
300 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
301 lower_32_bits(evt->dma));
302 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
303 upper_32_bits(evt->dma));
304 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
305 DWC3_GEVNTSIZ_SIZE(evt->length));
306 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
307 }
308
309 return 0;
310}
311
312static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
313{
314 struct dwc3_event_buffer *evt;
315 int n;
316
317 for (n = 0; n < dwc->num_event_buffers; n++) {
318 evt = dwc->ev_buffs[n];
319
320 evt->lpos = 0;
321
322 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
323 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
324 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
325 | DWC3_GEVNTSIZ_SIZE(0));
326 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
327 }
328}
329
330static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
331{
332 if (!dwc->has_hibernation)
333 return 0;
334
335 if (!dwc->nr_scratch)
336 return 0;
337
338 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
339 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
340 if (!dwc->scratchbuf)
341 return -ENOMEM;
342
343 return 0;
344}
345
346static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
347{
348 dma_addr_t scratch_addr;
349 u32 param;
350 int ret;
351
352 if (!dwc->has_hibernation)
353 return 0;
354
355 if (!dwc->nr_scratch)
356 return 0;
357
358 scratch_addr = dma_map_single(dwc->scratchbuf,
359 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
360 DMA_BIDIRECTIONAL);
361 if (dma_mapping_error(dwc->dev, scratch_addr)) {
362 dev_err(dwc->dev, "failed to map scratch buffer\n");
363 ret = -EFAULT;
364 goto err0;
365 }
366
367 dwc->scratch_addr = scratch_addr;
368
369 param = lower_32_bits(scratch_addr);
370
371 ret = dwc3_send_gadget_generic_command(dwc,
372 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
373 if (ret < 0)
374 goto err1;
375
376 param = upper_32_bits(scratch_addr);
377
378 ret = dwc3_send_gadget_generic_command(dwc,
379 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
380 if (ret < 0)
381 goto err1;
382
383 return 0;
384
385err1:
386 dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
387 DMA_BIDIRECTIONAL);
388
389err0:
390 return ret;
391}
392
393static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
394{
395 if (!dwc->has_hibernation)
396 return;
397
398 if (!dwc->nr_scratch)
399 return;
400
401 dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
402 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
403 kfree(dwc->scratchbuf);
404}
405
406static void dwc3_core_num_eps(struct dwc3 *dwc)
407{
408 struct dwc3_hwparams *parms = &dwc->hwparams;
409
410 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
411 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
412
413 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
414 dwc->num_in_eps, dwc->num_out_eps);
415}
416
417static void dwc3_cache_hwparams(struct dwc3 *dwc)
418{
419 struct dwc3_hwparams *parms = &dwc->hwparams;
420
421 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
422 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
423 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
424 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
425 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
426 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
427 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
428 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
429 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
430}
431
432static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
433{
434 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
435 u32 reg;
436
437
438 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
439
440 switch (hsphy_mode) {
441 case USBPHY_INTERFACE_MODE_UTMI:
442 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
443 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
444 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
445 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
446 break;
447 case USBPHY_INTERFACE_MODE_UTMIW:
448 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
449 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
450 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
451 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
452 break;
453 default:
454 break;
455 }
456
457 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
458}
459
460
461
462
463
464static void dwc3_phy_setup(struct dwc3 *dwc)
465{
466 u32 reg;
467
468 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
469
470
471
472
473
474
475
476 if (dwc->revision > DWC3_REVISION_194A)
477 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
478
479 if (dwc->u2ss_inp3_quirk)
480 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
481
482 if (dwc->req_p1p2p3_quirk)
483 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
484
485 if (dwc->del_p1p2p3_quirk)
486 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
487
488 if (dwc->del_phy_power_chg_quirk)
489 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
490
491 if (dwc->lfps_filter_quirk)
492 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
493
494 if (dwc->rx_detect_poll_quirk)
495 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
496
497 if (dwc->tx_de_emphasis_quirk)
498 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
499
500 if (dwc->dis_u3_susphy_quirk)
501 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
502
503 if (dwc->dis_del_phy_power_chg_quirk)
504 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
505
506 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
507
508 dwc3_hsphy_mode_setup(dwc);
509
510 mdelay(100);
511
512 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
513
514
515
516
517
518
519
520 if (dwc->revision > DWC3_REVISION_194A)
521 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
522
523 if (dwc->dis_u2_susphy_quirk)
524 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
525
526 if (dwc->dis_enblslpm_quirk)
527 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
528
529 if (dwc->dis_u2_freeclk_exists_quirk)
530 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
531
532 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
533
534 mdelay(100);
535}
536
537
538static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
539{
540 struct udevice *dev = dwc->dev;
541 u32 cfg;
542
543 if (!dwc->incrx_size)
544 return;
545
546 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
547
548
549 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
550 if (dwc->incrx_mode)
551 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
552 switch (dwc->incrx_size) {
553 case 256:
554 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
555 break;
556 case 128:
557 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
558 break;
559 case 64:
560 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
561 break;
562 case 32:
563 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
564 break;
565 case 16:
566 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
567 break;
568 case 8:
569 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
570 break;
571 case 4:
572 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
573 break;
574 case 1:
575 break;
576 default:
577 dev_err(dev, "Invalid property\n");
578 break;
579 }
580
581 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
582}
583
584
585
586
587
588
589
590static int dwc3_core_init(struct dwc3 *dwc)
591{
592 unsigned long timeout;
593 u32 hwparams4 = dwc->hwparams.hwparams4;
594 u32 reg;
595 int ret;
596
597 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
598
599 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
600 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
601 ret = -ENODEV;
602 goto err0;
603 }
604 dwc->revision = reg;
605
606
607 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
608 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
609 if (dwc->maximum_speed == USB_SPEED_SUPER)
610 dwc->maximum_speed = USB_SPEED_HIGH;
611 }
612
613
614 timeout = 5000;
615 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
616 while (timeout--) {
617 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
618 if (!(reg & DWC3_DCTL_CSFTRST))
619 break;
620 };
621
622 if (!timeout) {
623 dev_err(dwc->dev, "Reset Timed Out\n");
624 ret = -ETIMEDOUT;
625 goto err0;
626 }
627
628 dwc3_phy_setup(dwc);
629
630 ret = dwc3_core_soft_reset(dwc);
631 if (ret)
632 goto err0;
633
634 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
635 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
636
637 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
638 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
639
640
641
642
643
644
645
646
647
648
649
650
651 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
652 dwc->dr_mode == USB_DR_MODE_OTG) &&
653 (dwc->revision >= DWC3_REVISION_210A &&
654 dwc->revision <= DWC3_REVISION_250A))
655 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
656 else
657 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
658 break;
659 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
660
661 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
662
663
664
665
666
667 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
668 break;
669 default:
670 dev_dbg(dwc->dev, "No power optimization available\n");
671 }
672
673
674 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
675 dev_dbg(dwc->dev, "it is on FPGA board\n");
676 dwc->is_fpga = true;
677 }
678
679 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
680 WARN(true,
681 "disable_scramble cannot be used on non-FPGA builds\n");
682
683 if (dwc->disable_scramble_quirk && dwc->is_fpga)
684 reg |= DWC3_GCTL_DISSCRAMBLE;
685 else
686 reg &= ~DWC3_GCTL_DISSCRAMBLE;
687
688 if (dwc->u2exit_lfps_quirk)
689 reg |= DWC3_GCTL_U2EXIT_LFPS;
690
691
692
693
694
695
696
697 if (dwc->revision < DWC3_REVISION_190A)
698 reg |= DWC3_GCTL_U2RSTECN;
699
700 dwc3_core_num_eps(dwc);
701
702 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
703
704 ret = dwc3_alloc_scratch_buffers(dwc);
705 if (ret)
706 goto err0;
707
708 ret = dwc3_setup_scratch_buffers(dwc);
709 if (ret)
710 goto err1;
711
712
713 dwc3_frame_length_adjustment(dwc, dwc->fladj);
714
715
716 dwc3_ref_clk_period(dwc);
717
718 dwc3_set_incr_burst_type(dwc);
719
720 return 0;
721
722err1:
723 dwc3_free_scratch_buffers(dwc);
724
725err0:
726 return ret;
727}
728
729static void dwc3_core_exit(struct dwc3 *dwc)
730{
731 dwc3_free_scratch_buffers(dwc);
732}
733
734static int dwc3_core_init_mode(struct dwc3 *dwc)
735{
736 int ret;
737
738 switch (dwc->dr_mode) {
739 case USB_DR_MODE_PERIPHERAL:
740 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
741 ret = dwc3_gadget_init(dwc);
742 if (ret) {
743 dev_err(dwc->dev, "failed to initialize gadget\n");
744 return ret;
745 }
746 break;
747 case USB_DR_MODE_HOST:
748 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
749 ret = dwc3_host_init(dwc);
750 if (ret) {
751 dev_err(dwc->dev, "failed to initialize host\n");
752 return ret;
753 }
754 break;
755 case USB_DR_MODE_OTG:
756 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
757 ret = dwc3_host_init(dwc);
758 if (ret) {
759 dev_err(dwc->dev, "failed to initialize host\n");
760 return ret;
761 }
762
763 ret = dwc3_gadget_init(dwc);
764 if (ret) {
765 dev_err(dwc->dev, "failed to initialize gadget\n");
766 return ret;
767 }
768 break;
769 default:
770 dev_err(dwc->dev,
771 "Unsupported mode of operation %d\n", dwc->dr_mode);
772 return -EINVAL;
773 }
774
775 return 0;
776}
777
778static void dwc3_gadget_run(struct dwc3 *dwc)
779{
780 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
781 mdelay(100);
782}
783
784static void dwc3_core_stop(struct dwc3 *dwc)
785{
786 u32 reg;
787
788 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
789 dwc3_writel(dwc->regs, DWC3_DCTL, reg & ~(DWC3_DCTL_RUN_STOP));
790}
791
792static void dwc3_core_exit_mode(struct dwc3 *dwc)
793{
794 switch (dwc->dr_mode) {
795 case USB_DR_MODE_PERIPHERAL:
796 dwc3_gadget_exit(dwc);
797 break;
798 case USB_DR_MODE_HOST:
799 dwc3_host_exit(dwc);
800 break;
801 case USB_DR_MODE_OTG:
802 dwc3_host_exit(dwc);
803 dwc3_gadget_exit(dwc);
804 break;
805 default:
806
807 break;
808 }
809
810
811
812
813
814 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
815 dwc3_gadget_run(dwc);
816}
817
818#define DWC3_ALIGN_MASK (16 - 1)
819
820
821
822
823
824
825
826
827
828
829
830
831int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
832{
833 struct dwc3 *dwc;
834 struct device *dev = NULL;
835 u8 lpm_nyet_threshold;
836 u8 tx_de_emphasis;
837 u8 hird_threshold;
838
839 int ret;
840
841 void *mem;
842
843 mem = devm_kzalloc((struct udevice *)dev,
844 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
845 if (!mem)
846 return -ENOMEM;
847
848 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
849 dwc->mem = mem;
850
851 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
852 DWC3_GLOBALS_REGS_START);
853
854
855 lpm_nyet_threshold = 0xff;
856
857
858 tx_de_emphasis = 1;
859
860
861
862
863
864 hird_threshold = 12;
865
866 dwc->maximum_speed = dwc3_dev->maximum_speed;
867 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
868 if (dwc3_dev->lpm_nyet_threshold)
869 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
870 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
871 if (dwc3_dev->hird_threshold)
872 hird_threshold = dwc3_dev->hird_threshold;
873
874 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
875 dwc->dr_mode = dwc3_dev->dr_mode;
876
877 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
878 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
879 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
880 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
881 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
882 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
883 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
884 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
885 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
886 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
887 dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
888 dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
889 dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
890 dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
891
892 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
893 if (dwc3_dev->tx_de_emphasis)
894 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
895
896
897 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
898 dwc->maximum_speed = USB_SPEED_SUPER;
899
900 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
901 dwc->tx_de_emphasis = tx_de_emphasis;
902
903 dwc->hird_threshold = hird_threshold
904 | (dwc->is_utmi_l1_suspend << 4);
905
906 dwc->hsphy_mode = dwc3_dev->hsphy_mode;
907
908 dwc->index = dwc3_dev->index;
909
910 dwc3_cache_hwparams(dwc);
911
912 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
913 if (ret) {
914 dev_err(dwc->dev, "failed to allocate event buffers\n");
915 return -ENOMEM;
916 }
917
918 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
919 dwc->dr_mode = USB_DR_MODE_HOST;
920 else if (!IS_ENABLED(CONFIG_USB_HOST))
921 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
922
923 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
924 dwc->dr_mode = USB_DR_MODE_OTG;
925
926 ret = dwc3_core_init(dwc);
927 if (ret) {
928 dev_err(dwc->dev, "failed to initialize core\n");
929 goto err0;
930 }
931
932 ret = dwc3_event_buffers_setup(dwc);
933 if (ret) {
934 dev_err(dwc->dev, "failed to setup event buffers\n");
935 goto err1;
936 }
937
938 ret = dwc3_core_init_mode(dwc);
939 if (ret)
940 goto err2;
941
942 list_add_tail(&dwc->list, &dwc3_list);
943
944 return 0;
945
946err2:
947 dwc3_event_buffers_cleanup(dwc);
948
949err1:
950 dwc3_core_exit(dwc);
951
952err0:
953 dwc3_free_event_buffers(dwc);
954
955 return ret;
956}
957
958
959
960
961
962
963
964
965
966
967
968
969void dwc3_uboot_exit(int index)
970{
971 struct dwc3 *dwc;
972
973 list_for_each_entry(dwc, &dwc3_list, list) {
974 if (dwc->index != index)
975 continue;
976
977 dwc3_core_exit_mode(dwc);
978 dwc3_event_buffers_cleanup(dwc);
979 dwc3_free_event_buffers(dwc);
980 dwc3_core_exit(dwc);
981 list_del(&dwc->list);
982 kfree(dwc->mem);
983 break;
984 }
985}
986
987
988
989
990
991
992
993
994
995void dwc3_uboot_handle_interrupt(int index)
996{
997 struct dwc3 *dwc = NULL;
998
999 list_for_each_entry(dwc, &dwc3_list, list) {
1000 if (dwc->index != index)
1001 continue;
1002
1003 dwc3_gadget_uboot_handle_interrupt(dwc);
1004 break;
1005 }
1006}
1007
1008MODULE_ALIAS("platform:dwc3");
1009MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1010MODULE_LICENSE("GPL v2");
1011MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1012
1013#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
1014int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
1015{
1016 int ret;
1017
1018 ret = generic_phy_get_bulk(dev, phys);
1019 if (ret)
1020 return ret;
1021
1022 ret = generic_phy_init_bulk(phys);
1023 if (ret)
1024 return ret;
1025
1026 ret = generic_phy_power_on_bulk(phys);
1027 if (ret)
1028 generic_phy_exit_bulk(phys);
1029
1030 return ret;
1031}
1032
1033int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
1034{
1035 int ret;
1036
1037 ret = generic_phy_power_off_bulk(phys);
1038 ret |= generic_phy_exit_bulk(phys);
1039 return ret;
1040}
1041#endif
1042
1043#if CONFIG_IS_ENABLED(DM_USB)
1044void dwc3_of_parse(struct dwc3 *dwc)
1045{
1046 const u8 *tmp;
1047 struct udevice *dev = dwc->dev;
1048 u8 lpm_nyet_threshold;
1049 u8 tx_de_emphasis;
1050 u8 hird_threshold;
1051 u32 val;
1052 int i;
1053
1054
1055 lpm_nyet_threshold = 0xff;
1056
1057
1058 tx_de_emphasis = 1;
1059
1060
1061
1062
1063
1064 hird_threshold = 12;
1065
1066 dwc->hsphy_mode = usb_get_phy_mode(dev_ofnode(dev));
1067
1068 dwc->has_lpm_erratum = dev_read_bool(dev,
1069 "snps,has-lpm-erratum");
1070 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
1071 if (tmp)
1072 lpm_nyet_threshold = *tmp;
1073
1074 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
1075 "snps,is-utmi-l1-suspend");
1076 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
1077 if (tmp)
1078 hird_threshold = *tmp;
1079
1080 dwc->disable_scramble_quirk = dev_read_bool(dev,
1081 "snps,disable_scramble_quirk");
1082 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
1083 "snps,u2exit_lfps_quirk");
1084 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
1085 "snps,u2ss_inp3_quirk");
1086 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
1087 "snps,req_p1p2p3_quirk");
1088 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
1089 "snps,del_p1p2p3_quirk");
1090 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
1091 "snps,del_phy_power_chg_quirk");
1092 dwc->lfps_filter_quirk = dev_read_bool(dev,
1093 "snps,lfps_filter_quirk");
1094 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
1095 "snps,rx_detect_poll_quirk");
1096 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
1097 "snps,dis_u3_susphy_quirk");
1098 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
1099 "snps,dis_u2_susphy_quirk");
1100 dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
1101 "snps,dis-del-phy-power-chg-quirk");
1102 dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
1103 "snps,dis-tx-ipgap-linecheck-quirk");
1104 dwc->dis_enblslpm_quirk = dev_read_bool(dev,
1105 "snps,dis_enblslpm_quirk");
1106 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
1107 "snps,dis-u2-freeclk-exists-quirk");
1108 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
1109 "snps,tx_de_emphasis_quirk");
1110 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
1111 if (tmp)
1112 tx_de_emphasis = *tmp;
1113
1114 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1115 dwc->tx_de_emphasis = tx_de_emphasis;
1116
1117 dwc->hird_threshold = hird_threshold
1118 | (dwc->is_utmi_l1_suspend << 4);
1119
1120 dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj);
1121
1122
1123
1124
1125
1126
1127
1128
1129 dwc->incrx_mode = INCRX_BURST_MODE;
1130 dwc->incrx_size = 0;
1131 for (i = 0; i < 8; i++) {
1132 if (dev_read_u32_index(dev, "snps,incr-burst-type-adjustment",
1133 i, &val))
1134 break;
1135
1136 dwc->incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1137 dwc->incrx_size = max(dwc->incrx_size, val);
1138 }
1139}
1140
1141int dwc3_init(struct dwc3 *dwc)
1142{
1143 int ret;
1144 u32 reg;
1145
1146 dwc3_cache_hwparams(dwc);
1147
1148 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1149 if (ret) {
1150 dev_err(dwc->dev, "failed to allocate event buffers\n");
1151 return -ENOMEM;
1152 }
1153
1154 ret = dwc3_core_init(dwc);
1155 if (ret) {
1156 dev_err(dwc->dev, "failed to initialize core\n");
1157 goto core_fail;
1158 }
1159
1160 ret = dwc3_event_buffers_setup(dwc);
1161 if (ret) {
1162 dev_err(dwc->dev, "failed to setup event buffers\n");
1163 goto event_fail;
1164 }
1165
1166 if (dwc->revision >= DWC3_REVISION_250A) {
1167 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1168
1169
1170
1171
1172
1173 if (dwc->revision >= DWC3_REVISION_290A)
1174 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1175
1176 if (dwc->dis_tx_ipgap_linecheck_quirk)
1177 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1178
1179 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1180 }
1181
1182 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1183 dwc->dr_mode == USB_DR_MODE_OTG) {
1184 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1185
1186 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1187
1188 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1189 }
1190
1191 ret = dwc3_core_init_mode(dwc);
1192 if (ret)
1193 goto mode_fail;
1194
1195 return 0;
1196
1197mode_fail:
1198 dwc3_event_buffers_cleanup(dwc);
1199
1200event_fail:
1201 dwc3_core_exit(dwc);
1202
1203core_fail:
1204 dwc3_free_event_buffers(dwc);
1205
1206 return ret;
1207}
1208
1209void dwc3_remove(struct dwc3 *dwc)
1210{
1211 dwc3_core_exit_mode(dwc);
1212 dwc3_event_buffers_cleanup(dwc);
1213 dwc3_free_event_buffers(dwc);
1214 dwc3_core_stop(dwc);
1215 dwc3_core_exit(dwc);
1216 kfree(dwc->mem);
1217}
1218#endif
1219