LXR uboot/drivers/usb/mtu3/mtu3.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * mtu3.h - MediaTek USB3 DRD header
   4 *
   5 * Copyright (C) 2016 MediaTek Inc.
   6 *
   7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   8 */
   9
  10#ifndef __MTU3_H__
  11#define __MTU3_H__
  12
  13#include <asm/io.h>
  14#include <clk.h>
  15#include <dm.h>
  16#include <dm/device_compat.h>
  17#include <dm/devres.h>
  18#include <generic-phy.h>
  19#include <linux/bug.h>
  20#include <linux/delay.h>
  21#include <linux/usb/ch9.h>
  22#include <linux/usb/gadget.h>
  23#include <linux/usb/otg.h>
  24#include <power/regulator.h>
  25#include <usb/xhci.h>
  26
  27struct mtu3;
  28struct mtu3_ep;
  29struct mtu3_request;
  30struct mtu3_host;
  31
  32#include "mtu3_hw_regs.h"
  33#include "mtu3_qmu.h"
  34
  35#define MU3D_EP_TXCR0(epnum)    (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
  36#define MU3D_EP_TXCR1(epnum)    (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
  37#define MU3D_EP_TXCR2(epnum)    (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
  38
  39#define MU3D_EP_RXCR0(epnum)    (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
  40#define MU3D_EP_RXCR1(epnum)    (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
  41#define MU3D_EP_RXCR2(epnum)    (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
  42
  43#define USB_QMU_RQCSR(epnum)    (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
  44#define USB_QMU_RQSAR(epnum)    (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
  45#define USB_QMU_RQCPR(epnum)    (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
  46
  47#define USB_QMU_TQCSR(epnum)    (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
  48#define USB_QMU_TQSAR(epnum)    (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
  49#define USB_QMU_TQCPR(epnum)    (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
  50
  51#define SSUSB_U3_CTRL(p)        (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
  52#define SSUSB_U2_CTRL(p)        (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
  53
  54#define MTU3_DRIVER_NAME        "mtu3-gadget"
  55#define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  56
  57#define MTU3_EP_ENABLED         BIT(0)
  58#define MTU3_EP_STALL           BIT(1)
  59#define MTU3_EP_WEDGE           BIT(2)
  60#define MTU3_EP_BUSY            BIT(3)
  61
  62/* should be set as 1 */
  63#define MTU3_U2_IP_SLOT_DEFAULT 1
  64#define MTU3_U3_IP_SLOT_DEFAULT (MTU3_U2_IP_SLOT_DEFAULT)
  65
  66/**
  67 * IP TRUNK version
  68 * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
  69 * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
  70 *    but not backward compatible
  71 * 2. QMU extend buffer length supported
  72 */
  73#define MTU3_TRUNK_VERS_1003    0x1003
  74
  75/**
  76 * Normally the device works on HS or SS, to simplify fifo management,
  77 * devide fifo into some 2*maxp parts, use bitmap to manage it; And
  78 * 32 bits size of bitmap is large enough, that means it can manage
  79 * up to 32KB/64KB fifo size.
  80 * NOTE: MTU3_U2/3IP_EP_FIFO_UNIT should be power of two;
  81 *      FIFO size is allocated according to @slot which is 1 by default
  82 */
  83#define USB_HS_MAXP     512
  84#define USB_SS_MAXP     1024
  85#define MTU3_U2IP_EP_FIFO_UNIT  \
  86        ((USB_HS_MAXP) * ((MTU3_U2_IP_SLOT_DEFAULT) + 1))
  87#define MTU3_U3IP_EP_FIFO_UNIT  \
  88        ((USB_SS_MAXP) * ((MTU3_U3_IP_SLOT_DEFAULT) + 1))
  89
  90#define MTU3_FIFO_BIT_SIZE              32
  91#define MTU3_U2_IP_EP0_FIFO_SIZE        64
  92
  93/**
  94 * Maximum size of ep0 response buffer for ch9 requests,
  95 * the SET_SEL request uses 6 so far, and GET_STATUS is 2
  96 */
  97#define EP0_RESPONSE_BUF  6
  98
  99/* device operated link and speed got from DEVICE_CONF register */
 100enum mtu3_speed {
 101        MTU3_SPEED_INACTIVE = 0,
 102        MTU3_SPEED_FULL = 1,
 103        MTU3_SPEED_HIGH = 3,
 104        MTU3_SPEED_SUPER = 4,
 105        MTU3_SPEED_SUPER_PLUS = 5,
 106};
 107
 108/**
 109 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
 110 *              without data stage.
 111 * @MU3D_EP0_STATE_TX: IN data stage
 112 * @MU3D_EP0_STATE_RX: OUT data stage
 113 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
 114 *              waits for its completion interrupt
 115 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
 116 *              after receives a SETUP.
 117 */
 118enum mtu3_g_ep0_state {
 119        MU3D_EP0_STATE_SETUP = 1,
 120        MU3D_EP0_STATE_TX,
 121        MU3D_EP0_STATE_RX,
 122        MU3D_EP0_STATE_TX_END,
 123        MU3D_EP0_STATE_STALL,
 124};
 125
 126/**
 127 * MTU3_DR_FORCE_NONE: automatically switch host and peripheral mode
 128 *              by IDPIN signal.
 129 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
 130 *              IDPIN signal.
 131 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
 132 */
 133enum mtu3_dr_force_mode {
 134        MTU3_DR_FORCE_NONE = 0,
 135        MTU3_DR_FORCE_HOST,
 136        MTU3_DR_FORCE_DEVICE,
 137};
 138
 139/**
 140 * @mac_base: register base address of MAC, include xHCI and device
 141 * @ippc_base: register base address of IP Power and Clock interface (IPPC)
 142 * @vusb33_supply: usb3.3V shared by device/host IP
 143 * @vbus_supply: vbus 5v of OTG port
 144 * @clks: optional clocks, include "sys_ck", "ref_ck", "mcu_ck",
 145 *              "dma_ck" and "xhci_ck"
 146 * @phys: phys used
 147 * @dr_mode: works in which mode:
 148 *              host only, device only or dual-role mode
 149 */
 150struct ssusb_mtk {
 151        struct udevice *dev;
 152        struct mtu3 *u3d;
 153        struct mtu3_host *u3h;
 154        void __iomem *mac_base;
 155        void __iomem *ippc_base;
 156        /* common power & clock */
 157        struct udevice *vusb33_supply;
 158        struct udevice *vbus_supply;
 159        struct clk_bulk clks;
 160        struct phy_bulk phys;
 161        /* otg */
 162        enum usb_dr_mode dr_mode;
 163};
 164
 165/**
 166 * @ctrl: xHCI controller, needs to come first in this struct!
 167 * @hcd: xHCI's register base address
 168 * @u2_ports: number of usb2 host ports
 169 * @u3_ports: number of usb3 host ports
 170 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
 171 *              disable u3port0, bit1==1 to disable u3port1,... etc
 172 */
 173struct mtu3_host {
 174        struct xhci_ctrl ctrl;
 175        struct xhci_hccr *hcd;
 176        void __iomem *ippc_base;
 177        struct ssusb_mtk *ssusb;
 178        struct udevice *dev;
 179        u32 u2_ports;
 180        u32 u3_ports;
 181        u32 u3p_dis_msk;
 182};
 183
 184/**
 185 * @base: the base address of fifo
 186 * @limit: the bitmap size in bits
 187 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
 188 */
 189struct mtu3_fifo_info {
 190        u32 base;
 191        u32 limit;
 192        DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
 193};
 194
 195/**
 196 * General Purpose Descriptor (GPD):
 197 *      The format of TX GPD is a little different from RX one.
 198 *      And the size of GPD is 16 bytes.
 199 *
 200 * @flag:
 201 *      bit0: Hardware Own (HWO)
 202 *      bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
 203 *      bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
 204 *      bit7: Interrupt On Completion (IOC)
 205 * @chksum: This is used to validate the contents of this GPD;
 206 *      If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued
 207 *      when checksum validation fails;
 208 *      Checksum value is calculated over the 16 bytes of the GPD by default;
 209 * @data_buf_len (RX ONLY): This value indicates the length of
 210 *      the assigned data buffer
 211 * @next_gpd: Physical address of the next GPD
 212 * @buffer: Physical address of the data buffer
 213 * @buf_len:
 214 *      (TX): This value indicates the length of the assigned data buffer
 215 *      (RX): The total length of data received
 216 * @ext_len: reserved
 217 * @ext_flag:
 218 *      bit5 (TX ONLY): Zero Length Packet (ZLP),
 219 */
 220struct qmu_gpd {
 221        __u8 flag;
 222        __u8 chksum;
 223        __le16 data_buf_len;
 224        __le32 next_gpd;
 225        __le32 buffer;
 226        __le16 buf_len;
 227        __u8 ext_len;
 228        __u8 ext_flag;
 229} __packed;
 230
 231/**
 232 * dma: physical base address of GPD segment
 233 * start: virtual base address of GPD segment
 234 * end: the last GPD element
 235 * enqueue: the first empty GPD to use
 236 * dequeue: the first completed GPD serviced by ISR
 237 * NOTE: the size of GPD ring should be >= 2
 238 */
 239struct mtu3_gpd_ring {
 240        dma_addr_t dma;
 241        struct qmu_gpd *start;
 242        struct qmu_gpd *end;
 243        struct qmu_gpd *enqueue;
 244        struct qmu_gpd *dequeue;
 245};
 246
 247/**
 248 * @fifo_size: it is (@slot + 1) * @fifo_seg_size
 249 * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
 250 */
 251struct mtu3_ep {
 252        struct usb_ep ep;
 253        char name[12];
 254        struct mtu3 *mtu;
 255        u8 epnum;
 256        u8 type;
 257        u8 is_in;
 258        u16 maxp;
 259        int slot;
 260        u32 fifo_size;
 261        u32 fifo_addr;
 262        u32 fifo_seg_size;
 263        struct mtu3_fifo_info *fifo;
 264
 265        struct list_head req_list;
 266        struct mtu3_gpd_ring gpd_ring;
 267        const struct usb_ss_ep_comp_descriptor *comp_desc;
 268        const struct usb_endpoint_descriptor *desc;
 269
 270        int flags;
 271};
 272
 273struct mtu3_request {
 274        struct usb_request request;
 275        struct list_head list;
 276        struct mtu3_ep *mep;
 277        struct mtu3 *mtu;
 278        struct qmu_gpd *gpd;
 279        int epnum;
 280};
 281
 282static inline struct ssusb_mtk *dev_to_ssusb(struct udevice *dev)
 283{
 284        return dev_get_priv(dev);
 285}
 286
 287/**
 288 * struct mtu3 - device driver instance data.
 289 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
 290 *              MTU3_U3_IP_SLOT_DEFAULT for U3 IP
 291 * @may_wakeup: means device's remote wakeup is enabled
 292 * @is_self_powered: is reported in device status and the config descriptor
 293 * @delayed_status: true when function drivers ask for delayed status
 294 * @gen2cp: compatible with USB3 Gen2 IP
 295 * @ep0_req: dummy request used while handling standard USB requests
 296 *              for GET_STATUS and SET_SEL
 297 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
 298 */
 299struct mtu3 {
 300        spinlock_t lock;
 301        struct ssusb_mtk *ssusb;
 302        struct udevice *dev;
 303        void __iomem *mac_base;
 304        void __iomem *ippc_base;
 305        int irq;
 306
 307        struct mtu3_fifo_info tx_fifo;
 308        struct mtu3_fifo_info rx_fifo;
 309
 310        struct mtu3_ep *ep_array;
 311        struct mtu3_ep *in_eps;
 312        struct mtu3_ep *out_eps;
 313        struct mtu3_ep *ep0;
 314        int num_eps;
 315        int slot;
 316        int active_ep;
 317
 318        enum mtu3_g_ep0_state ep0_state;
 319        struct usb_gadget g;    /* the gadget */
 320        struct usb_gadget_driver *gadget_driver;
 321        struct mtu3_request ep0_req;
 322        u8 setup_buf[EP0_RESPONSE_BUF];
 323        enum usb_device_speed max_speed;
 324        enum usb_device_speed speed;
 325
 326        unsigned is_active:1;
 327        unsigned may_wakeup:1;
 328        unsigned is_self_powered:1;
 329        unsigned test_mode:1;
 330        unsigned softconnect:1;
 331        unsigned u1_enable:1;
 332        unsigned u2_enable:1;
 333        unsigned is_u3_ip:1;
 334        unsigned delayed_status:1;
 335        unsigned gen2cp:1;
 336        unsigned force_vbus:1;
 337
 338        u8 address;
 339        u8 test_mode_nr;
 340        u32 hw_version;
 341};
 342
 343static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
 344{
 345        return container_of(g, struct mtu3, g);
 346}
 347
 348static inline int is_first_entry(const struct list_head *list,
 349                                 const struct list_head *head)
 350{
 351        return list_is_last(head, list);
 352}
 353
 354static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
 355{
 356        return req ? container_of(req, struct mtu3_request, request) : NULL;
 357}
 358
 359static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
 360{
 361        return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
 362}
 363
 364static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
 365{
 366        if (list_empty(&mep->req_list))
 367                return NULL;
 368
 369        return list_first_entry(&mep->req_list, struct mtu3_request, list);
 370}
 371
 372static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
 373{
 374        writel(data, base + offset);
 375}
 376
 377static inline u32 mtu3_readl(void __iomem *base, u32 offset)
 378{
 379        return readl(base + offset);
 380}
 381
 382static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
 383{
 384        void __iomem *addr = base + offset;
 385        u32 tmp = readl(addr);
 386
 387        writel((tmp | (bits)), addr);
 388}
 389
 390static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
 391{
 392        void __iomem *addr = base + offset;
 393        u32 tmp = readl(addr);
 394
 395        writel((tmp & ~(bits)), addr);
 396}
 397
 398int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
 399struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
 400void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
 401void mtu3_req_complete(struct mtu3_ep *mep,
 402                       struct usb_request *req, int status);
 403
 404int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
 405                   int interval, int burst, int mult);
 406void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
 407void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
 408void mtu3_ep0_setup(struct mtu3 *mtu);
 409void mtu3_start(struct mtu3 *mtu);
 410void mtu3_stop(struct mtu3 *mtu);
 411void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
 412void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed);
 413
 414int mtu3_gadget_setup(struct mtu3 *mtu);
 415void mtu3_gadget_cleanup(struct mtu3 *mtu);
 416void mtu3_gadget_reset(struct mtu3 *mtu);
 417void mtu3_gadget_suspend(struct mtu3 *mtu);
 418void mtu3_gadget_resume(struct mtu3 *mtu);
 419void mtu3_gadget_disconnect(struct mtu3 *mtu);
 420
 421irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
 422extern const struct usb_ep_ops mtu3_ep0_ops;
 423
 424#endif
 425