LXR uboot/drivers/watchdog/mtk

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Watchdog driver for MediaTek SoCs
   4 *
   5 * Copyright (C) 2018 MediaTek Inc.
   6 * Author: Ryder Lee <ryder.lee@mediatek.com>
   7 */
   8
   9#include <common.h>
  10#include <dm.h>
  11#include <hang.h>
  12#include <wdt.h>
  13#include <asm/io.h>
  14#include <linux/bitops.h>
  15
  16#define MTK_WDT_MODE                    0x00
  17#define MTK_WDT_LENGTH                  0x04
  18#define MTK_WDT_RESTART                 0x08
  19#define MTK_WDT_STATUS                  0x0c
  20#define MTK_WDT_INTERVAL                0x10
  21#define MTK_WDT_SWRST                   0x14
  22#define MTK_WDT_REQ_MODE                0x30
  23#define MTK_WDT_DEBUG_CTL               0x40
  24
  25#define WDT_MODE_KEY                    (0x22 << 24)
  26#define WDT_MODE_EN                     BIT(0)
  27#define WDT_MODE_EXTPOL                 BIT(1)
  28#define WDT_MODE_EXTEN                  BIT(2)
  29#define WDT_MODE_IRQ_EN                 BIT(3)
  30#define WDT_MODE_DUAL_EN                BIT(6)
  31
  32#define WDT_LENGTH_KEY                  0x8
  33#define WDT_LENGTH_TIMEOUT(n)           ((n) << 5)
  34
  35#define WDT_RESTART_KEY                 0x1971
  36#define WDT_SWRST_KEY                   0x1209
  37
  38struct mtk_wdt_priv {
  39        void __iomem *base;
  40};
  41
  42static int mtk_wdt_reset(struct udevice *dev)
  43{
  44        struct mtk_wdt_priv *priv = dev_get_priv(dev);
  45
  46        /* Reload watchdog duration */
  47        writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
  48
  49        return 0;
  50}
  51
  52static int mtk_wdt_stop(struct udevice *dev)
  53{
  54        struct mtk_wdt_priv *priv = dev_get_priv(dev);
  55
  56        clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
  57
  58        return 0;
  59}
  60
  61static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
  62{
  63        struct mtk_wdt_priv *priv = dev_get_priv(dev);
  64
  65        /* Kick watchdog to prevent counter == 0 */
  66        writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
  67
  68        /* Reset */
  69        writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
  70        hang();
  71
  72        return 0;
  73}
  74
  75static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
  76{
  77        struct mtk_wdt_priv *priv = dev_get_priv(dev);
  78        u64 timeout_us;
  79        u32 timeout_cc;
  80        u32 length;
  81
  82        /*
  83         * One WDT_LENGTH count is 512 ticks of the wdt clock
  84         * Clock runs at 32768 Hz
  85         * e.g. 15.625 ms per count (nominal)
  86         * We want the ceiling after dividing timeout_ms by 15.625 ms
  87         * We add 15624 prior to the divide to implement the ceiling
  88         * We prevent over-flow by clamping the timeout_ms value here
  89         *  as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec
  90         * We also enforce a minimum of 1 count
  91         * Many watchdog peripherals have a self-imposed count of 1
  92         *  that is added to the register counts.
  93         *  The MediaTek docs lack details to know if this is the case here.
  94         *  So we enforce a minimum of 1 to guarantee operation.
  95         */
  96        if (timeout_ms > 15984)
  97                timeout_ms = 15984;
  98
  99        timeout_us = timeout_ms * 1000;
 100        timeout_cc = (15624 + timeout_us) / 15625;
 101        if (timeout_cc == 0)
 102                timeout_cc = 1;
 103
 104        length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
 105        writel(length, priv->base + MTK_WDT_LENGTH);
 106}
 107
 108static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 109{
 110        struct mtk_wdt_priv *priv = dev_get_priv(dev);
 111
 112        mtk_wdt_set_timeout(dev, timeout_ms);
 113
 114        mtk_wdt_reset(dev);
 115
 116        /* Enable watchdog reset signal */
 117        setbits_le32(priv->base + MTK_WDT_MODE,
 118                     WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
 119
 120        return 0;
 121}
 122
 123static int mtk_wdt_probe(struct udevice *dev)
 124{
 125        struct mtk_wdt_priv *priv = dev_get_priv(dev);
 126
 127        priv->base = dev_read_addr_ptr(dev);
 128        if (!priv->base)
 129                return -ENOENT;
 130
 131        /* Clear status */
 132        clrsetbits_le32(priv->base + MTK_WDT_MODE,
 133                        WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
 134
 135        return mtk_wdt_stop(dev);
 136}
 137
 138static const struct wdt_ops mtk_wdt_ops = {
 139        .start = mtk_wdt_start,
 140        .reset = mtk_wdt_reset,
 141        .stop = mtk_wdt_stop,
 142        .expire_now = mtk_wdt_expire_now,
 143};
 144
 145static const struct udevice_id mtk_wdt_ids[] = {
 146        { .compatible = "mediatek,wdt"},
 147        { .compatible = "mediatek,mt6589-wdt"},
 148        { .compatible = "mediatek,mt7986-wdt" },
 149        {}
 150};
 151
 152U_BOOT_DRIVER(mtk_wdt) = {
 153        .name = "mtk_wdt",
 154        .id = UCLASS_WDT,
 155        .of_match = mtk_wdt_ids,
 156        .priv_auto      = sizeof(struct mtk_wdt_priv),
 157        .probe = mtk_wdt_probe,
 158        .ops = &mtk_wdt_ops,
 159        .flags = DM_FLAG_PRE_RELOC,
 160};
 161