1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the esd TASREG board. 4 * 5 * (C) Copyright 2004 6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5249EVB_H 14#define _M5249EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CFG_SYS_UART_PORT (0) 22 23/* 24 * Clock configuration: enable only one of the following options 25 */ 26 27#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 28#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 29#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 30 31/* 32 * Low Level Configuration Settings 33 * (address mappings, register initial values, etc.) 34 * You should know what you are doing if you make changes here. 35 */ 36 37#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 38#define CFG_SYS_MBAR2 0x80000000 39 40/*----------------------------------------------------------------------- 41 * Definitions for initial stack pointer and data area (in DPRAM) 42 */ 43#define CFG_SYS_INIT_RAM_ADDR 0x20000000 44#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 45 46#define LDS_BOARD_TEXT \ 47 . = DEFINED(env_offset) ? env_offset : .; \ 48 env/embedded.o(.text); 49 50/*----------------------------------------------------------------------- 51 * Start addresses for the final memory configuration 52 * (Set up by the startup code) 53 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 54 */ 55#define CFG_SYS_SDRAM_BASE 0x00000000 56#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 57#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) 58 59#if 0 /* test-only */ 60#define CFG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 61#endif 62 63/* 64 * For booting Linux, the board info and command line data 65 * have to be in the first 8 MB of memory, since this is 66 * the maximum mapped by the Linux kernel during initialization ?? 67 */ 68#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) 69 70/*----------------------------------------------------------------------- 71 * FLASH organization 72 */ 73#ifdef CONFIG_SYS_FLASH_CFI 74 75# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 76# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } 77#endif 78 79/*----------------------------------------------------------------------- 80 * Cache Configuration 81 */ 82 83#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 84 CFG_SYS_INIT_RAM_SIZE - 8) 85#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 86 CFG_SYS_INIT_RAM_SIZE - 4) 87#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) 88#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ 89 CF_ADDRMASK(2) | \ 90 CF_ACR_EN | CF_ACR_SM_ALL) 91#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ 92 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ 93 CF_ACR_EN | CF_ACR_SM_ALL) 94#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 95 CF_CACR_DBWE) 96 97/*----------------------------------------------------------------------- 98 * Memory bank definitions 99 */ 100 101/* CS0 - AMD Flash, address 0xffc00000 */ 102#define CFG_SYS_CS0_BASE 0xffe00000 103#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 104/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 105#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 106 107/* CS1 - FPGA, address 0xe0000000 */ 108#define CFG_SYS_CS1_BASE 0xe0000000 109#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 110#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 111 112/*----------------------------------------------------------------------- 113 * Port configuration 114 */ 115#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 116#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 117#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 118#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 119#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 120#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 121#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ 122 123 124#endif /* M5249 */ 125