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7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12
13#define DDR_SDRAM_CFG 0x470c0008
14#define DDR_CS0_BNDS 0x008000bf
15#define DDR_CS0_CONFIG 0x80014302
16#define DDR_TIMING_CFG_0 0x50550004
17#define DDR_TIMING_CFG_1 0xbcb38c56
18#define DDR_TIMING_CFG_2 0x0040d120
19#define DDR_TIMING_CFG_3 0x010e1000
20#define DDR_TIMING_CFG_4 0x00000001
21#define DDR_TIMING_CFG_5 0x03401400
22#define DDR_SDRAM_CFG_2 0x00401010
23#define DDR_SDRAM_MODE 0x00061c60
24#define DDR_SDRAM_MODE_2 0x00180000
25#define DDR_SDRAM_INTERVAL 0x18600618
26#define DDR_DDR_WRLVL_CNTL 0x8655f605
27#define DDR_DDR_WRLVL_CNTL_2 0x05060607
28#define DDR_DDR_WRLVL_CNTL_3 0x05050505
29#define DDR_DDR_CDR1 0x80040000
30#define DDR_DDR_CDR2 0x00000001
31#define DDR_SDRAM_CLK_CNTL 0x02000000
32#define DDR_DDR_ZQ_CNTL 0x89080600
33#define DDR_CS0_CONFIG_2 0
34#define DDR_SDRAM_CFG_MEM_EN 0x80000000
35#define SDRAM_CFG2_D_INIT 0x00000010
36#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
37#define SDRAM_CFG2_FRC_SR 0x80000000
38#define SDRAM_CFG_BI 0x00000001
39
40#define PHYS_SDRAM 0x80000000
41#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
42
43#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
44#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
45
46
47
48
49#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
50#define CFG_SYS_FLASH_BASE 0x60000000
51#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
52
53#define CFG_SYS_NOR0_CSPR_EXT (0x0)
54#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
55 CSPR_PORT_SIZE_16 | \
56 CSPR_MSEL_NOR | \
57 CSPR_V)
58#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
59
60
61#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
62 CSOR_NOR_TRHZ_80)
63#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
64 FTIM0_NOR_TEADC(0x5) | \
65 FTIM0_NOR_TAVDS(0x0) | \
66 FTIM0_NOR_TEAHC(0x5))
67#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
68 FTIM1_NOR_TRAD_NOR(0x1A) | \
69 FTIM1_NOR_TSEQRAD_NOR(0x13))
70#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
71 FTIM2_NOR_TCH(0x4) | \
72 FTIM2_NOR_TWP(0x1c) | \
73 FTIM2_NOR_TWPH(0x0e))
74#define CFG_SYS_NOR_FTIM3 0
75
76#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
77
78#define CFG_SYS_WRITE_SWAPPED_DATA
79#endif
80
81
82
83#define CFG_SYS_CPLD_BASE 0x7fb00000
84#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
85
86#define CFG_SYS_FPGA_CSPR_EXT (0x0)
87#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
88 CSPR_PORT_SIZE_8 | \
89 CSPR_MSEL_GPCM | \
90 CSPR_V)
91#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
92#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
93 CSOR_NOR_NOR_MODE_AVD_NOR | \
94 CSOR_NOR_TRHZ_80)
95
96
97#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
98 FTIM0_GPCM_TEADC(0xf) | \
99 FTIM0_GPCM_TEAHC(0xf))
100#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
101 FTIM1_GPCM_TRAD(0x3f))
102#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
103 FTIM2_GPCM_TCH(0xf) | \
104 FTIM2_GPCM_TWP(0xff))
105#define CFG_SYS_FPGA_FTIM3 0x0
106#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
107#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
108#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
109#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
110#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
111#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
112#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
113#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
114#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT
115#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR
116#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK
117#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR
118#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0
119#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1
120#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2
121#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
122
123
124
125
126#ifndef CONFIG_LPUART
127#define CFG_SYS_NS16550_CLK get_serial_clock()
128#endif
129
130
131
132
133
134
135
136#define CFG_SMP_PEN_ADDR 0x01ee0200
137
138#define HWCONFIG_BUFFER_SIZE 256
139
140#define BOOT_TARGET_DEVICES(func) \
141 func(MMC, mmc, 0) \
142 func(USB, usb, 0) \
143 func(DHCP, dhcp, na)
144#include <config_distro_bootcmd.h>
145
146#ifdef CONFIG_LPUART
147#define CFG_EXTRA_ENV_SETTINGS \
148 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
149 "cma=64M@0x0-0xb0000000\0" \
150 "initrd_high=0xffffffff\0" \
151 "kernel_addr=0x65000000\0" \
152 "scriptaddr=0x80000000\0" \
153 "scripthdraddr=0x80080000\0" \
154 "fdtheader_addr_r=0x80100000\0" \
155 "kernelheader_addr_r=0x80200000\0" \
156 "kernel_addr_r=0x81000000\0" \
157 "fdt_addr_r=0x90000000\0" \
158 "ramdisk_addr_r=0xa0000000\0" \
159 "load_addr=0xa0000000\0" \
160 "kernel_size=0x2800000\0" \
161 "kernel_addr_sd=0x8000\0" \
162 "kernel_size_sd=0x14000\0" \
163 "othbootargs=cma=64M@0x0-0xb0000000\0" \
164 BOOTENV \
165 "boot_scripts=ls1021atwr_boot.scr\0" \
166 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
167 "scan_dev_for_boot_part=" \
168 "part list ${devtype} ${devnum} devplist; " \
169 "env exists devplist || setenv devplist 1; " \
170 "for distro_bootpart in ${devplist}; do " \
171 "if fstype ${devtype} " \
172 "${devnum}:${distro_bootpart} " \
173 "bootfstype; then " \
174 "run scan_dev_for_boot; " \
175 "fi; " \
176 "done\0" \
177 "scan_dev_for_boot=" \
178 "echo Scanning ${devtype} " \
179 "${devnum}:${distro_bootpart}...; " \
180 "for prefix in ${boot_prefixes}; do " \
181 "run scan_dev_for_scripts; " \
182 "done;" \
183 "\0" \
184 "boot_a_script=" \
185 "load ${devtype} ${devnum}:${distro_bootpart} " \
186 "${scriptaddr} ${prefix}${script}; " \
187 "env exists secureboot && load ${devtype} " \
188 "${devnum}:${distro_bootpart} " \
189 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
190 "env exists secureboot " \
191 "&& esbc_validate ${scripthdraddr};" \
192 "source ${scriptaddr}\0" \
193 "installer=load mmc 0:2 $load_addr " \
194 "/flex_installer_arm32.itb; " \
195 "bootm $load_addr#ls1021atwr\0" \
196 "qspi_bootcmd=echo Trying load from qspi..;" \
197 "sf probe && sf read $load_addr " \
198 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
199 "nor_bootcmd=echo Trying load from nor..;" \
200 "cp.b $kernel_addr $load_addr " \
201 "$kernel_size && bootm $load_addr#$board\0"
202#else
203#define CFG_EXTRA_ENV_SETTINGS \
204 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
205 "cma=64M@0x0-0xb0000000\0" \
206 "initrd_high=0xffffffff\0" \
207 "kernel_addr=0x61000000\0" \
208 "kernelheader_addr=0x60800000\0" \
209 "scriptaddr=0x80000000\0" \
210 "scripthdraddr=0x80080000\0" \
211 "fdtheader_addr_r=0x80100000\0" \
212 "kernelheader_addr_r=0x80200000\0" \
213 "kernel_addr_r=0x81000000\0" \
214 "kernelheader_size=0x40000\0" \
215 "fdt_addr_r=0x90000000\0" \
216 "ramdisk_addr_r=0xa0000000\0" \
217 "load_addr=0xa0000000\0" \
218 "kernel_size=0x2800000\0" \
219 "kernel_addr_sd=0x8000\0" \
220 "kernel_size_sd=0x14000\0" \
221 "kernelhdr_addr_sd=0x4000\0" \
222 "kernelhdr_size_sd=0x10\0" \
223 "othbootargs=cma=64M@0x0-0xb0000000\0" \
224 BOOTENV \
225 "boot_scripts=ls1021atwr_boot.scr\0" \
226 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
227 "scan_dev_for_boot_part=" \
228 "part list ${devtype} ${devnum} devplist; " \
229 "env exists devplist || setenv devplist 1; " \
230 "for distro_bootpart in ${devplist}; do " \
231 "if fstype ${devtype} " \
232 "${devnum}:${distro_bootpart} " \
233 "bootfstype; then " \
234 "run scan_dev_for_boot; " \
235 "fi; " \
236 "done\0" \
237 "scan_dev_for_boot=" \
238 "echo Scanning ${devtype} " \
239 "${devnum}:${distro_bootpart}...; " \
240 "for prefix in ${boot_prefixes}; do " \
241 "run scan_dev_for_scripts; " \
242 "done;" \
243 "\0" \
244 "boot_a_script=" \
245 "load ${devtype} ${devnum}:${distro_bootpart} " \
246 "${scriptaddr} ${prefix}${script}; " \
247 "env exists secureboot && load ${devtype} " \
248 "${devnum}:${distro_bootpart} " \
249 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
250 "&& esbc_validate ${scripthdraddr};" \
251 "source ${scriptaddr}\0" \
252 "qspi_bootcmd=echo Trying load from qspi..;" \
253 "sf probe && sf read $load_addr " \
254 "$kernel_addr $kernel_size; env exists secureboot " \
255 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
256 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
257 "bootm $load_addr#$board\0" \
258 "nor_bootcmd=echo Trying load from nor..;" \
259 "cp.b $kernel_addr $load_addr " \
260 "$kernel_size; env exists secureboot " \
261 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
262 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
263 "bootm $load_addr#$board\0" \
264 "sd_bootcmd=echo Trying load from SD ..;" \
265 "mmcinfo && mmc read $load_addr " \
266 "$kernel_addr_sd $kernel_size_sd && " \
267 "env exists secureboot && mmc read $kernelheader_addr_r " \
268 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
269 " && esbc_validate ${kernelheader_addr_r};" \
270 "bootm $load_addr#$board\0"
271#endif
272
273
274
275
276#define CFG_SYS_BOOTMAPSZ (256 << 20)
277
278
279
280
281
282#include <asm/fsl_secure_boot.h>
283
284#endif
285
