1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2008 4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 5 * 6 * Wolfgang Denk <wd@denx.de> 7 * Copyright 2004 Freescale Semiconductor. 8 * (C) Copyright 2002,2003 Motorola,Inc. 9 * Xianghua Xiao <X.Xiao@motorola.com> 10 */ 11 12/* 13 * Socrates 14 */ 15 16#ifndef __CONFIG_H 17#define __CONFIG_H 18 19/* 20 * Only possible on E500 Version 2 or newer cores. 21 */ 22 23/* 24 * sysclk for MPC85xx 25 * 26 * Two valid values are: 27 * 33000000 28 * 66000000 29 * 30 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 31 * is likely the desired value here, so that is now the default. 32 * The board, however, can run at 66MHz. In any event, this value 33 * must match the settings of some switches. Details can be found 34 * in the README.mpc85xxads. 35 */ 36 37#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 38 39#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ 40 41#define CFG_SYS_CCSRBAR 0xE0000000 42#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR 43 44/* DDR Setup */ 45#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 46#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 47 48/* I2C addresses of SPD EEPROMs */ 49#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 50 51 52/* Hardcoded values, to use instead of SPD */ 53#define CFG_SYS_DDR_CS0_BNDS 0x0000000f 54#define CFG_SYS_DDR_CS0_CONFIG 0x80010102 55#define CFG_SYS_DDR_TIMING_0 0x00260802 56#define CFG_SYS_DDR_TIMING_1 0x3935D322 57#define CFG_SYS_DDR_TIMING_2 0x14904CC8 58#define CFG_SYS_DDR_MODE 0x00480432 59#define CFG_SYS_DDR_INTERVAL 0x030C0100 60#define CFG_SYS_DDR_CONFIG_2 0x04400000 61#define CFG_SYS_DDR_CONFIG 0xC3008000 62#define CFG_SYS_DDR_CLK_CONTROL 0x03800000 63#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ 64 65/* 66 * Flash on the LocalBus 67 */ 68#define CFG_SYS_FLASH0 0xFE000000 69#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH0 } 70 71#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH0 /* Localbus flash start */ 72#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */ 73 74#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 75#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 76#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 77#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 78 79#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 80#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 81 82#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 83 84/* FPGA and NAND */ 85#define CFG_SYS_FPGA_BASE 0xc0000000 86#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 87 88#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70) 89 90/* LIME GDC */ 91#define CFG_SYS_LIME_BASE 0xc8000000 92 93/* 94 * General PCI 95 * Memory space is mapped 1-1. 96 */ 97 98#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 99#define CFG_SYS_PCI1_IO_PHYS 0xE2000000 100 101/* 102 * Miscellaneous configurable options 103 */ 104 105/* 106 * For booting Linux, the board info and command line data 107 * have to be in the first 8 MB of memory, since this is 108 * the maximum mapped by the Linux kernel during initialization. 109 */ 110#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 111 112#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" 113 114/* pass open firmware flat tree */ 115 116#endif /* __CONFIG_H */ 117