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13#ifndef __MPCXX_H__
14#define __MPCXX_H__
15
16
17
18
19
20#define EXC_OFF_SYS_RESET 0x0100
21#define _START_OFFSET EXC_OFF_SYS_RESET
22
23
24
25
26#define SYPCR_SWTC 0xFFFF0000
27#define SYPCR_BMT 0x0000FF00
28#define SYPCR_BME 0x00000080
29#define SYPCR_SWF 0x00000008
30#define SYPCR_SWE 0x00000004
31#define SYPCR_SWRI 0x00000002
32#define SYPCR_SWP 0x00000001
33
34
35
36
37#define SIUMCR_EARB 0x80000000
38#define SIUMCR_EARP0 0x00000000
39#define SIUMCR_EARP1 0x10000000
40#define SIUMCR_EARP2 0x20000000
41#define SIUMCR_EARP3 0x30000000
42#define SIUMCR_EARP4 0x40000000
43#define SIUMCR_EARP5 0x50000000
44#define SIUMCR_EARP6 0x60000000
45#define SIUMCR_EARP7 0x70000000
46#define SIUMCR_DSHW 0x00800000
47#define SIUMCR_DBGC00 0x00000000
48#define SIUMCR_DBGC01 0x00200000
49#define SIUMCR_DBGC10 0x00400000
50#define SIUMCR_DBGC11 0x00600000
51#define SIUMCR_DBPC00 0x00000000
52#define SIUMCR_DBPC01 0x00080000
53#define SIUMCR_DBPC10 0x00100000
54#define SIUMCR_DBPC11 0x00180000
55#define SIUMCR_FRC 0x00020000
56#define SIUMCR_DLK 0x00010000
57#define SIUMCR_PNCS 0x00008000
58#define SIUMCR_OPAR 0x00004000
59#define SIUMCR_DPC 0x00002000
60#define SIUMCR_MPRE 0x00001000
61#define SIUMCR_MLRC00 0x00000000
62#define SIUMCR_MLRC01 0x00000400
63#define SIUMCR_MLRC10 0x00000800
64#define SIUMCR_MLRC11 0x00000C00
65#define SIUMCR_AEME 0x00000200
66#define SIUMCR_SEME 0x00000100
67#define SIUMCR_BSC 0x00000080
68#define SIUMCR_GB5E 0x00000040
69#define SIUMCR_B2DD 0x00000020
70#define SIUMCR_B3DD 0x00000010
71
72
73
74
75#define TBSCR_TBIRQ7 0x8000
76#define TBSCR_TBIRQ6 0x4000
77#define TBSCR_TBIRQ5 0x2000
78#define TBSCR_TBIRQ4 0x1000
79#define TBSCR_TBIRQ3 0x0800
80#define TBSCR_TBIRQ2 0x0400
81#define TBSCR_TBIRQ1 0x0200
82#define TBSCR_TBIRQ0 0x0100
83#if 0
84#define TBSCR_REFA 0x0080
85#define TBSCR_REFB 0x0040
86#define TBSCR_REFAE 0x0008
87#define TBSCR_REFBE 0x0004
88#define TBSCR_TBF 0x0002
89#define TBSCR_TBE 0x0001
90#endif
91
92
93
94
95#undef PISCR_PIRQ
96#define PISCR_PITF 0x0002
97#if 0
98#define PISCR_PS 0x0080
99#define PISCR_PIE 0x0004
100#define PISCR_PTE 0x0001
101#endif
102
103
104
105
106#define RSR_JTRS 0x01000000
107#define RSR_DBSRS 0x02000000
108#define RSR_DBHRS 0x04000000
109#define RSR_CSRS 0x08000000
110#define RSR_SWRS 0x10000000
111#define RSR_LLRS 0x20000000
112#define RSR_ESRS 0x40000000
113#define RSR_EHRS 0x80000000
114
115#define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
116
117
118
119
120
121#define MPC8xx_NEW_CLK 0x0800
122
123
124
125
126
127#define PLPRCR_MFN_MSK 0xF8000000
128#define PLPRCR_MFN_SHIFT 27
129#define PLPRCR_MFD_MSK 0x07C00000
130#define PLPRCR_MFD_SHIFT 22
131#define PLPRCR_S_MSK 0x00300000
132#define PLPRCR_S_SHIFT 20
133#define PLPRCR_MFI_MSK 0x000F0000
134#define PLPRCR_MFI_SHIFT 16
135
136#define PLPRCR_PDF_MSK 0x0000001E
137#define PLPRCR_PDF_SHIFT 1
138#define PLPRCR_DBRMO 0x00000001
139
140
141#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
142 PLPRCR_MFD_MSK | \
143 PLPRCR_S_MSK | \
144 PLPRCR_MFI_MSK | \
145 PLPRCR_PDF_MSK)
146
147
148#define PLPRCR_TEXPS 0x00004000
149#define PLPRCR_CSRC 0x00000400
150
151#define PLPRCR_CSR 0x00000080
152#define PLPRCR_LOLRE 0x00000040
153#define PLPRCR_FIOPD 0x00000020
154
155
156
157
158#define SCCR_COM00 0x00000000
159#define SCCR_COM01 0x20000000
160#define SCCR_COM10 0x40000000
161#define SCCR_COM11 0x60000000
162#define SCCR_TBS 0x02000000
163#define SCCR_RTDIV 0x01000000
164#define SCCR_RTSEL 0x00800000
165#define SCCR_CRQEN 0x00400000
166#define SCCR_PRQEN 0x00200000
167#define SCCR_EBDF00 0x00000000
168#define SCCR_EBDF01 0x00020000
169#define SCCR_EBDF10 0x00040000
170#define SCCR_EBDF11 0x00060000
171#define SCCR_DFSYNC00 0x00000000
172#define SCCR_DFSYNC01 0x00002000
173#define SCCR_DFSYNC10 0x00004000
174#define SCCR_DFSYNC11 0x00006000
175#define SCCR_DFBRG00 0x00000000
176#define SCCR_DFBRG01 0x00000800
177#define SCCR_DFBRG10 0x00001000
178#define SCCR_DFBRG11 0x00001800
179#define SCCR_DFNL000 0x00000000
180#define SCCR_DFNL001 0x00000100
181#define SCCR_DFNL010 0x00000200
182#define SCCR_DFNL011 0x00000300
183#define SCCR_DFNL100 0x00000400
184#define SCCR_DFNL101 0x00000500
185#define SCCR_DFNL110 0x00000600
186#define SCCR_DFNL111 0x00000700
187#define SCCR_DFNH000 0x00000000
188#define SCCR_DFNH110 0x000000D0
189#define SCCR_DFNH111 0x000000E0
190#define SCCR_DFLCD000 0x00000000
191#define SCCR_DFLCD001 0x00000004
192#define SCCR_DFLCD010 0x00000008
193#define SCCR_DFLCD011 0x0000000C
194#define SCCR_DFLCD100 0x00000010
195#define SCCR_DFLCD101 0x00000014
196#define SCCR_DFLCD110 0x00000018
197#define SCCR_DFLCD111 0x0000001C
198#define SCCR_DFALCD00 0x00000000
199#define SCCR_DFALCD01 0x00000001
200#define SCCR_DFALCD10 0x00000002
201#define SCCR_DFALCD11 0x00000003
202
203
204
205
206
207#define BR_BA_MSK 0xFFFF8000
208#define BR_AT_MSK 0x00007000
209#define BR_PS_MSK 0x00000C00
210#define BR_PS_32 0x00000000
211#define BR_PS_16 0x00000800
212#define BR_PS_8 0x00000400
213#define BR_PARE 0x00000200
214#define BR_WP 0x00000100
215#define BR_MS_MSK 0x000000C0
216#define BR_MS_GPCM 0x00000000
217#define BR_MS_UPMA 0x00000080
218#define BR_MS_UPMB 0x000000C0
219#define BR_V 0x00000001
220
221
222
223
224#define OR_AM_MSK 0xFFFF8000
225#define OR_ATM_MSK 0x00007000
226#define OR_CSNT_SAM 0x00000800
227
228#define OR_ACS_MSK 0x00000600
229#define OR_ACS_DIV1 0x00000000
230#define OR_ACS_DIV4 0x00000400
231#define OR_ACS_DIV2 0x00000600
232#define OR_G5LA 0x00000400
233#define OR_G5LS 0x00000200
234#define OR_BI 0x00000100
235#define OR_SCY_MSK 0x000000F0
236#define OR_SCY_0_CLK 0x00000000
237#define OR_SCY_1_CLK 0x00000010
238#define OR_SCY_2_CLK 0x00000020
239#define OR_SCY_3_CLK 0x00000030
240#define OR_SCY_4_CLK 0x00000040
241#define OR_SCY_5_CLK 0x00000050
242#define OR_SCY_6_CLK 0x00000060
243#define OR_SCY_7_CLK 0x00000070
244#define OR_SCY_8_CLK 0x00000080
245#define OR_SCY_9_CLK 0x00000090
246#define OR_SCY_10_CLK 0x000000A0
247#define OR_SCY_11_CLK 0x000000B0
248#define OR_SCY_12_CLK 0x000000C0
249#define OR_SCY_13_CLK 0x000000D0
250#define OR_SCY_14_CLK 0x000000E0
251#define OR_SCY_15_CLK 0x000000F0
252#define OR_SETA 0x00000008
253#define OR_TRLX 0x00000004
254#define OR_EHTR 0x00000002
255
256
257
258
259
260#define MPTPR_PTP_MSK 0xFF00
261#define MPTPR_PTP_DIV2 0x2000
262#define MPTPR_PTP_DIV4 0x1000
263#define MPTPR_PTP_DIV8 0x0800
264#define MPTPR_PTP_DIV16 0x0400
265#define MPTPR_PTP_DIV32 0x0200
266#define MPTPR_PTP_DIV64 0x0100
267
268
269
270
271#define MCR_OP_WRITE 0x00000000
272#define MCR_OP_READ 0x40000000
273#define MCR_OP_RUN 0x80000000
274#define MCR_UPM_A 0x00000000
275#define MCR_UPM_B 0x00800000
276#define MCR_MB_CS0 0x00000000
277#define MCR_MB_CS1 0x00002000
278#define MCR_MB_CS2 0x00004000
279#define MCR_MB_CS3 0x00006000
280#define MCR_MB_CS4 0x00008000
281#define MCR_MB_CS5 0x0000A000
282#define MCR_MB_CS6 0x0000C000
283#define MCR_MB_CS7 0x0000E000
284#define MCR_MLCF(n) (((n)&0xF)<<8)
285#define MCR_MAD(addr) ((addr)&0x3F)
286
287
288
289
290#define MAMR_PTA_MSK 0xFF000000
291#define MAMR_PTA_SHIFT 0x00000018
292#define MAMR_PTAE 0x00800000
293#define MAMR_AMA_MSK 0x00700000
294#define MAMR_AMA_TYPE_0 0x00000000
295#define MAMR_AMA_TYPE_1 0x00100000
296#define MAMR_AMA_TYPE_2 0x00200000
297#define MAMR_AMA_TYPE_3 0x00300000
298#define MAMR_AMA_TYPE_4 0x00400000
299#define MAMR_AMA_TYPE_5 0x00500000
300#define MAMR_DSA_MSK 0x00060000
301#define MAMR_DSA_1_CYCL 0x00000000
302#define MAMR_DSA_2_CYCL 0x00020000
303#define MAMR_DSA_3_CYCL 0x00040000
304#define MAMR_DSA_4_CYCL 0x00060000
305#define MAMR_G0CLA_MSK 0x0000E000
306#define MAMR_G0CLA_A12 0x00000000
307#define MAMR_G0CLA_A11 0x00002000
308#define MAMR_G0CLA_A10 0x00004000
309#define MAMR_G0CLA_A9 0x00006000
310#define MAMR_G0CLA_A8 0x00008000
311#define MAMR_G0CLA_A7 0x0000A000
312#define MAMR_G0CLA_A6 0x0000C000
313#define MAMR_G0CLA_A5 0x0000E000
314#define MAMR_GPL_A4DIS 0x00001000
315#define MAMR_RLFA_MSK 0x00000F00
316#define MAMR_RLFA_1X 0x00000100
317#define MAMR_RLFA_2X 0x00000200
318#define MAMR_RLFA_3X 0x00000300
319#define MAMR_RLFA_4X 0x00000400
320#define MAMR_RLFA_5X 0x00000500
321#define MAMR_RLFA_6X 0x00000600
322#define MAMR_RLFA_7X 0x00000700
323#define MAMR_RLFA_8X 0x00000800
324#define MAMR_RLFA_9X 0x00000900
325#define MAMR_RLFA_10X 0x00000A00
326#define MAMR_RLFA_11X 0x00000B00
327#define MAMR_RLFA_12X 0x00000C00
328#define MAMR_RLFA_13X 0x00000D00
329#define MAMR_RLFA_14X 0x00000E00
330#define MAMR_RLFA_15X 0x00000F00
331#define MAMR_RLFA_16X 0x00000000
332#define MAMR_WLFA_MSK 0x000000F0
333#define MAMR_WLFA_1X 0x00000010
334#define MAMR_WLFA_2X 0x00000020
335#define MAMR_WLFA_3X 0x00000030
336#define MAMR_WLFA_4X 0x00000040
337#define MAMR_WLFA_5X 0x00000050
338#define MAMR_WLFA_6X 0x00000060
339#define MAMR_WLFA_7X 0x00000070
340#define MAMR_WLFA_8X 0x00000080
341#define MAMR_WLFA_9X 0x00000090
342#define MAMR_WLFA_10X 0x000000A0
343#define MAMR_WLFA_11X 0x000000B0
344#define MAMR_WLFA_12X 0x000000C0
345#define MAMR_WLFA_13X 0x000000D0
346#define MAMR_WLFA_14X 0x000000E0
347#define MAMR_WLFA_15X 0x000000F0
348#define MAMR_WLFA_16X 0x00000000
349#define MAMR_TLFA_MSK 0x0000000F
350#define MAMR_TLFA_1X 0x00000001
351#define MAMR_TLFA_2X 0x00000002
352#define MAMR_TLFA_3X 0x00000003
353#define MAMR_TLFA_4X 0x00000004
354#define MAMR_TLFA_5X 0x00000005
355#define MAMR_TLFA_6X 0x00000006
356#define MAMR_TLFA_7X 0x00000007
357#define MAMR_TLFA_8X 0x00000008
358#define MAMR_TLFA_9X 0x00000009
359#define MAMR_TLFA_10X 0x0000000A
360#define MAMR_TLFA_11X 0x0000000B
361#define MAMR_TLFA_12X 0x0000000C
362#define MAMR_TLFA_13X 0x0000000D
363#define MAMR_TLFA_14X 0x0000000E
364#define MAMR_TLFA_15X 0x0000000F
365#define MAMR_TLFA_16X 0x00000000
366
367
368
369
370#define MBMR_PTB_MSK 0xFF000000
371#define MBMR_PTB_SHIFT 0x00000018
372#define MBMR_PTBE 0x00800000
373#define MBMR_AMB_MSK 0x00700000
374#define MBMR_AMB_TYPE_0 0x00000000
375#define MBMR_AMB_TYPE_1 0x00100000
376#define MBMR_AMB_TYPE_2 0x00200000
377#define MBMR_AMB_TYPE_3 0x00300000
378#define MBMR_AMB_TYPE_4 0x00400000
379#define MBMR_AMB_TYPE_5 0x00500000
380#define MBMR_DSB_MSK 0x00060000
381#define MBMR_DSB_1_CYCL 0x00000000
382#define MBMR_DSB_2_CYCL 0x00020000
383#define MBMR_DSB_3_CYCL 0x00040000
384#define MBMR_DSB_4_CYCL 0x00060000
385#define MBMR_G0CLB_MSK 0x0000E000
386#define MBMR_G0CLB_A12 0x00000000
387#define MBMR_G0CLB_A11 0x00002000
388#define MBMR_G0CLB_A10 0x00004000
389#define MBMR_G0CLB_A9 0x00006000
390#define MBMR_G0CLB_A8 0x00008000
391#define MBMR_G0CLB_A7 0x0000A000
392#define MBMR_G0CLB_A6 0x0000C000
393#define MBMR_G0CLB_A5 0x0000E000
394#define MBMR_GPL_B4DIS 0x00001000
395#define MBMR_RLFB_MSK 0x00000F00
396#define MBMR_RLFB_1X 0x00000100
397#define MBMR_RLFB_2X 0x00000200
398#define MBMR_RLFB_3X 0x00000300
399#define MBMR_RLFB_4X 0x00000400
400#define MBMR_RLFB_5X 0x00000500
401#define MBMR_RLFB_6X 0x00000600
402#define MBMR_RLFB_7X 0x00000700
403#define MBMR_RLFB_8X 0x00000800
404#define MBMR_RLFB_9X 0x00000900
405#define MBMR_RLFB_10X 0x00000A00
406#define MBMR_RLFB_11X 0x00000B00
407#define MBMR_RLFB_12X 0x00000C00
408#define MBMR_RLFB_13X 0x00000D00
409#define MBMR_RLFB_14X 0x00000E00
410#define MBMR_RLFB_15X 0x00000f00
411#define MBMR_RLFB_16X 0x00000000
412#define MBMR_WLFB_MSK 0x000000F0
413#define MBMR_WLFB_1X 0x00000010
414#define MBMR_WLFB_2X 0x00000020
415#define MBMR_WLFB_3X 0x00000030
416#define MBMR_WLFB_4X 0x00000040
417#define MBMR_WLFB_5X 0x00000050
418#define MBMR_WLFB_6X 0x00000060
419#define MBMR_WLFB_7X 0x00000070
420#define MBMR_WLFB_8X 0x00000080
421#define MBMR_WLFB_9X 0x00000090
422#define MBMR_WLFB_10X 0x000000A0
423#define MBMR_WLFB_11X 0x000000B0
424#define MBMR_WLFB_12X 0x000000C0
425#define MBMR_WLFB_13X 0x000000D0
426#define MBMR_WLFB_14X 0x000000E0
427#define MBMR_WLFB_15X 0x000000F0
428#define MBMR_WLFB_16X 0x00000000
429#define MBMR_TLFB_MSK 0x0000000F
430#define MBMR_TLFB_1X 0x00000001
431#define MBMR_TLFB_2X 0x00000002
432#define MBMR_TLFB_3X 0x00000003
433#define MBMR_TLFB_4X 0x00000004
434#define MBMR_TLFB_5X 0x00000005
435#define MBMR_TLFB_6X 0x00000006
436#define MBMR_TLFB_7X 0x00000007
437#define MBMR_TLFB_8X 0x00000008
438#define MBMR_TLFB_9X 0x00000009
439#define MBMR_TLFB_10X 0x0000000A
440#define MBMR_TLFB_11X 0x0000000B
441#define MBMR_TLFB_12X 0x0000000C
442#define MBMR_TLFB_13X 0x0000000D
443#define MBMR_TLFB_14X 0x0000000E
444#define MBMR_TLFB_15X 0x0000000F
445#define MBMR_TLFB_16X 0x00000000
446
447
448
449
450#define TGCR_CAS4 0x8000
451#define TGCR_FRZ4 0x4000
452#define TGCR_STP4 0x2000
453#define TGCR_RST4 0x1000
454#define TGCR_GM2 0x0800
455#define TGCR_FRZ3 0x0400
456#define TGCR_STP3 0x0200
457#define TGCR_RST3 0x0100
458#define TGCR_CAS2 0x0080
459#define TGCR_FRZ2 0x0040
460#define TGCR_STP2 0x0020
461#define TGCR_RST2 0x0010
462#define TGCR_GM1 0x0008
463#define TGCR_FRZ1 0x0004
464#define TGCR_STP1 0x0002
465#define TGCR_RST1 0x0001
466
467
468
469
470
471#define TMR_PS_MSK 0xFF00
472#define TMR_PS_SHIFT 8
473#define TMR_CE_MSK 0x00C0
474#define TMR_CE_INTR_DIS 0x0000
475#define TMR_CE_RISING 0x0040
476#define TMR_CE_FALLING 0x0080
477#define TMR_CE_ANY 0x00C0
478#define TMR_OM 0x0020
479#define TMR_ORI 0x0010
480#define TMR_FRR 0x0008
481#define TMR_ICLK_MSK 0x0006
482#define TMR_ICLK_IN_CAS 0x0000
483#define TMR_ICLK_IN_GEN 0x0002
484#define TMR_ICLK_IN_GEN_DIV16 0x0004
485#define TMR_ICLK_TIN_PIN 0x0006
486#define TMR_GE 0x0001
487
488
489
490
491
492#define I2MOD_REVD 0x20
493#define I2MOD_GCD 0x10
494#define I2MOD_FLT 0x08
495#define I2MOD_PDIV32 0x00
496#define I2MOD_PDIV16 0x02
497#define I2MOD_PDIV8 0x04
498#define I2MOD_PDIV4 0x06
499#define I2MOD_EN 0x01
500
501#define I2CER_TXE 0x10
502#define I2CER_BSY 0x04
503#define I2CER_TXB 0x02
504#define I2CER_RXB 0x01
505#define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
506
507#define I2COM_STR 0x80
508#define I2COM_MASTER 0x01
509
510
511
512
513#define SPI_EMASK 0x37
514#define SPI_MME 0x20
515#define SPI_TXE 0x10
516#define SPI_BSY 0x04
517#define SPI_TXB 0x02
518#define SPI_RXB 0x01
519
520#define SPI_STR 0x80
521
522
523
524
525#define PCMCIA_GCRX_CXRESET 0x00000040
526#define PCMCIA_GCRX_CXOE 0x00000080
527
528#define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
529#define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
530#define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4))
531#define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
532
533#define PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
534#define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
535#define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
536#define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
537#define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
538#define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
539#define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
540#define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
541#define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
542#define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
543#define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
544
545
546
547
548
549
550#define PCMCIA_BSIZE_1 0x00000000
551#define PCMCIA_BSIZE_2 0x08000000
552#define PCMCIA_BSIZE_4 0x18000000
553#define PCMCIA_BSIZE_8 0x10000000
554#define PCMCIA_BSIZE_16 0x30000000
555#define PCMCIA_BSIZE_32 0x38000000
556#define PCMCIA_BSIZE_64 0x28000000
557#define PCMCIA_BSIZE_128 0x20000000
558#define PCMCIA_BSIZE_256 0x60000000
559#define PCMCIA_BSIZE_512 0x68000000
560#define PCMCIA_BSIZE_1K 0x78000000
561#define PCMCIA_BSIZE_2K 0x70000000
562#define PCMCIA_BSIZE_4K 0x50000000
563#define PCMCIA_BSIZE_8K 0x58000000
564#define PCMCIA_BSIZE_16K 0x48000000
565#define PCMCIA_BSIZE_32K 0x40000000
566#define PCMCIA_BSIZE_64K 0xC0000000
567#define PCMCIA_BSIZE_128K 0xC8000000
568#define PCMCIA_BSIZE_256K 0xD8000000
569#define PCMCIA_BSIZE_512K 0xD0000000
570#define PCMCIA_BSIZE_1M 0xF0000000
571#define PCMCIA_BSIZE_2M 0xF8000000
572#define PCMCIA_BSIZE_4M 0xE8000000
573#define PCMCIA_BSIZE_8M 0xE0000000
574#define PCMCIA_BSIZE_16M 0xA0000000
575#define PCMCIA_BSIZE_32M 0xA8000000
576#define PCMCIA_BSIZE_64M 0xB8000000
577
578
579#define PCMCIA_SHT(t) ((t & 0x0F)<<16)
580#define PCMCIA_SST(t) ((t & 0x0F)<<12)
581#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7))
582
583
584#define PCMCIA_PPS_8 0x00000000
585#define PCMCIA_PPS_16 0x00000040
586
587
588#define PCMCIA_PRS_MEM 0x00000000
589#define PCMCIA_PRS_ATTR 0x00000010
590#define PCMCIA_PRS_IO 0x00000018
591#define PCMCIA_PRS_DMA 0x00000020
592#define PCMCIA_PRS_DMA_LAST 0x00000028
593#define PCMCIA_PRS_CEx 0x00000030
594
595#define PCMCIA_PSLOT_A 0x00000000
596#define PCMCIA_PSLOT_B 0x00000004
597#define PCMCIA_WPROT 0x00000002
598#define PCMCIA_PV 0x00000001
599
600#define UPMA 0x00000000
601#define UPMB 0x00800000
602
603#endif
604