1/* 2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef AT91_MC_H 8#define AT91_MC_H 9 10#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60) 11#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64) 12#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70) 13#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90) 14#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94) 15#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98) 16 17#ifndef __ASSEMBLY__ 18 19typedef struct at91_ebi { 20 u32 csa; /* 0x00 Chip Select Assignment Register */ 21 u32 cfgr; /* 0x04 Configuration Register */ 22 u32 reserved[2]; 23} at91_ebi_t; 24 25#define AT91_EBI_CSA_CS0A 0x0001 26#define AT91_EBI_CSA_CS1A 0x0002 27 28#define AT91_EBI_CSA_CS3A 0x0008 29#define AT91_EBI_CSA_CS4A 0x0010 30 31typedef struct at91_sdramc { 32 u32 mr; /* 0x00 SDRAMC Mode Register */ 33 u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ 34 u32 cr; /* 0x08 SDRAMC Configuration Register */ 35 u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ 36 u32 lpr; /* 0x10 SDRAMC Low Power Register */ 37 u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ 38 u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ 39 u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ 40 u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ 41 u32 reserved[3]; 42} at91_sdramc_t; 43 44typedef struct at91_smc { 45 u32 csr[8]; /* 0x00 SDRAMC Mode Register */ 46} at91_smc_t; 47 48#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) 49#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) 50#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 51#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 52#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 53#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 54#define AT91_SMC_CSR_DRP 0x00008000 55#define AT91_SMC_CSR_DBW_8 0x00004000 56#define AT91_SMC_CSR_DBW_16 0x00002000 57#define AT91_SMC_CSR_BAT_8 0x00000000 58#define AT91_SMC_CSR_BAT_16 0x00001000 59#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) 60#define AT91_SMC_CSR_WSEN 0x00000080 61#define AT91_SMC_CSR_NWS(x) (x & 0x7F) 62 63typedef struct at91_bfc { 64 u32 mr; /* 0x00 SDRAMC Mode Register */ 65} at91_bfc_t; 66 67typedef struct at91_mc { 68 u32 rcr; /* 0x00 MC Remap Control Register */ 69 u32 asr; /* 0x04 MC Abort Status Register */ 70 u32 aasr; /* 0x08 MC Abort Address Status Reg */ 71 u32 mpr; /* 0x0C MC Master Priority Register */ 72 u32 reserved1[20]; /* 0x10-0x5C */ 73 at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ 74 at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ 75 at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ 76 at91_bfc_t bfc; /* 0xC0 BFC User Interface */ 77 u32 reserved2[15]; 78} at91_mc_t; 79 80#endif 81#endif 82