1/* 2 * MCF5329 Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __IMMAP_5329__ 11#define __IMMAP_5329__ 12 13#define MMAP_SCM1 0xEC000000 14#define MMAP_MDHA 0xEC080000 15#define MMAP_SKHA 0xEC084000 16#define MMAP_RNG 0xEC088000 17#define MMAP_SCM2 0xFC000000 18#define MMAP_XBS 0xFC004000 19#define MMAP_FBCS 0xFC008000 20#define MMAP_CAN 0xFC020000 21#define MMAP_FEC 0xFC030000 22#define MMAP_SCM3 0xFC040000 23#define MMAP_EDMA 0xFC044000 24#define MMAP_TCD 0xFC045000 25#define MMAP_INTC0 0xFC048000 26#define MMAP_INTC1 0xFC04C000 27#define MMAP_INTCACK 0xFC054000 28#define MMAP_I2C 0xFC058000 29#define MMAP_QSPI 0xFC05C000 30#define MMAP_UART0 0xFC060000 31#define MMAP_UART1 0xFC064000 32#define MMAP_UART2 0xFC068000 33#define MMAP_DTMR0 0xFC070000 34#define MMAP_DTMR1 0xFC074000 35#define MMAP_DTMR2 0xFC078000 36#define MMAP_DTMR3 0xFC07C000 37#define MMAP_PIT0 0xFC080000 38#define MMAP_PIT1 0xFC084000 39#define MMAP_PIT2 0xFC088000 40#define MMAP_PIT3 0xFC08C000 41#define MMAP_PWM 0xFC090000 42#define MMAP_EPORT 0xFC094000 43#define MMAP_WDOG 0xFC098000 44#define MMAP_RCM 0xFC0A0000 45#define MMAP_CCM 0xFC0A0004 46#define MMAP_GPIO 0xFC0A4000 47#define MMAP_RTC 0xFC0A8000 48#define MMAP_LCDC 0xFC0AC000 49#define MMAP_USBOTG 0xFC0B0000 50#define MMAP_USBH 0xFC0B4000 51#define MMAP_SDRAM 0xFC0B8000 52#define MMAP_SSI 0xFC0BC000 53#define MMAP_PLL 0xFC0C0000 54 55#include <asm/coldfire/crossbar.h> 56#include <asm/coldfire/edma.h> 57#include <asm/coldfire/eport.h> 58#include <asm/coldfire/qspi.h> 59#include <asm/coldfire/flexbus.h> 60#include <asm/coldfire/flexcan.h> 61#include <asm/coldfire/intctrl.h> 62#include <asm/coldfire/lcd.h> 63#include <asm/coldfire/mdha.h> 64#include <asm/coldfire/pwm.h> 65#include <asm/coldfire/ssi.h> 66#include <asm/coldfire/skha.h> 67 68/* System control module registers */ 69typedef struct scm1_ctrl { 70 u32 mpr0; /* 0x00 Master Privilege Register 0 */ 71 u32 res1[15]; /* 0x04 - 0x3F */ 72 u32 pacrh; /* 0x40 Peripheral Access Control Register H */ 73 u32 res2[3]; /* 0x44 - 0x53 */ 74 u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ 75} scm1_t; 76 77/* System control module registers 2 */ 78typedef struct scm2_ctrl { 79 u32 mpr1; /* 0x00 Master Privilege Register */ 80 u32 res1[7]; /* 0x04 - 0x1F */ 81 u32 pacra; /* 0x20 Peripheral Access Control Register A */ 82 u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 83 u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 84 u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 85 u32 res2[4]; /* 0x30 - 0x3F */ 86 u32 pacre; /* 0x40 Peripheral Access Control Register E */ 87 u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 88 u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 89 u32 res3[2]; /* 0x4C - 0x53 */ 90 u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ 91} scm2_t; 92 93/* System Control Module register 3 */ 94typedef struct scm3_ctrl { 95 u8 res1[19]; /* 0x00 - 0x12 */ 96 u8 wcr; /* 0x13 wakeup control register */ 97 u16 res2; /* 0x14 - 0x15 */ 98 u16 cwcr; /* 0x16 Core Watchdog Control Register */ 99 u8 res3[3]; /* 0x18 - 0x1A */ 100 u8 cwsr; /* 0x1B Core Watchdog Service Register */ 101 u8 res4[2]; /* 0x1C - 0x1D */ 102 u8 scmisr; /* 0x1F Interrupt Status Register */ 103 u32 res5; /* 0x20 */ 104 u32 bcr; /* 0x24 Burst Configuration Register */ 105 u32 res6[18]; /* 0x28 - 0x6F */ 106 u32 cfadr; /* 0x70 Core Fault Address Register */ 107 u8 res7[4]; /* 0x71 - 0x74 */ 108 u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ 109 u8 cfloc; /* 0x76 Core Fault Location Register */ 110 u8 cfatr; /* 0x77 Core Fault Attributes Register */ 111 u32 res8; /* 0x78 */ 112 u32 cfdtr; /* 0x7C Core Fault Data Register */ 113} scm3_t; 114 115typedef struct canex_ctrl { 116 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 117} canex_t; 118 119/* Watchdog registers */ 120typedef struct wdog_ctrl { 121 u16 cr; /* 0x00 Control register */ 122 u16 mr; /* 0x02 Modulus register */ 123 u16 cntr; /* 0x04 Count register */ 124 u16 sr; /* 0x06 Service register */ 125} wdog_t; 126 127/*Chip configuration module registers */ 128typedef struct ccm_ctrl { 129 u16 ccr; /* 0x00 Chip configuration register */ 130 u16 res2; /* 0x02 */ 131 u16 rcon; /* 0x04 Rreset configuration register */ 132 u16 cir; /* 0x06 Chip identification register */ 133 u32 res3; /* 0x08 */ 134 u16 misccr; /* 0x0A Miscellaneous control register */ 135 u16 cdr; /* 0x0C Clock divider register */ 136 u16 uhcsr; /* 0x10 USB Host controller status register */ 137 u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */ 138} ccm_t; 139 140typedef struct rcm { 141 u8 rcr; 142 u8 rsr; 143} rcm_t; 144 145/* GPIO port registers */ 146typedef struct gpio_ctrl { 147 /* Port Output Data Registers */ 148#ifdef CONFIG_M5329 149 u8 podr_fech; /* 0x00 */ 150 u8 podr_fecl; /* 0x01 */ 151#else 152 u16 res00; /* 0x00 - 0x01 */ 153#endif 154 u8 podr_ssi; /* 0x02 */ 155 u8 podr_busctl; /* 0x03 */ 156 u8 podr_be; /* 0x04 */ 157 u8 podr_cs; /* 0x05 */ 158 u8 podr_pwm; /* 0x06 */ 159 u8 podr_feci2c; /* 0x07 */ 160 u8 res08; /* 0x08 */ 161 u8 podr_uart; /* 0x09 */ 162 u8 podr_qspi; /* 0x0A */ 163 u8 podr_timer; /* 0x0B */ 164#ifdef CONFIG_M5329 165 u8 res0C; /* 0x0C */ 166 u8 podr_lcddatah; /* 0x0D */ 167 u8 podr_lcddatam; /* 0x0E */ 168 u8 podr_lcddatal; /* 0x0F */ 169 u8 podr_lcdctlh; /* 0x10 */ 170 u8 podr_lcdctll; /* 0x11 */ 171#else 172 u16 res0C; /* 0x0C - 0x0D */ 173 u8 podr_fech; /* 0x0E */ 174 u8 podr_fecl; /* 0x0F */ 175 u16 res10[3]; /* 0x10 - 0x15 */ 176#endif 177 178 /* Port Data Direction Registers */ 179#ifdef CONFIG_M5329 180 u16 res12; /* 0x12 - 0x13 */ 181 u8 pddr_fech; /* 0x14 */ 182 u8 pddr_fecl; /* 0x15 */ 183#endif 184 u8 pddr_ssi; /* 0x16 */ 185 u8 pddr_busctl; /* 0x17 */ 186 u8 pddr_be; /* 0x18 */ 187 u8 pddr_cs; /* 0x19 */ 188 u8 pddr_pwm; /* 0x1A */ 189 u8 pddr_feci2c; /* 0x1B */ 190 u8 res1C; /* 0x1C */ 191 u8 pddr_uart; /* 0x1D */ 192 u8 pddr_qspi; /* 0x1E */ 193 u8 pddr_timer; /* 0x1F */ 194#ifdef CONFIG_M5329 195 u8 res20; /* 0x20 */ 196 u8 pddr_lcddatah; /* 0x21 */ 197 u8 pddr_lcddatam; /* 0x22 */ 198 u8 pddr_lcddatal; /* 0x23 */ 199 u8 pddr_lcdctlh; /* 0x24 */ 200 u8 pddr_lcdctll; /* 0x25 */ 201 u16 res26; /* 0x26 - 0x27 */ 202#else 203 u16 res20; /* 0x20 - 0x21 */ 204 u8 pddr_fech; /* 0x22 */ 205 u8 pddr_fecl; /* 0x23 */ 206 u16 res24[3]; /* 0x24 - 0x29 */ 207#endif 208 209 /* Port Data Direction Registers */ 210#ifdef CONFIG_M5329 211 u8 ppd_fech; /* 0x28 */ 212 u8 ppd_fecl; /* 0x29 */ 213#endif 214 u8 ppd_ssi; /* 0x2A */ 215 u8 ppd_busctl; /* 0x2B */ 216 u8 ppd_be; /* 0x2C */ 217 u8 ppd_cs; /* 0x2D */ 218 u8 ppd_pwm; /* 0x2E */ 219 u8 ppd_feci2c; /* 0x2F */ 220 u8 res30; /* 0x30 */ 221 u8 ppd_uart; /* 0x31 */ 222 u8 ppd_qspi; /* 0x32 */ 223 u8 ppd_timer; /* 0x33 */ 224#ifdef CONFIG_M5329 225 u8 res34; /* 0x34 */ 226 u8 ppd_lcddatah; /* 0x35 */ 227 u8 ppd_lcddatam; /* 0x36 */ 228 u8 ppd_lcddatal; /* 0x37 */ 229 u8 ppd_lcdctlh; /* 0x38 */ 230 u8 ppd_lcdctll; /* 0x39 */ 231 u16 res3A; /* 0x3A - 0x3B */ 232#else 233 u16 res34; /* 0x34 - 0x35 */ 234 u8 ppd_fech; /* 0x36 */ 235 u8 ppd_fecl; /* 0x37 */ 236 u16 res38[3]; /* 0x38 - 0x3D */ 237#endif 238 239 /* Port Clear Output Data Registers */ 240#ifdef CONFIG_M5329 241 u8 res3C; /* 0x3C */ 242 u8 pclrr_fech; /* 0x3D */ 243 u8 pclrr_fecl; /* 0x3E */ 244#else 245 u8 pclrr_ssi; /* 0x3E */ 246#endif 247 u8 pclrr_busctl; /* 0x3F */ 248 u8 pclrr_be; /* 0x40 */ 249 u8 pclrr_cs; /* 0x41 */ 250 u8 pclrr_pwm; /* 0x42 */ 251 u8 pclrr_feci2c; /* 0x43 */ 252 u8 res44; /* 0x44 */ 253 u8 pclrr_uart; /* 0x45 */ 254 u8 pclrr_qspi; /* 0x46 */ 255 u8 pclrr_timer; /* 0x47 */ 256#ifdef CONFIG_M5329 257 u8 pclrr_lcddatah; /* 0x48 */ 258 u8 pclrr_lcddatam; /* 0x49 */ 259 u8 pclrr_lcddatal; /* 0x4A */ 260 u8 pclrr_ssi; /* 0x4B */ 261 u8 pclrr_lcdctlh; /* 0x4C */ 262 u8 pclrr_lcdctll; /* 0x4D */ 263 u16 res4E; /* 0x4E - 0x4F */ 264#else 265 u16 res48; /* 0x48 - 0x49 */ 266 u8 pclrr_fech; /* 0x4A */ 267 u8 pclrr_fecl; /* 0x4B */ 268 u8 res4C[5]; /* 0x4C - 0x50 */ 269#endif 270 271 /* Pin Assignment Registers */ 272#ifdef CONFIG_M5329 273 u8 par_fec; /* 0x50 */ 274#endif 275 u8 par_pwm; /* 0x51 */ 276 u8 par_busctl; /* 0x52 */ 277 u8 par_feci2c; /* 0x53 */ 278 u8 par_be; /* 0x54 */ 279 u8 par_cs; /* 0x55 */ 280 u16 par_ssi; /* 0x56 */ 281 u16 par_uart; /* 0x58 */ 282 u16 par_qspi; /* 0x5A */ 283 u8 par_timer; /* 0x5C */ 284#ifdef CONFIG_M5329 285 u8 par_lcddata; /* 0x5D */ 286 u16 par_lcdctl; /* 0x5E */ 287#else 288 u8 par_fec; /* 0x5D */ 289 u16 res5E; /* 0x5E - 0x5F */ 290#endif 291 u16 par_irq; /* 0x60 */ 292 u16 res62; /* 0x62 - 0x63 */ 293 294 /* Mode Select Control Registers */ 295 u8 mscr_flexbus; /* 0x64 */ 296 u8 mscr_sdram; /* 0x65 */ 297 u16 res66; /* 0x66 - 0x67 */ 298 299 /* Drive Strength Control Registers */ 300 u8 dscr_i2c; /* 0x68 */ 301 u8 dscr_pwm; /* 0x69 */ 302 u8 dscr_fec; /* 0x6A */ 303 u8 dscr_uart; /* 0x6B */ 304 u8 dscr_qspi; /* 0x6C */ 305 u8 dscr_timer; /* 0x6D */ 306 u8 dscr_ssi; /* 0x6E */ 307#ifdef CONFIG_M5329 308 u8 dscr_lcd; /* 0x6F */ 309#else 310 u8 res6F; /* 0x6F */ 311#endif 312 u8 dscr_debug; /* 0x70 */ 313 u8 dscr_clkrst; /* 0x71 */ 314 u8 dscr_irq; /* 0x72 */ 315} gpio_t; 316 317/* USB OTG module registers */ 318typedef struct usb_otg { 319 u32 id; /* 0x000 Identification Register */ 320 u32 hwgeneral; /* 0x004 General HW Parameters */ 321 u32 hwhost; /* 0x008 Host HW Parameters */ 322 u32 hwdev; /* 0x00C Device HW parameters */ 323 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ 324 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ 325 u32 res1[58]; /* 0x18 - 0xFF */ 326 u8 caplength; /* 0x100 Capability Register Length */ 327 u8 res2; /* 0x101 */ 328 u16 hciver; /* 0x102 Host Interface Version Number */ 329 u32 hcsparams; /* 0x104 Host Structural Parameters */ 330 u32 hccparams; /* 0x108 Host Capability Parameters */ 331 u32 res3[5]; /* 0x10C - 0x11F */ 332 u16 dciver; /* 0x120 Device Interface Version Number */ 333 u16 res4; /* 0x122 */ 334 u32 dccparams; /* 0x124 Device Capability Parameters */ 335 u32 res5[6]; /* 0x128 - 0x13F */ 336 u32 cmd; /* 0x140 USB Command */ 337 u32 sts; /* 0x144 USB Status */ 338 u32 intr; /* 0x148 USB Interrupt Enable */ 339 u32 frindex; /* 0x14C USB Frame Index */ 340 u32 res6; /* 0x150 */ 341 u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ 342 u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ 343 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ 344 u32 burstsize; /* 0x160 Master Interface Data Burst Size */ 345 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ 346 u32 res7[6]; /* 0x168 - 0x17F */ 347 u32 cfgflag; /* 0x180 Configure Flag Register */ 348 u32 portsc1; /* 0x184 Port Status/Control */ 349 u32 res8[7]; /* 0x188 - 0x1A3 */ 350 u32 otgsc; /* 0x1A4 On The Go Status and Control */ 351 u32 mode; /* 0x1A8 USB mode register */ 352 u32 eptsetstat; /* 0x1AC Endpoint Setup status */ 353 u32 eptprime; /* 0x1B0 Endpoint initialization */ 354 u32 eptflush; /* 0x1B4 Endpoint de-initialize */ 355 u32 eptstat; /* 0x1B8 Endpoint status */ 356 u32 eptcomplete; /* 0x1BC Endpoint Complete */ 357 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ 358 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ 359 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ 360 u32 eptctrl3; /* 0x1CC Endpoint control 3 */ 361} usbotg_t; 362 363/* SDRAM controller registers */ 364typedef struct sdram_ctrl { 365 u32 mode; /* 0x00 Mode/Extended Mode register */ 366 u32 ctrl; /* 0x04 Control register */ 367 u32 cfg1; /* 0x08 Configuration register 1 */ 368 u32 cfg2; /* 0x0C Configuration register 2 */ 369 u32 res1[64]; /* 0x10 - 0x10F */ 370 u32 cs0; /* 0x110 Chip Select 0 Configuration */ 371 u32 cs1; /* 0x114 Chip Select 1 Configuration */ 372} sdram_t; 373 374/* Clock Module registers */ 375typedef struct pll_ctrl { 376 u8 podr; /* 0x00 Output Divider Register */ 377 u8 res1[3]; 378 u8 pcr; /* 0x04 Control Register */ 379 u8 res2[3]; 380 u8 pmdr; /* 0x08 Modulation Divider Register */ 381 u8 res3[3]; 382 u8 pfdr; /* 0x0C Feedback Divider Register */ 383 u8 res4[3]; 384} pll_t; 385 386#endif /* __IMMAP_5329__ */ 387