1/* 2 * uart.h -- ColdFire internal UART support defines. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/****************************************************************************/ 11#ifndef uart_h 12#define uart_h 13/****************************************************************************/ 14 15/* UART module registers */ 16/* Register read/write struct */ 17typedef struct uart { 18 u8 umr; /* 0x00 Mode Register */ 19 u8 resv0[0x3]; 20 union { 21 u8 usr; /* 0x04 Status Register */ 22 u8 ucsr; /* 0x04 Clock Select Register */ 23 }; 24 u8 resv1[0x3]; 25 u8 ucr; /* 0x08 Command Register */ 26 u8 resv2[0x3]; 27 union { 28 u8 utb; /* 0x0c Transmit Buffer */ 29 u8 urb; /* 0x0c Receive Buffer */ 30 }; 31 u8 resv3[0x3]; 32 union { 33 u8 uipcr; /* 0x10 Input Port Change Register */ 34 u8 uacr; /* 0x10 Auxiliary Control reg */ 35 }; 36 u8 resv4[0x3]; 37 union { 38 u8 uimr; /* 0x14 Interrupt Mask reg */ 39 u8 uisr; /* 0x14 Interrupt Status reg */ 40 }; 41 u8 resv5[0x3]; 42 u8 ubg1; /* 0x18 Counter Timer Upper Register */ 43 u8 resv6[0x3]; 44 u8 ubg2; /* 0x1c Counter Timer Lower Register */ 45 u8 resv7[0x17]; 46 u8 uip; /* 0x34 Input Port Register */ 47 u8 resv8[0x3]; 48 u8 uop1; /* 0x38 Output Port Set Register */ 49 u8 resv9[0x3]; 50 u8 uop0; /* 0x3c Output Port Reset Register */ 51} uart_t; 52 53/********************************************************************* 54* Universal Asynchronous Receiver Transmitter (UART) 55*********************************************************************/ 56/* Bit definitions and macros for UMR */ 57#define UART_UMR_BC(x) (((x)&0x03)) 58#define UART_UMR_PT (0x04) 59#define UART_UMR_PM(x) (((x)&0x03)<<3) 60#define UART_UMR_ERR (0x20) 61#define UART_UMR_RXIRQ (0x40) 62#define UART_UMR_RXRTS (0x80) 63#define UART_UMR_SB(x) (((x)&0x0F)) 64#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ 65#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ 66#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ 67#define UART_UMR_PM_MULTI_ADDR (0x1C) 68#define UART_UMR_PM_MULTI_DATA (0x18) 69#define UART_UMR_PM_NONE (0x10) 70#define UART_UMR_PM_FORCE_HI (0x0C) 71#define UART_UMR_PM_FORCE_LO (0x08) 72#define UART_UMR_PM_ODD (0x04) 73#define UART_UMR_PM_EVEN (0x00) 74#define UART_UMR_BC_5 (0x00) 75#define UART_UMR_BC_6 (0x01) 76#define UART_UMR_BC_7 (0x02) 77#define UART_UMR_BC_8 (0x03) 78#define UART_UMR_CM_NORMAL (0x00) 79#define UART_UMR_CM_ECH (0x40) 80#define UART_UMR_CM_LOCAL_LOOP (0x80) 81#define UART_UMR_CM_REMOTE_LOOP (0xC0) 82#define UART_UMR_SB_STOP_BITS_1 (0x07) 83#define UART_UMR_SB_STOP_BITS_15 (0x08) 84#define UART_UMR_SB_STOP_BITS_2 (0x0F) 85 86/* Bit definitions and macros for USR */ 87#define UART_USR_RXRDY (0x01) 88#define UART_USR_FFULL (0x02) 89#define UART_USR_TXRDY (0x04) 90#define UART_USR_TXEMP (0x08) 91#define UART_USR_OE (0x10) 92#define UART_USR_PE (0x20) 93#define UART_USR_FE (0x40) 94#define UART_USR_RB (0x80) 95 96/* Bit definitions and macros for UCSR */ 97#define UART_UCSR_TCS(x) (((x)&0x0F)) 98#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) 99#define UART_UCSR_RCS_SYS_CLK (0xD0) 100#define UART_UCSR_RCS_CTM16 (0xE0) 101#define UART_UCSR_RCS_CTM (0xF0) 102#define UART_UCSR_TCS_SYS_CLK (0x0D) 103#define UART_UCSR_TCS_CTM16 (0x0E) 104#define UART_UCSR_TCS_CTM (0x0F) 105 106/* Bit definitions and macros for UCR */ 107#define UART_UCR_RXC(x) (((x)&0x03)) 108#define UART_UCR_TXC(x) (((x)&0x03)<<2) 109#define UART_UCR_MISC(x) (((x)&0x07)<<4) 110#define UART_UCR_NONE (0x00) 111#define UART_UCR_STOP_BREAK (0x70) 112#define UART_UCR_START_BREAK (0x60) 113#define UART_UCR_BKCHGINT (0x50) 114#define UART_UCR_RESET_ERROR (0x40) 115#define UART_UCR_RESET_TX (0x30) 116#define UART_UCR_RESET_RX (0x20) 117#define UART_UCR_RESET_MR (0x10) 118#define UART_UCR_TX_DISABLED (0x08) 119#define UART_UCR_TX_ENABLED (0x04) 120#define UART_UCR_RX_DISABLED (0x02) 121#define UART_UCR_RX_ENABLED (0x01) 122 123/* Bit definitions and macros for UIPCR */ 124#define UART_UIPCR_CTS (0x01) 125#define UART_UIPCR_COS (0x10) 126 127/* Bit definitions and macros for UACR */ 128#define UART_UACR_IEC (0x01) 129 130/* Bit definitions and macros for UIMR */ 131#define UART_UIMR_TXRDY (0x01) 132#define UART_UIMR_RXRDY_FU (0x02) 133#define UART_UIMR_DB (0x04) 134#define UART_UIMR_COS (0x80) 135 136/* Bit definitions and macros for UISR */ 137#define UART_UISR_TXRDY (0x01) 138#define UART_UISR_RXRDY_FU (0x02) 139#define UART_UISR_DB (0x04) 140#define UART_UISR_RXFTO (0x08) 141#define UART_UISR_TXFIFO (0x10) 142#define UART_UISR_RXFIFO (0x20) 143#define UART_UISR_COS (0x80) 144 145/* Bit definitions and macros for UIP */ 146#define UART_UIP_CTS (0x01) 147 148/* Bit definitions and macros for UOP1 */ 149#define UART_UOP1_RTS (0x01) 150 151/* Bit definitions and macros for UOP0 */ 152#define UART_UOP0_RTS (0x01) 153 154/****************************************************************************/ 155#endif /* mcfuart_h */ 156