LXR uboot/arch/powerpc/cpu/mpc8260/pci.c

   1/*
   2 * (C) Copyright 2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * Copyright (c) 2005 MontaVista Software, Inc.
   6 * Vitaly Bordug <vbordug@ru.mvista.com>
   7 * Added support for PCI bridge on MPC8272ADS
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#include <common.h>
  13
  14#ifdef CONFIG_PCI
  15
  16#include <pci.h>
  17#include <mpc8260.h>
  18#include <asm/m8260_pci.h>
  19#include <asm/io.h>
  20#ifdef CONFIG_OF_LIBFDT
  21#include <libfdt.h>
  22#include <fdt_support.h>
  23#endif
  24
  25/*
  26 *   Local->PCI map (from CPU)                             controlled by
  27 *   MPC826x master window
  28 *
  29 *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
  30 *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
  31 *
  32 *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
  33 *                              PCI Mem with prefetch
  34 *
  35 *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
  36 *                              PCI Mem w/o  prefetch
  37 *
  38 *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
  39 *                              32-bit PCI IO
  40 *
  41 *   PCI->Local map (from PCI)
  42 *   MPC826x slave window                                  controlled by
  43 *
  44 *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
  45 *                              MPC826x local memory
  46 */
  47
  48/*
  49 * Slave window that allows PCI masters to access MPC826x local memory.
  50 * This window is set up using the first set of Inbound ATU registers
  51 */
  52
  53#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
  54#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
  55#else
  56#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
  57#endif
  58
  59#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
  60#define PCI_SLV_MEM_BUS 0x00000000      /* PCI base */
  61#else
  62#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
  63#endif
  64
  65#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
  66#define PICMR0_MASK_ATTRIB      (PICMR_MASK_512MB | PICMR_ENABLE | \
  67                                 PICMR_PREFETCH_EN)
  68#else
  69#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
  70#endif
  71
  72/*
  73 * These are the windows that allow the CPU to access PCI address space.
  74 * All three PCI master windows, which allow the CPU to access PCI
  75 * prefetch, non prefetch, and IO space (see below), must all fit within
  76 * these windows.
  77 */
  78
  79/* PCIBR0 */
  80#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
  81#define PCI_MSTR0_LOCAL         0x80000000      /* Local base */
  82#else
  83#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
  84#endif
  85
  86#ifndef CONFIG_SYS_PCIMSK0_MASK
  87#define PCIMSK0_MASK            PCIMSK_1GB      /* Size of window */
  88#else
  89#define PCIMSK0_MASK    CONFIG_SYS_PCIMSK0_MASK
  90#endif
  91
  92/* PCIBR1 */
  93#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
  94#define PCI_MSTR1_LOCAL         0xF4000000      /* Local base */
  95#else
  96#define PCI_MSTR1_LOCAL         CONFIG_SYS_PCI_MSTR1_LOCAL
  97#endif
  98
  99#ifndef CONFIG_SYS_PCIMSK1_MASK
 100#define  PCIMSK1_MASK           PCIMSK_64MB     /* Size of window */
 101#else
 102#define  PCIMSK1_MASK           CONFIG_SYS_PCIMSK1_MASK
 103#endif
 104
 105/*
 106 * Master window that allows the CPU to access PCI Memory (prefetch).
 107 * This window will be setup with the first set of Outbound ATU registers
 108 * in the bridge.
 109 */
 110
 111#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 112#define PCI_MSTR_MEM_LOCAL 0x80000000   /* Local base */
 113#else
 114#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 115#endif
 116
 117#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
 118#define PCI_MSTR_MEM_BUS 0x80000000     /* PCI base   */
 119#else
 120#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
 121#endif
 122
 123#ifndef CONFIG_SYS_CPU_PCI_MEM_START
 124#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
 125#else
 126#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
 127#endif
 128
 129#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
 130#define PCI_MSTR_MEM_SIZE 0x10000000    /* 256MB */
 131#else
 132#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
 133#endif
 134
 135#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
 136#define POCMR0_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 137#else
 138#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
 139#endif
 140
 141/*
 142 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 143 * This window will be setup with the second set of Outbound ATU registers
 144 * in the bridge.
 145 */
 146
 147#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
 148#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
 149#else
 150#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
 151#endif
 152
 153#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
 154#define PCI_MSTR_MEMIO_BUS 0x90000000   /* PCI base   */
 155#else
 156#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
 157#endif
 158
 159#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
 160#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
 161#else
 162#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
 163#endif
 164
 165#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
 166#define PCI_MSTR_MEMIO_SIZE 0x10000000  /* 256 MB */
 167#else
 168#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
 169#endif
 170
 171#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
 172#define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 173#else
 174#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
 175#endif
 176
 177/*
 178 * Master window that allows the CPU to access PCI IO space.
 179 * This window will be setup with the third set of Outbound ATU registers
 180 * in the bridge.
 181 */
 182
 183#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
 184#define PCI_MSTR_IO_LOCAL 0xA0000000    /* Local base */
 185#else
 186#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
 187#endif
 188
 189#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
 190#define PCI_MSTR_IO_BUS 0xA0000000      /* PCI base   */
 191#else
 192#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
 193#endif
 194
 195#ifndef CONFIG_SYS_CPU_PCI_IO_START
 196#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
 197#else
 198#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
 199#endif
 200
 201#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
 202#define PCI_MSTR_IO_SIZE 0x10000000     /* 256MB */
 203#else
 204#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
 205#endif
 206
 207#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
 208#define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
 209#else
 210#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
 211#endif
 212
 213/* PCI bus configuration registers.
 214 */
 215
 216#define PCI_CLASS_BRIDGE_CTLR   0x06
 217
 218
 219static inline void pci_outl (u32 addr, u32 data)
 220{
 221        *(volatile u32 *) addr = cpu_to_le32 (data);
 222}
 223
 224void pci_mpc8250_init (struct pci_controller *hose)
 225{
 226        u16 tempShort;
 227
 228        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 229        pci_dev_t host_devno = PCI_BDF (0, 0, 0);
 230
 231        pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
 232                            CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
 233
 234        /*
 235         * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
 236         * and local bus for PCI (SIUMCR [LBPC]).
 237         */
 238        immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 239                                                ~SIUMCR_LBPC11 &
 240                                                ~SIUMCR_CS10PC11 &
 241                                                ~SIUMCR_LBPC11) |
 242                                        SIUMCR_LBPC01 |
 243                                        SIUMCR_CS10PC01 |
 244                                        SIUMCR_APPC10;
 245
 246        /* Make PCI lowest priority */
 247        /* Each 4 bits is a device bus request  and the MS 4bits
 248           is highest priority */
 249        /* Bus               4bit value
 250           ---               ----------
 251           CPM high          0b0000
 252           CPM middle        0b0001
 253           CPM low           0b0010
 254           PCI reguest       0b0011
 255           Reserved          0b0100
 256           Reserved          0b0101
 257           Internal Core     0b0110
 258           External Master 1 0b0111
 259           External Master 2 0b1000
 260           External Master 3 0b1001
 261           The rest are reserved */
 262        immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
 263
 264        /* Park bus on core while modifying PCI Bus accesses */
 265        immap->im_siu_conf.sc_ppc_acr = 0x6;
 266
 267        /*
 268         * Set up master windows that allow the CPU to access PCI space. These
 269         * windows are set up using the two SIU PCIBR registers.
 270         */
 271        immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
 272        immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 273
 274        /* Release PCI RST (by default the PCI RST signal is held low)  */
 275        immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
 276
 277        /* give it some time */
 278        {
 279                        udelay (1000);
 280        }
 281
 282        /*
 283         * Set up master window that allows the CPU to access PCI Memory (prefetch)
 284         * space. This window is set up using the first set of Outbound ATU registers.
 285         */
 286        immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);        /* PCI base */
 287        immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);      /* Local base */
 288        immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);    /* Size & attribute */
 289
 290        /*
 291         * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
 292         * space. This window is set up using the second set of Outbound ATU registers.
 293         */
 294        immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);      /* PCI base */
 295        immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);    /* Local base */
 296        immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);    /* Size & attribute */
 297
 298        /*
 299         * Set up master window that allows the CPU to access PCI IO space. This window
 300         * is set up using the third set of Outbound ATU registers.
 301         */
 302        immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
 303        immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);       /* Local base */
 304        immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);    /* Size & attribute */
 305
 306        /*
 307         * Set up slave window that allows PCI masters to access MPC826x local memory.
 308         * This window is set up using the first set of Inbound ATU registers
 309         */
 310        immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);       /* PCI base */
 311        immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
 312        immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);    /* Size & attribute */
 313
 314        /* See above for description - puts PCI request as highest priority */
 315        immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
 316
 317        /* Park the bus on the PCI */
 318        immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
 319
 320        /* Host mode - specify the bridge as a host-PCI bridge */
 321
 322        pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
 323                                    PCI_CLASS_BRIDGE_CTLR);
 324
 325        /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
 326        pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
 327        pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
 328                                    tempShort | PCI_COMMAND_MASTER |
 329                                    PCI_COMMAND_MEMORY);
 330
 331        /* do some bridge init, should be done on all 8260 based bridges */
 332        pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
 333                                    0x08);
 334        pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
 335                                    0xF8);
 336
 337        hose->first_busno = 0;
 338        hose->last_busno = 0xff;
 339
 340        /* System memory space */
 341        pci_set_region (hose->regions + 0,
 342                        CONFIG_SYS_SDRAM_BASE,
 343                        CONFIG_SYS_SDRAM_BASE,
 344                        0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 345
 346        /* PCI memory space */
 347        pci_set_region (hose->regions + 1,
 348                        PCI_MSTR_MEM_BUS,
 349                        PCI_MSTR_MEM_LOCAL,
 350                        PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
 351
 352        /* PCI I/O space */
 353        pci_set_region (hose->regions + 2,
 354                        PCI_MSTR_IO_BUS,
 355                        PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
 356
 357        hose->region_count = 3;
 358
 359        pci_register_hose (hose);
 360        /* Mask off master abort machine checks */
 361        immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
 362        eieio ();
 363
 364        hose->last_busno = pci_hose_scan (hose);
 365
 366
 367        /* clear the error in the error status register */
 368        immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 369
 370        /* unmask master abort machine checks */
 371        immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 372}
 373
 374#if defined(CONFIG_OF_LIBFDT)
 375void ft_pci_setup(void *blob, bd_t *bd)
 376{
 377        do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
 378                "clock-frequency", gd->pci_clk, 1);
 379}
 380#endif
 381
 382#endif /* CONFIG_PCI */
 383