1/* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _ASM_CONFIG_H_ 8#define _ASM_CONFIG_H_ 9 10#ifdef CONFIG_MPC85xx 11#include <asm/config_mpc85xx.h> 12#define CONFIG_SYS_FSL_DDR 13#endif 14 15#ifdef CONFIG_MPC86xx 16#include <asm/config_mpc86xx.h> 17#define CONFIG_SYS_FSL_DDR 18#endif 19 20#ifdef CONFIG_MPC83xx 21#define CONFIG_SYS_FSL_DDR 22#endif 23 24#ifndef HWCONFIG_BUFFER_SIZE 25 #define HWCONFIG_BUFFER_SIZE 256 26#endif 27 28/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 29#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 30# ifndef CONFIG_HARD_SPI 31# define CONFIG_HARD_SPI 32# endif 33#endif 34 35#define CONFIG_LMB 36#define CONFIG_SYS_BOOT_RAMDISK_HIGH 37#define CONFIG_SYS_BOOT_GET_CMDLINE 38#define CONFIG_SYS_BOOT_GET_KBD 39 40#ifndef CONFIG_MAX_MEM_MAPPED 41#if defined(CONFIG_4xx) || \ 42 defined(CONFIG_E500) || \ 43 defined(CONFIG_MPC86xx) || \ 44 defined(CONFIG_E300) 45#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 46#else 47#define CONFIG_MAX_MEM_MAPPED (256 << 20) 48#endif 49#endif 50 51/* Check if boards need to enable FSL DMA engine for SDRAM init */ 52#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 53#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 54 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 55 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 56#define CONFIG_FSL_DMA 57#endif 58#endif 59 60#ifndef CONFIG_MAX_CPUS 61#define CONFIG_MAX_CPUS 1 62#endif 63 64/* 65 * Provide a default boot page translation virtual address that lines up with 66 * Freescale's default e500 reset page. 67 */ 68#if (defined(CONFIG_E500) && defined(CONFIG_MP)) 69#ifndef CONFIG_BPTR_VIRT_ADDR 70#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 71#endif 72#endif 73 74/* 75 * SEC (crypto unit) major compatible version determination 76 */ 77#if defined(CONFIG_MPC83xx) 78#define CONFIG_SYS_FSL_SEC_BE 79#define CONFIG_SYS_FSL_SEC_COMPAT 2 80#endif 81 82/* Since so many PPC SOCs have a semi-common LBC, define this here */ 83#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 84 defined(CONFIG_MPC83xx) 85#if !defined(CONFIG_FSL_IFC) 86#define CONFIG_FSL_LBC 87#endif 88#endif 89 90/* The TSEC driver uses the PHYLIB infrastructure */ 91#ifndef CONFIG_PHYLIB 92#if defined(CONFIG_TSEC_ENET) 93#define CONFIG_PHYLIB 94 95#include <config_phylib_all_drivers.h> 96#endif /* TSEC_ENET */ 97#endif /* !CONFIG_PHYLIB */ 98 99/* The FMAN driver uses the PHYLIB infrastructure */ 100#if defined(CONFIG_FMAN_ENET) 101#define CONFIG_PHYLIB 102#endif 103 104/* All PPC boards must swap IDE bytes */ 105#define CONFIG_IDE_SWAP_IO 106 107#if defined(CONFIG_DM_SERIAL) 108/* 109 * TODO: Convert this to a clock driver exists that can give us the UART 110 * clock here. 111 */ 112#define CONFIG_SYS_NS16550_CLK get_serial_clock() 113#endif 114 115#endif /* _ASM_CONFIG_H_ */ 116