LXR uboot/arch/sparc/cpu/leon3/memcfg.c

   1/* GRLIB Memory controller setup. The register values are used
   2 * from the associated low level assembler routine implemented
   3 * in memcfg_low.S.
   4 *
   5 * (C) Copyright 2010, 2015
   6 * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#include <ambapp.h>
  12#include "memcfg.h"
  13#include <config.h>
  14
  15#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
  16struct mctrl_setup esa_mctrl1_cfg = {
  17        .reg_mask = 0x7,
  18        .regs = {
  19                {
  20                        .mask = 0x00000300,
  21                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1,
  22                },
  23                {
  24                        .mask = 0x00000000,
  25                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2,
  26                },
  27                {
  28                        .mask = 0x00000000,
  29                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3,
  30                },
  31        }
  32};
  33#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
  34struct mctrl_setup esa_mctrl2_cfg = {
  35        .reg_mask = 0x7,
  36        .regs = {
  37                {
  38                        .mask = 0x00000300,
  39                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1,
  40                },
  41                {
  42                        .mask = 0x00000000,
  43                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2,
  44                },
  45                {
  46                        .mask = 0x00000000,
  47                        .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3,
  48                },
  49        }
  50};
  51#endif
  52#endif
  53
  54#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
  55struct mctrl_setup gaisler_ftmctrl1_cfg = {
  56        .reg_mask = 0x7,
  57        .regs = {
  58                {
  59                        .mask = 0x00000300,
  60                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1,
  61                },
  62                {
  63                        .mask = 0x00000000,
  64                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2,
  65                },
  66                {
  67                        .mask = 0x00000000,
  68                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3,
  69                },
  70        }
  71};
  72#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
  73struct mctrl_setup gaisler_ftmctrl2_cfg = {
  74        .reg_mask = 0x7,
  75        .regs = {
  76                {
  77                        .mask = 0x00000300,
  78                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1,
  79                },
  80                {
  81                        .mask = 0x00000000,
  82                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2,
  83                },
  84                {
  85                        .mask = 0x00000000,
  86                        .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3,
  87                },
  88        }
  89};
  90#endif
  91#endif
  92
  93#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
  94struct mctrl_setup gaisler_sdctrl1_cfg = {
  95        .reg_mask = 0x1,
  96        .regs = {
  97                {
  98                        .mask = 0x00000000,
  99                        .value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL,
 100                },
 101        }
 102};
 103#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
 104struct mctrl_setup gaisler_sdctrl2_cfg = {
 105        .reg_mask = 0x1,
 106        .regs = {
 107                {
 108                        .mask = 0x00000000,
 109                        .value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL,
 110                },
 111        }
 112};
 113#endif
 114#endif
 115
 116#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
 117struct ahbmctrl_setup gaisler_ddr2spa1_cfg = {
 118        .ahb_mbar_no = 1,
 119        .reg_mask = 0xd,
 120        .regs = {
 121                {
 122                        .mask = 0x00000000,
 123                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1,
 124                },
 125                { 0x00000000, 0},
 126                {
 127                        .mask = 0x00000000,
 128                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3,
 129                },
 130                {
 131                        .mask = 0x00000000,
 132                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4,
 133                },
 134        }
 135};
 136#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
 137struct ahbmctrl_setup gaisler_ddr2spa2_cfg = {
 138        .ahb_mbar_no = 1,
 139        .reg_mask = 0xd,
 140        .regs = {
 141                {
 142                        .mask = 0x00000000,
 143                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1,
 144                },
 145                { 0x00000000, 0},
 146                {
 147                        .mask = 0x00000000,
 148                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3,
 149                },
 150                {
 151                        .mask = 0x00000000,
 152                        .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4,
 153                },
 154        }
 155};
 156#endif
 157#endif
 158
 159#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
 160struct ahbmctrl_setup gaisler_ddrspa1_cfg = {
 161        .ahb_mbar_no = 1,
 162        .reg_mask = 0x1,
 163        .regs = {
 164                {
 165                        .mask = 0x00000000,
 166                        .value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL,
 167                },
 168        }
 169};
 170#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
 171struct ahbmctrl_setup gaisler_ddrspa2_cfg = {
 172        .ahb_mbar_no = 1,
 173        .reg_mask = 0x1,
 174        .regs = {
 175                {
 176                        .mask = 0x00000000,
 177                        .value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL,
 178                },
 179        }
 180};
 181#endif
 182#endif
 183
 184struct grlib_mctrl_handler grlib_mctrl_handlers[] = {
 185/* ESA MCTRL (PROM/FLASH/IO/SRAM/SDRAM) */
 186#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
 187        {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
 188        _nomem_mctrl_init, (void *)&esa_mctrl1_cfg},
 189#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
 190        {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
 191        _nomem_mctrl_init, (void *)&esa_mctrl2_cfg},
 192#endif
 193#endif
 194
 195/* GAISLER Fault Tolerant Memory controller (PROM/FLASH/IO/SRAM/SDRAM) */
 196#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
 197        {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
 198        _nomem_mctrl_init, (void *)&gaisler_ftmctrl1_cfg},
 199#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
 200        {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
 201        _nomem_mctrl_init, (void *)&gaisler_ftmctrl2_cfg},
 202#endif
 203#endif
 204
 205/* GAISLER SDRAM-only Memory controller (SDRAM) */
 206#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
 207        {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
 208        _nomem_mctrl_init, (void *)&gaisler_sdctrl1_cfg},
 209#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
 210        {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
 211        _nomem_mctrl_init, (void *)&gaisler_sdctrl2_cfg},
 212#endif
 213#endif
 214
 215/* GAISLER DDR Memory controller (DDR) */
 216#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
 217        {DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
 218        _nomem_ahbmctrl_init, (void *)&gaisler_ddrspa1_cfg},
 219#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
 220        {DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
 221        _nomem_ahbmctrl_init, (void *)&gaisler_ddrspa2_cfg},
 222#endif
 223#endif
 224
 225/* GAISLER DDR2 Memory controller (DDR2) */
 226#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
 227        {DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
 228        _nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa1_cfg},
 229#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
 230        {DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
 231        _nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa2_cfg},
 232#endif
 233#endif
 234
 235        /* Mark end */
 236        MH_END
 237};
 238