1/* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Note: Part of this code has been derived from linux 8 */ 9#ifndef _USB_UHCI_H_ 10#define _USB_UHCI_H_ 11 12/* Command register */ 13#define USBCMD 0 14#define USBCMD_RS 0x0001 /* Run/Stop */ 15#define USBCMD_HCRESET 0x0002 /* Host reset */ 16#define USBCMD_GRESET 0x0004 /* Global reset */ 17#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 18#define USBCMD_FGR 0x0010 /* Force Global Resume */ 19#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 20#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 21#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 22 23/* Status register */ 24#define USBSTS 2 25#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 26#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 27#define USBSTS_RD 0x0004 /* Resume Detect */ 28#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ 29#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ 30#define USBSTS_HCH 0x0020 /* HC Halted */ 31 32/* Interrupt enable register */ 33#define USBINTR 4 34#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 35#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 36#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 37#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 38 39#define USBFRNUM 6 40#define USBFLBASEADD 8 41#define USBSOF 12 42 43/* USB port status and control registers */ 44#define USBPORTSC1 16 45#define USBPORTSC2 18 46#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ 47#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 48#define USBPORTSC_PE 0x0004 /* Port Enable */ 49#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 50#define USBPORTSC_LS 0x0030 /* Line Status */ 51#define USBPORTSC_RD 0x0040 /* Resume Detect */ 52#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 53#define USBPORTSC_PR 0x0200 /* Port Reset */ 54#define USBPORTSC_SUSP 0x1000 /* Suspend */ 55 56/* Legacy support register */ 57#define USBLEGSUP 0xc0 58#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 59 60#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */ 61#define UHCI_PID 0xff /* PID MASK */ 62 63#define UHCI_PTR_BITS 0x000F 64#define UHCI_PTR_TERM 0x0001 65#define UHCI_PTR_QH 0x0002 66#define UHCI_PTR_DEPTH 0x0004 67 68/* for TD <status>: */ 69#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 70#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 71#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 72#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 73#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 74#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 75#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 76#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 77#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 78#define TD_CTRL_NAK (1 << 19) /* NAK Received */ 79#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 80#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 81#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ 82 83#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ 84 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) 85 86#define TD_TOKEN_TOGGLE 19 87 88/* ------------------------------------------------------------------------------------ 89 Virtual Root HUB 90 ------------------------------------------------------------------------------------ */ 91/* destination of request */ 92#define RH_INTERFACE 0x01 93#define RH_ENDPOINT 0x02 94#define RH_OTHER 0x03 95 96#define RH_CLASS 0x20 97#define RH_VENDOR 0x40 98 99/* Requests: bRequest << 8 | bmRequestType */ 100#define RH_GET_STATUS 0x0080 101#define RH_CLEAR_FEATURE 0x0100 102#define RH_SET_FEATURE 0x0300 103#define RH_SET_ADDRESS 0x0500 104#define RH_GET_DESCRIPTOR 0x0680 105#define RH_SET_DESCRIPTOR 0x0700 106#define RH_GET_CONFIGURATION 0x0880 107#define RH_SET_CONFIGURATION 0x0900 108#define RH_GET_STATE 0x0280 109#define RH_GET_INTERFACE 0x0A80 110#define RH_SET_INTERFACE 0x0B00 111#define RH_SYNC_FRAME 0x0C80 112/* Our Vendor Specific Request */ 113#define RH_SET_EP 0x2000 114 115/* Hub port features */ 116#define RH_PORT_CONNECTION 0x00 117#define RH_PORT_ENABLE 0x01 118#define RH_PORT_SUSPEND 0x02 119#define RH_PORT_OVER_CURRENT 0x03 120#define RH_PORT_RESET 0x04 121#define RH_PORT_POWER 0x08 122#define RH_PORT_LOW_SPEED 0x09 123#define RH_C_PORT_CONNECTION 0x10 124#define RH_C_PORT_ENABLE 0x11 125#define RH_C_PORT_SUSPEND 0x12 126#define RH_C_PORT_OVER_CURRENT 0x13 127#define RH_C_PORT_RESET 0x14 128 129/* Hub features */ 130#define RH_C_HUB_LOCAL_POWER 0x00 131#define RH_C_HUB_OVER_CURRENT 0x01 132 133#define RH_DEVICE_REMOTE_WAKEUP 0x00 134#define RH_ENDPOINT_STALL 0x01 135 136/* Our Vendor Specific feature */ 137#define RH_REMOVE_EP 0x00 138 139#define RH_ACK 0x01 140#define RH_REQ_ERR -1 141#define RH_NACK 0x00 142 143/* Transfer descriptor structure */ 144typedef struct { 145 unsigned long link; /* next td/qh (LE) */ 146 unsigned long status; /* status of the td */ 147 unsigned long info; /* Max Lenght / Endpoint / device address and PID */ 148 unsigned long buffer; /* pointer to data buffer (LE) */ 149 unsigned long dev_ptr; /* pointer to the assigned device (BE) */ 150 unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ 151} uhci_td_t, *puhci_td_t; 152 153/* Queue Header structure */ 154typedef struct { 155 unsigned long head; /* Next QH (LE) */ 156 unsigned long element; /* Queue element pointer (LE) */ 157 unsigned long res[5]; /* reserved */ 158 unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ 159} uhci_qh_t, *puhci_qh_t; 160 161struct virt_root_hub { 162 int devnum; /* Address of Root Hub endpoint */ 163 int numports; /* number of ports */ 164 int c_p_r[8]; /* C_PORT_RESET */ 165}; 166 167#endif /* _USB_UHCI_H_ */ 168