LXR uboot/board/CarMediaLab/flea3/flea3.c

   1/*
   2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3 *
   4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   5 *
   6 * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#include <common.h>
  12#include <asm/io.h>
  13#include <asm/errno.h>
  14#include <asm/arch/imx-regs.h>
  15#include <asm/arch/crm_regs.h>
  16#include <asm/arch/iomux-mx35.h>
  17#include <i2c.h>
  18#include <linux/types.h>
  19#include <asm/gpio.h>
  20#include <asm/arch/sys_proto.h>
  21#include <netdev.h>
  22
  23#ifndef CONFIG_BOARD_EARLY_INIT_F
  24#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  25#endif
  26
  27#define CCM_CCMR_CONFIG         0x003F4208
  28
  29#define ESDCTL_DDR2_CONFIG      0x007FFC3F
  30#define ESDCTL_0x92220000       0x92220000
  31#define ESDCTL_0xA2220000       0xA2220000
  32#define ESDCTL_0xB2220000       0xB2220000
  33#define ESDCTL_0x82228080       0x82228080
  34#define ESDCTL_DDR2_EMR2        0x04000000
  35#define ESDCTL_DDR2_EMR3        0x06000000
  36#define ESDCTL_PRECHARGE        0x00000400
  37#define ESDCTL_DDR2_EN_DLL      0x02000400
  38#define ESDCTL_DDR2_RESET_DLL   0x00000333
  39#define ESDCTL_DDR2_MR          0x00000233
  40#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
  41#define ESDCTL_DELAY_LINE5      0x00F49F00
  42
  43static inline void dram_wait(unsigned int count)
  44{
  45        volatile unsigned int wait = count;
  46
  47        while (wait--)
  48                ;
  49}
  50
  51DECLARE_GLOBAL_DATA_PTR;
  52
  53int dram_init(void)
  54{
  55        gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  56                PHYS_SDRAM_1_SIZE);
  57
  58        return 0;
  59}
  60
  61static void board_setup_sdram_bank(u32 start_address)
  62
  63{
  64        struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  65        u32 *cfg_reg, *ctl_reg;
  66        u32 val;
  67
  68        switch (start_address) {
  69        case CSD0_BASE_ADDR:
  70                cfg_reg = &esdc->esdcfg0;
  71                ctl_reg = &esdc->esdctl0;
  72                break;
  73        case CSD1_BASE_ADDR:
  74                cfg_reg = &esdc->esdcfg1;
  75                ctl_reg = &esdc->esdctl1;
  76                break;
  77        default:
  78                return;
  79        }
  80
  81        /* Initialize MISC register for DDR2 */
  82        val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
  83                ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
  84        writel(val, &esdc->esdmisc);
  85        val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
  86        writel(val, &esdc->esdmisc);
  87
  88        /*
  89         * according to DDR2 specs, wait a while before
  90         * the PRECHARGE_ALL command
  91         */
  92        dram_wait(0x20000);
  93
  94        /* Load DDR2 config and timing */
  95        writel(ESDCTL_DDR2_CONFIG, cfg_reg);
  96
  97        /* Precharge ALL */
  98        writel(ESDCTL_0x92220000,
  99                ctl_reg);
 100        writel(0xda, start_address + ESDCTL_PRECHARGE);
 101
 102        /* Load mode */
 103        writel(ESDCTL_0xB2220000,
 104                ctl_reg);
 105        writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
 106        writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
 107        writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
 108        writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
 109
 110        /* Precharge ALL */
 111        writel(ESDCTL_0x92220000,
 112                ctl_reg);
 113        writel(0xda, start_address + ESDCTL_PRECHARGE);
 114
 115        /* Set mode auto refresh : at least two refresh are required */
 116        writel(ESDCTL_0xA2220000,
 117                ctl_reg);
 118        writel(0xda, start_address);
 119        writel(0xda, start_address);
 120
 121        writel(ESDCTL_0xB2220000,
 122                ctl_reg);
 123        writeb(0xda, start_address + ESDCTL_DDR2_MR);
 124        writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
 125
 126        /* OCD mode exit */
 127        writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
 128
 129        /* Set normal mode */
 130        writel(ESDCTL_0x82228080,
 131                ctl_reg);
 132
 133        dram_wait(0x20000);
 134
 135        /* Do not set delay lines, only for MDDR */
 136}
 137
 138static void board_setup_sdram(void)
 139{
 140        struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
 141
 142        /* Initialize with default values both CSD0/1 */
 143        writel(0x2000, &esdc->esdctl0);
 144        writel(0x2000, &esdc->esdctl1);
 145
 146        board_setup_sdram_bank(CSD0_BASE_ADDR);
 147}
 148
 149static void setup_iomux_uart3(void)
 150{
 151        static const iomux_v3_cfg_t uart3_pads[] = {
 152                MX35_PAD_RTS2__UART3_RXD_MUX,
 153                MX35_PAD_CTS2__UART3_TXD_MUX,
 154        };
 155
 156        imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 157}
 158
 159#define I2C_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
 160
 161static void setup_iomux_i2c(void)
 162{
 163        static const iomux_v3_cfg_t i2c_pads[] = {
 164                NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
 165                NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
 166
 167                NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
 168                NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
 169        };
 170
 171        imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 172}
 173
 174
 175static void setup_iomux_spi(void)
 176{
 177        static const iomux_v3_cfg_t spi_pads[] = {
 178                MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
 179                MX35_PAD_CSPI1_MISO__CSPI1_MISO,
 180                MX35_PAD_CSPI1_SS0__CSPI1_SS0,
 181                MX35_PAD_CSPI1_SS1__CSPI1_SS1,
 182                MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
 183        };
 184
 185        imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 186}
 187
 188static void setup_iomux_fec(void)
 189{
 190        static const iomux_v3_cfg_t fec_pads[] = {
 191                MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 192                MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 193                MX35_PAD_FEC_RX_DV__FEC_RX_DV,
 194                MX35_PAD_FEC_COL__FEC_COL,
 195                MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
 196                MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
 197                MX35_PAD_FEC_TX_EN__FEC_TX_EN,
 198                MX35_PAD_FEC_MDC__FEC_MDC,
 199                MX35_PAD_FEC_MDIO__FEC_MDIO,
 200                MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
 201                MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
 202                MX35_PAD_FEC_CRS__FEC_CRS,
 203                MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
 204                MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
 205                MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
 206                MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 207                MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 208                MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
 209        };
 210
 211        /* setup pins for FEC */
 212        imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 213}
 214
 215int board_early_init_f(void)
 216{
 217        struct ccm_regs *ccm =
 218                (struct ccm_regs *)IMX_CCM_BASE;
 219
 220        /* setup GPIO3_1 to set HighVCore signal */
 221        imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
 222        gpio_direction_output(65, 1);
 223
 224        /* initialize PLL and clock configuration */
 225        writel(CCM_CCMR_CONFIG, &ccm->ccmr);
 226
 227        writel(CCM_MPLL_532_HZ, &ccm->mpctl);
 228        writel(CCM_PPLL_300_HZ, &ccm->ppctl);
 229
 230        /* Set the core to run at 532 Mhz */
 231        writel(0x00001000, &ccm->pdr0);
 232
 233        /* Set-up RAM */
 234        board_setup_sdram();
 235
 236        /* enable clocks */
 237        writel(readl(&ccm->cgr0) |
 238                MXC_CCM_CGR0_EMI_MASK |
 239                MXC_CCM_CGR0_EDIO_MASK |
 240                MXC_CCM_CGR0_EPIT1_MASK,
 241                &ccm->cgr0);
 242
 243        writel(readl(&ccm->cgr1) |
 244                MXC_CCM_CGR1_FEC_MASK |
 245                MXC_CCM_CGR1_GPIO1_MASK |
 246                MXC_CCM_CGR1_GPIO2_MASK |
 247                MXC_CCM_CGR1_GPIO3_MASK |
 248                MXC_CCM_CGR1_I2C1_MASK |
 249                MXC_CCM_CGR1_I2C2_MASK |
 250                MXC_CCM_CGR1_I2C3_MASK,
 251                &ccm->cgr1);
 252
 253        /* Set-up NAND */
 254        __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 255
 256        /* Set pinmux for the required peripherals */
 257        setup_iomux_uart3();
 258        setup_iomux_i2c();
 259        setup_iomux_fec();
 260        setup_iomux_spi();
 261
 262        return 0;
 263}
 264
 265int board_init(void)
 266{
 267        /* address of boot parameters */
 268        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 269
 270        return 0;
 271}
 272
 273u32 get_board_rev(void)
 274{
 275        int rev = 0;
 276
 277        return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 278}
 279