LXR uboot/board/amcc/walnut/walnut.c

   1/*
   2 * (C) Copyright 2000-2005
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/processor.h>
  10#include <spd_sdram.h>
  11
  12int board_early_init_f(void)
  13{
  14        /*-------------------------------------------------------------------------+
  15          | Interrupt controller setup for the Walnut/Sycamore board.
  16          | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  17          |       IRQ 16    405GP internally generated; active low; level sensitive
  18          |       IRQ 17-24 RESERVED
  19          |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  20          |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  21          |       IRQ 27 (EXT IRQ 2) Not Used
  22          |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  23          |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  24          |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  25          |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  26          | Note for Walnut board:
  27          |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  28          |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  29          |       interrupt. The FPGA must be read to determine which device
  30          |       caused the interrupt. The default setting of the FPGA clears
  31          |
  32          +-------------------------------------------------------------------------*/
  33
  34        mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  35        mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  36        mtdcr(UIC0CR, 0x00000020);      /* set all but FPGA SMI to be non-critical */
  37        mtdcr(UIC0PR, 0xFFFFFFE0);      /* set int polarities */
  38        mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  39        mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority */
  40        mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  41
  42        /* set UART1 control to select CTS/RTS */
  43#define FPGA_BRDC       0xF0300004
  44        *(volatile char *)(FPGA_BRDC) |= 0x1;
  45
  46        return 0;
  47}
  48
  49/*
  50 * Check Board Identity:
  51 */
  52int checkboard(void)
  53{
  54        char buf[64];
  55        int i = getenv_f("serial#", buf, sizeof(buf));
  56        uint pvr = get_pvr();
  57
  58        if (pvr == PVR_405GPR_RB) {
  59                puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
  60        } else {
  61                puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
  62        }
  63
  64        if (i > 0) {
  65                puts(", serial# ");
  66                puts(buf);
  67        }
  68        putc('\n');
  69
  70        return (0);
  71}
  72
  73/*
  74 * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  75 * the necessary info for SDRAM controller configuration
  76 */
  77phys_size_t initdram(int board_type)
  78{
  79        return spd_sdram();
  80}
  81