LXR uboot/board/freescale/mpc8560ads/mpc8560ads.c

   1/*
   2 * Copyright 2004 Freescale Semiconductor.
   3 * (C) Copyright 2003,Motorola Inc.
   4 * Xianghua Xiao, (X.Xiao@motorola.com)
   5 *
   6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11
  12#include <common.h>
  13#include <pci.h>
  14#include <asm/processor.h>
  15#include <asm/mmu.h>
  16#include <asm/immap_85xx.h>
  17#include <fsl_ddr_sdram.h>
  18#include <ioports.h>
  19#include <spd_sdram.h>
  20#include <miiphy.h>
  21#include <libfdt.h>
  22#include <fdt_support.h>
  23#include <asm/fsl_lbc.h>
  24
  25#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  26extern void ddr_enable_ecc(unsigned int dram_size);
  27#endif
  28
  29
  30void local_bus_init(void);
  31
  32
  33/*
  34 * I/O Port configuration table
  35 *
  36 * if conf is 1, then that port pin will be configured at boot time
  37 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  38 */
  39
  40const iop_conf_t iop_conf_tab[4][32] = {
  41
  42    /* Port A configuration */
  43    {   /*            conf ppar psor pdir podr pdat */
  44        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  45        /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  46        /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  47        /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  48        /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  49        /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  50        /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  51        /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  52        /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  53        /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  54        /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  55        /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  56        /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  57        /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  58        /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  59        /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  60        /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  61        /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  62        /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  63        /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  64        /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  65        /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  66        /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  67        /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  68        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  69        /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  70        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  71        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  72        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  73        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  74        /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  75        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  76    },
  77
  78    /* Port B configuration */
  79    {   /*            conf ppar psor pdir podr pdat */
  80        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  81        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  82        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  83        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  84        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  85        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  86        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  87        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  88        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  89        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  90        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  91        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
  92        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
  93        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
  94        /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
  95        /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
  96        /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
  97        /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
  98        /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
  99        /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 100        /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 101        /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 102        /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 103        /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 104        /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 105        /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 106        /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 107        /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 108        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 109        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 110        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 111        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 112    },
 113
 114    /* Port C */
 115    {   /*            conf ppar psor pdir podr pdat */
 116        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 117        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 118        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 119        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 120        /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 121        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 122        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 123        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 124        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 125        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 126        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 127        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 128        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 129        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 130        /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 131        /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 132        /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 133        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 134        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 135        /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 136        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 137        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 138        /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 139        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 140        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 141        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 142        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 143        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 144        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 145        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 146        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 147        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 148    },
 149
 150    /* Port D */
 151    {   /*            conf ppar psor pdir podr pdat */
 152        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 153        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 154        /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 155        /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 156        /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 157        /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 158        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 159        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 160        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 161        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 162        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 163        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 164        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 165        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 166        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 167        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 168        /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 169        /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 170        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 171        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 172        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 173        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 174        /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 175        /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 176        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 177        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 178        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 179        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 180        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 181        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 182        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 183        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 184    }
 185};
 186
 187
 188/*
 189 * MPC8560ADS Board Status & Control Registers
 190 */
 191typedef struct bcsr_ {
 192        volatile unsigned char bcsr0;
 193        volatile unsigned char bcsr1;
 194        volatile unsigned char bcsr2;
 195        volatile unsigned char bcsr3;
 196        volatile unsigned char bcsr4;
 197        volatile unsigned char bcsr5;
 198} bcsr_t;
 199
 200void reset_phy (void)
 201{
 202#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 203        volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
 204#endif
 205        /* reset Giga bit Ethernet port if needed here */
 206
 207        /* reset the CPM FEC port */
 208#if (CONFIG_ETHER_INDEX == 2)
 209        bcsr->bcsr2 &= ~FETH2_RST;
 210        udelay(2);
 211        bcsr->bcsr2 |=  FETH2_RST;
 212        udelay(1000);
 213#elif (CONFIG_ETHER_INDEX == 3)
 214        bcsr->bcsr3 &= ~FETH3_RST;
 215        udelay(2);
 216        bcsr->bcsr3 |=  FETH3_RST;
 217        udelay(1000);
 218#endif
 219#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 220        /* reset PHY */
 221        miiphy_reset("FCC1", 0x0);
 222
 223        /* change PHY address to 0x02 */
 224        bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
 225
 226        bb_miiphy_write(NULL, 0x02, MII_BMCR,
 227                        BMCR_ANENABLE | BMCR_ANRESTART);
 228#endif /* CONFIG_MII */
 229}
 230
 231
 232int checkboard (void)
 233{
 234        puts("Board: ADS\n");
 235
 236#ifdef CONFIG_PCI
 237        printf("PCI1: 32 bit, %d MHz (compiled)\n",
 238               CONFIG_SYS_CLK_FREQ / 1000000);
 239#else
 240        printf("PCI1: disabled\n");
 241#endif
 242
 243        /*
 244         * Initialize local bus.
 245         */
 246        local_bus_init();
 247
 248        return 0;
 249}
 250
 251/*
 252 * Initialize Local Bus
 253 */
 254
 255void
 256local_bus_init(void)
 257{
 258        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 259        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 260
 261        uint clkdiv;
 262        uint lbc_hz;
 263        sys_info_t sysinfo;
 264
 265        /*
 266         * Errata LBC11.
 267         * Fix Local Bus clock glitch when DLL is enabled.
 268         *
 269         * If localbus freq is < 66MHz, DLL bypass mode must be used.
 270         * If localbus freq is > 133MHz, DLL can be safely enabled.
 271         * Between 66 and 133, the DLL is enabled with an override workaround.
 272         */
 273
 274        get_sys_info(&sysinfo);
 275        clkdiv = lbc->lcrr & LCRR_CLKDIV;
 276        lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 277
 278        if (lbc_hz < 66) {
 279                lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;    /* DLL Bypass */
 280
 281        } else if (lbc_hz >= 133) {
 282                lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
 283
 284        } else {
 285                /*
 286                 * On REV1 boards, need to change CLKDIV before enable DLL.
 287                 * Default CLKDIV is 8, change it to 4 temporarily.
 288                 */
 289                uint pvr = get_pvr();
 290                uint temp_lbcdll = 0;
 291
 292                if (pvr == PVR_85xx_REV1) {
 293                        /* FIXME: Justify the high bit here. */
 294                        lbc->lcrr = 0x10000004;
 295                }
 296
 297                lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
 298                udelay(200);
 299
 300                /*
 301                 * Sample LBC DLL ctrl reg, upshift it to set the
 302                 * override bits.
 303                 */
 304                temp_lbcdll = gur->lbcdllcr;
 305                gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 306                asm("sync;isync;msync");
 307        }
 308}
 309
 310
 311/*
 312 * Initialize SDRAM memory on the Local Bus.
 313 */
 314void lbc_sdram_init(void)
 315{
 316        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 317        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 318
 319        puts("LBC SDRAM: ");
 320        print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 321                   "\n       ");
 322
 323        /*
 324         * Setup SDRAM Base and Option Registers
 325         */
 326        set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 327        set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 328        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 329        asm("msync");
 330
 331        lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 332        lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 333        asm("sync");
 334
 335        /*
 336         * Configure the SDRAM controller.
 337         */
 338        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 339        asm("sync");
 340        *sdram_addr = 0xff;
 341        ppcDcbf((unsigned long) sdram_addr);
 342        udelay(100);
 343
 344        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 345        asm("sync");
 346        *sdram_addr = 0xff;
 347        ppcDcbf((unsigned long) sdram_addr);
 348        udelay(100);
 349
 350        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 351        asm("sync");
 352        *sdram_addr = 0xff;
 353        ppcDcbf((unsigned long) sdram_addr);
 354        udelay(100);
 355
 356        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 357        asm("sync");
 358        *sdram_addr = 0xff;
 359        ppcDcbf((unsigned long) sdram_addr);
 360        udelay(100);
 361
 362        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 363        asm("sync");
 364        *sdram_addr = 0xff;
 365        ppcDcbf((unsigned long) sdram_addr);
 366        udelay(100);
 367}
 368
 369#if !defined(CONFIG_SPD_EEPROM)
 370/*************************************************************************
 371 *  fixed sdram init -- doesn't use serial presence detect.
 372 ************************************************************************/
 373phys_size_t fixed_sdram(void)
 374{
 375  #ifndef CONFIG_SYS_RAMBOOT
 376        volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
 377
 378        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 379        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 380        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 381        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 382        ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 383        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 384    #if defined (CONFIG_DDR_ECC)
 385        ddr->err_disable = 0x0000000D;
 386        ddr->err_sbe = 0x00ff0000;
 387    #endif
 388        asm("sync;isync;msync");
 389        udelay(500);
 390    #if defined (CONFIG_DDR_ECC)
 391        /* Enable ECC checking */
 392        ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 393    #else
 394        ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 395    #endif
 396        asm("sync; isync; msync");
 397        udelay(500);
 398  #endif
 399        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 400}
 401#endif  /* !defined(CONFIG_SPD_EEPROM) */
 402
 403
 404#if defined(CONFIG_PCI)
 405/*
 406 * Initialize PCI Devices, report devices found.
 407 */
 408
 409#ifndef CONFIG_PCI_PNP
 410static struct pci_config_table pci_mpc85xxads_config_table[] = {
 411    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 412      PCI_IDSEL_NUMBER, PCI_ANY_ID,
 413      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 414                                   PCI_ENET0_MEMADDR,
 415                                   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 416      } },
 417    { }
 418};
 419#endif
 420
 421
 422static struct pci_controller hose = {
 423#ifndef CONFIG_PCI_PNP
 424        config_table: pci_mpc85xxads_config_table,
 425#endif
 426};
 427
 428#endif  /* CONFIG_PCI */
 429
 430
 431void
 432pci_init_board(void)
 433{
 434#ifdef CONFIG_PCI
 435        pci_mpc85xx_init(&hose);
 436#endif /* CONFIG_PCI */
 437}
 438
 439
 440#if defined(CONFIG_OF_BOARD_SETUP)
 441int ft_board_setup(void *blob, bd_t *bd)
 442{
 443        int node, tmp[2];
 444        const char *path;
 445
 446        ft_cpu_setup(blob, bd);
 447
 448        node = fdt_path_offset(blob, "/aliases");
 449        tmp[0] = 0;
 450        if (node >= 0) {
 451#ifdef CONFIG_PCI
 452                path = fdt_getprop(blob, node, "pci0", NULL);
 453                if (path) {
 454                        tmp[1] = hose.last_busno - hose.first_busno;
 455                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 456                }
 457#endif
 458        }
 459
 460        return 0;
 461}
 462#endif
 463