uboot/board/freescale/mx6qarm2/mx6qarm2.c
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   1/*
   2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/io.h>
   9#include <asm/arch/imx-regs.h>
  10#include <asm/arch/mx6-pins.h>
  11#include <asm/arch/clock.h>
  12#include <asm/errno.h>
  13#include <asm/gpio.h>
  14#include <asm/imx-common/iomux-v3.h>
  15#include <mmc.h>
  16#include <fsl_esdhc.h>
  17#include <miiphy.h>
  18#include <netdev.h>
  19#include <usb.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  24        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  25        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  26
  27#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  28        PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  29        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  30
  31#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  32        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  33
  34int dram_init(void)
  35{
  36#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
  37        defined(CONFIG_DDR_32BIT)
  38        gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
  39#else
  40        gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  41#endif
  42
  43        return 0;
  44}
  45
  46iomux_v3_cfg_t const uart4_pads[] = {
  47        MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48        MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49};
  50
  51iomux_v3_cfg_t const usdhc3_pads[] = {
  52        MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53        MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54        MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55        MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56        MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57        MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58        MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59        MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60        MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61        MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62        MX6_PAD_NANDF_CS0__GPIO6_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  63};
  64
  65iomux_v3_cfg_t const usdhc4_pads[] = {
  66        MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67        MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68        MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69        MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70        MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71        MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72        MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73        MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74        MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75        MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76};
  77
  78iomux_v3_cfg_t const enet_pads[] = {
  79        MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80        MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81        MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82        MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83        MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84        MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85        MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86        MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87        MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88        MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89        MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90        MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91        MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92        MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93        MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94};
  95
  96
  97static void setup_iomux_uart(void)
  98{
  99        imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 100}
 101
 102static void setup_iomux_enet(void)
 103{
 104        imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 105}
 106
 107#ifdef CONFIG_FSL_ESDHC
 108struct fsl_esdhc_cfg usdhc_cfg[2] = {
 109        {USDHC3_BASE_ADDR},
 110        {USDHC4_BASE_ADDR},
 111};
 112
 113int board_mmc_get_env_dev(int devno)
 114{
 115        return devno - 2;
 116}
 117
 118int board_mmc_getcd(struct mmc *mmc)
 119{
 120        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 121        int ret;
 122
 123        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 124                gpio_direction_input(IMX_GPIO_NR(6, 11));
 125                ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
 126        } else /* Don't have the CD GPIO pin on board */
 127                ret = 1;
 128
 129        return ret;
 130}
 131
 132int board_mmc_init(bd_t *bis)
 133{
 134        int ret;
 135        u32 index = 0;
 136
 137        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 138        usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 139
 140        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 141                switch (index) {
 142                case 0:
 143                        imx_iomux_v3_setup_multiple_pads(
 144                                usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 145                        break;
 146                case 1:
 147                        imx_iomux_v3_setup_multiple_pads(
 148                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 149                        break;
 150                default:
 151                        printf("Warning: you configured more USDHC controllers"
 152                                "(%d) then supported by the board (%d)\n",
 153                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 154                        return -EINVAL;
 155                }
 156
 157                ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 158                if (ret)
 159                        return ret;
 160        }
 161
 162        return 0;
 163}
 164#endif
 165
 166#define MII_MMD_ACCESS_CTRL_REG         0xd
 167#define MII_MMD_ACCESS_ADDR_DATA_REG    0xe
 168#define MII_DBG_PORT_REG                0x1d
 169#define MII_DBG_PORT2_REG               0x1e
 170
 171int fecmxc_mii_postcall(int phy)
 172{
 173        unsigned short val;
 174
 175        /*
 176         * Due to the i.MX6Q Armadillo2 board HW design,there is
 177         * no 125Mhz clock input from SOC. In order to use RGMII,
 178         * We need enable AR8031 ouput a 125MHz clk from CLK_25M
 179         */
 180        miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
 181        miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
 182        miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
 183        miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
 184        val &= 0xffe3;
 185        val |= 0x18;
 186        miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
 187
 188        /* For the RGMII phy, we need enable tx clock delay */
 189        miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
 190        miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
 191        val |= 0x0100;
 192        miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
 193
 194        miiphy_write("FEC", phy, MII_BMCR, 0xa100);
 195
 196        return 0;
 197}
 198
 199int board_eth_init(bd_t *bis)
 200{
 201        struct eth_device *dev;
 202        int ret = cpu_eth_init(bis);
 203
 204        if (ret)
 205                return ret;
 206
 207        dev = eth_get_dev_by_name("FEC");
 208        if (!dev) {
 209                printf("FEC MXC: Unable to get FEC device entry\n");
 210                return -EINVAL;
 211        }
 212
 213        ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
 214        if (ret) {
 215                printf("FEC MXC: Unable to register FEC mii postcall\n");
 216                return ret;
 217        }
 218
 219        return 0;
 220}
 221
 222#ifdef CONFIG_USB_EHCI_MX6
 223#define USB_OTHERREGS_OFFSET    0x800
 224#define UCTRL_PWR_POL           (1 << 9)
 225
 226static iomux_v3_cfg_t const usb_otg_pads[] = {
 227        MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 228        MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 229};
 230
 231static void setup_usb(void)
 232{
 233        imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 234                                         ARRAY_SIZE(usb_otg_pads));
 235
 236        /*
 237         * set daisy chain for otg_pin_id on 6q.
 238         * for 6dl, this bit is reserved
 239         */
 240        imx_iomux_set_gpr_register(1, 13, 1, 1);
 241}
 242
 243int board_ehci_hcd_init(int port)
 244{
 245        u32 *usbnc_usb_ctrl;
 246
 247        if (port > 0)
 248                return -EINVAL;
 249
 250        usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 251                                 port * 4);
 252
 253        setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 254
 255        return 0;
 256}
 257#endif
 258
 259int board_early_init_f(void)
 260{
 261        setup_iomux_uart();
 262        setup_iomux_enet();
 263
 264        return 0;
 265}
 266
 267int board_init(void)
 268{
 269        /* address of boot parameters */
 270        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 271
 272#ifdef CONFIG_USB_EHCI_MX6
 273        setup_usb();
 274#endif
 275
 276        return 0;
 277}
 278
 279int checkboard(void)
 280{
 281#ifdef CONFIG_MX6DL
 282        puts("Board: MX6DL-Armadillo2\n");
 283#else
 284        puts("Board: MX6Q-Armadillo2\n");
 285#endif
 286
 287        return 0;
 288}
 289