LXR uboot/board/gdsys/common/adv7611.c

   1/*
   2 * (C) Copyright 2014
   3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <i2c.h>
  10
  11#define ADV7611_I2C_ADDR 0x4c
  12#define ADV7611_RDINFO 0x2051
  13
  14/*
  15 * ADV7611 I2C Addresses in u-boot notation
  16 */
  17enum {
  18        CP_I2C_ADDR = 0x22,
  19        DPLL_I2C_ADDR = 0x26,
  20        KSV_I2C_ADDR = 0x32,
  21        HDMI_I2C_ADDR = 0x34,
  22        EDID_I2C_ADDR = 0x36,
  23        INFOFRAME_I2C_ADDR = 0x3e,
  24        CEC_I2C_ADDR = 0x40,
  25        IO_I2C_ADDR = ADV7611_I2C_ADDR,
  26};
  27
  28/*
  29 * Global Control Registers
  30 */
  31enum {
  32        IO_RD_INFO_MSB = 0xea,
  33        IO_RD_INFO_LSB = 0xeb,
  34        IO_CEC_ADDR = 0xf4,
  35        IO_INFOFRAME_ADDR = 0xf5,
  36        IO_DPLL_ADDR = 0xf8,
  37        IO_KSV_ADDR = 0xf9,
  38        IO_EDID_ADDR = 0xfa,
  39        IO_HDMI_ADDR = 0xfb,
  40        IO_CP_ADDR = 0xfd,
  41};
  42
  43int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
  44
  45int adv7611_probe(unsigned int screen)
  46{
  47        int old_bus = i2c_get_bus_num();
  48        unsigned int rd_info;
  49        int res = 0;
  50
  51        i2c_set_bus_num(adv7611_i2c[screen]);
  52
  53        rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
  54                  | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
  55
  56        if (rd_info != ADV7611_RDINFO) {
  57                res = -1;
  58                goto out;
  59        }
  60
  61        /*
  62         * set I2C addresses to default values
  63         */
  64        i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
  65        i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
  66        i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
  67        i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
  68        i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
  69        i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
  70        i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
  71
  72        /*
  73         * do magic initialization sequence from
  74         * "ADV7611 Register Settings Recommendations Revision 1.5"
  75         * with most registers undocumented
  76         */
  77        i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
  78        i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
  79        i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
  80        i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
  81        i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
  82        i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
  83        i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
  84        i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
  85        i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
  86
  87        /*
  88         * IO_REG_02, default 0xf0
  89         *
  90         * INP_COLOR_SPACE (IO, Address 0x02[7:4])
  91         * default: 0b1111 auto
  92         * set to : 0b0001 force RGB (range 0 to 255) input
  93         *
  94         * RGB_OUT (IO, Address 0x02[1])
  95         * default: 0 YPbPr color space output
  96         * set to : 1 RGB color space output
  97         */
  98        i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
  99
 100        /*
 101         * IO_REG_03, default 0x00
 102         *
 103         * OP_FORMAT_SEL (IO, Address 0x03[7:0])
 104         * default: 0x00 8-bit SDR ITU-656 mode
 105         * set to : 0x40 24-bit 4:4:4 SDR mode
 106         */
 107        i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
 108
 109        /*
 110         * IO_REG_05, default 0x2c
 111         *
 112         * AVCODE_INSERT_EN (IO, Address 0x05[2])
 113         * default: 1 insert AV codes into data stream
 114         * set to : 0 do not insert AV codes into data stream
 115         */
 116        i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
 117
 118        /*
 119         * IO_REG_0C, default 0x62
 120         *
 121         * POWER_DOWN (IO, Address 0x0C[5])
 122         * default: 1 chip is powered down
 123         * set to : 0 chip is operational
 124         */
 125        i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
 126
 127        /*
 128         * IO_REG_15, default 0xbe
 129         *
 130         * TRI_SYNCS (IO, Address 0x15[3)
 131         * TRI_LLC (IO, Address 0x15[2])
 132         * TRI_PIX (IO, Address 0x15[1])
 133         * default: 1 video output pins are tristate
 134         * set to : 0 video output pins are active
 135         */
 136        i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
 137
 138        /*
 139         * HDMI_REGISTER_02H, default 0xff
 140         *
 141         * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
 142         * default: 1 disable termination
 143         * set to : 0 enable termination
 144         * Future options are:
 145         * - use the chips automatic termination control
 146         * - set this manually on cable detect
 147         * but at the moment this seems a safe default.
 148         */
 149        i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
 150
 151        /*
 152         * HDMI_CP_CNTRL_1, default 0x01
 153         *
 154         * HDMI_FRUN_EN (CP, Address 0xBA[0])
 155         * default: 1 Enable the free run feature in HDMI mode
 156         * set to : 0 Disable the free run feature in HDMI mode
 157         */
 158        i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
 159
 160        /*
 161         * INT1_CONFIGURATION, default 0x20
 162         *
 163         * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
 164         * default: 00 Interrupt signal is active for 4 Xtal periods
 165         * set to : 11 Active until cleared
 166         *
 167         * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
 168         * default: 00 Open drain
 169         * set to : 10 Drives high when active
 170         */
 171        i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
 172
 173out:
 174        i2c_set_bus_num(old_bus);
 175
 176        return res;
 177}
 178