LXR uboot/board/quipos/cairo/cairo.c

   1/*
   2 * Copyright (c) 2014 DENX
   3 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
   4 *
   5 * Derived from code written by Robert Aigner (ra@spiid.net)
   6 *
   7 * Itself derived from Beagle Board and 3430 SDP code by
   8 *      Richard Woodruff <r-woodruff2@ti.com>
   9 *      Syed Mohammed Khasim <khasim@ti.com>
  10 *
  11 * SPDX-License-Identifier:     GPL-2.0+
  12 */
  13#include <common.h>
  14#include <dm.h>
  15#include <netdev.h>
  16#include <ns16550.h>
  17#include <asm/io.h>
  18#include <asm/arch/mem.h>
  19#include <asm/arch/mux.h>
  20#include <asm/arch/sys_proto.h>
  21#include <i2c.h>
  22#include <asm/mach-types.h>
  23#include <asm/omap_mmc.h>
  24#include "cairo.h"
  25
  26DECLARE_GLOBAL_DATA_PTR;
  27
  28/*
  29 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
  30 */
  31u8 omap3_evm_need_extvbus(void)
  32{
  33        u8 retval = 0;
  34
  35        /* TODO: verify if cairo handheld platform needs extvbus programming */
  36
  37        return retval;
  38}
  39
  40/*
  41 * Routine: board_init
  42 * Description: Early hardware init.
  43 */
  44int board_init(void)
  45{
  46        gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  47        /* board id for Linux */
  48        gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
  49        /* boot param addr */
  50        gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  51        return 0;
  52}
  53
  54/*
  55 * Routine: set_muxconf_regs
  56 * Description: Setting up the configuration Mux registers specific to the
  57 *              hardware. Many pins need to be moved from protect to primary
  58 *              mode.
  59 */
  60void set_muxconf_regs(void)
  61{
  62        MUX_CAIRO();
  63}
  64
  65#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
  66int board_mmc_init(bd_t *bis)
  67{
  68        return omap_mmc_init(0, 0, 0, -1, -1);
  69}
  70#endif
  71
  72#ifdef CONFIG_SPL_BUILD
  73/*
  74 * Routine: get_board_mem_timings
  75 * Description: If we use SPL then there is no x-loader nor config header
  76 * so we have to setup the DDR timings ourself on the first bank.  This
  77 * provides the timing values back to the function that configures
  78 * the memory.
  79 *
  80 * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
  81 */
  82void get_board_mem_timings(struct board_sdrc_timings *timings)
  83{
  84        timings->sharing = SAMSUNG_SHARING;
  85        timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
  86        timings->ctrla = SAMSUNG_V_ACTIMA_165;
  87        timings->ctrlb = SAMSUNG_V_ACTIMB_165;
  88        timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  89        timings->mr = SAMSUNG_V_MR_165;
  90}
  91#endif
  92
  93static const struct ns16550_platdata cairo_serial = {
  94        .base = OMAP34XX_UART2,
  95        .reg_shift = 2,
  96        .clock = V_NS16550_CLK
  97};
  98
  99U_BOOT_DEVICE(cairo_uart) = {
 100        "ns16550_serial",
 101        &cairo_serial
 102};
 103
 104/* force SPL booting into U-Boot, not Linux */
 105#ifdef CONFIG_SPL_OS_BOOT
 106int spl_start_uboot(void)
 107{
 108        return 1;
 109}
 110#endif
 111