LXR uboot/board/schulercontrol/sc_sps_1/sc_sps

   1/*
   2 * SchulerControl GmbH, SC_SPS_1 module
   3 *
   4 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   5 * on behalf of DENX Software Engineering GmbH
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <asm/gpio.h>
  12#include <asm/io.h>
  13#include <asm/arch/imx-regs.h>
  14#include <asm/arch/iomux-mx28.h>
  15#include <asm/arch/clock.h>
  16#include <asm/arch/sys_proto.h>
  17#include <linux/mii.h>
  18#include <miiphy.h>
  19#include <netdev.h>
  20#include <errno.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24/*
  25 * Functions
  26 */
  27int board_early_init_f(void)
  28{
  29        /* IO0 clock at 480MHz */
  30        mxs_set_ioclk(MXC_IOCLK0, 480000);
  31        /* IO1 clock at 480MHz */
  32        mxs_set_ioclk(MXC_IOCLK1, 480000);
  33
  34        /* SSP0 clock at 96MHz */
  35        mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
  36        /* SSP2 clock at 96MHz */
  37        mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
  38
  39#ifdef  CONFIG_CMD_USB
  40        mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
  41        mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
  42                        MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
  43        gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
  44#endif
  45
  46        return 0;
  47}
  48
  49int board_init(void)
  50{
  51        /* Adress of boot parameters */
  52        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  53
  54        return 0;
  55}
  56
  57int dram_init(void)
  58{
  59        return mxs_dram_init();
  60}
  61
  62#ifdef  CONFIG_CMD_MMC
  63int board_mmc_init(bd_t *bis)
  64{
  65        return mxsmmc_initialize(bis, 0, NULL, NULL);
  66}
  67#endif
  68
  69#ifdef  CONFIG_CMD_NET
  70int board_eth_init(bd_t *bis)
  71{
  72        struct mxs_clkctrl_regs *clkctrl_regs =
  73                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  74        int ret;
  75
  76        ret = cpu_eth_init(bis);
  77
  78        clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  79                CLKCTRL_ENET_TIME_SEL_MASK,
  80                CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
  81
  82        ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
  83        if (ret) {
  84                printf("FEC MXS: Unable to init FEC0\n");
  85                return ret;
  86        }
  87
  88        ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
  89        if (ret) {
  90                printf("FEC MXS: Unable to init FEC1\n");
  91                return ret;
  92        }
  93
  94        return ret;
  95}
  96
  97#endif
  98