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13#define pr_fmt(fmt) "tegra-pcie: " fmt
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <fdtdec.h>
19#include <malloc.h>
20#include <pci.h>
21
22#include <asm/io.h>
23#include <asm/gpio.h>
24
25#include <asm/arch/clock.h>
26#include <asm/arch/powergate.h>
27#include <asm/arch-tegra/xusb-padctl.h>
28
29#include <linux/list.h>
30
31#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#define AFI_AXI_BAR0_SZ 0x00
36#define AFI_AXI_BAR1_SZ 0x04
37#define AFI_AXI_BAR2_SZ 0x08
38#define AFI_AXI_BAR3_SZ 0x0c
39#define AFI_AXI_BAR4_SZ 0x10
40#define AFI_AXI_BAR5_SZ 0x14
41
42#define AFI_AXI_BAR0_START 0x18
43#define AFI_AXI_BAR1_START 0x1c
44#define AFI_AXI_BAR2_START 0x20
45#define AFI_AXI_BAR3_START 0x24
46#define AFI_AXI_BAR4_START 0x28
47#define AFI_AXI_BAR5_START 0x2c
48
49#define AFI_FPCI_BAR0 0x30
50#define AFI_FPCI_BAR1 0x34
51#define AFI_FPCI_BAR2 0x38
52#define AFI_FPCI_BAR3 0x3c
53#define AFI_FPCI_BAR4 0x40
54#define AFI_FPCI_BAR5 0x44
55
56#define AFI_CACHE_BAR0_SZ 0x48
57#define AFI_CACHE_BAR0_ST 0x4c
58#define AFI_CACHE_BAR1_SZ 0x50
59#define AFI_CACHE_BAR1_ST 0x54
60
61#define AFI_MSI_BAR_SZ 0x60
62#define AFI_MSI_FPCI_BAR_ST 0x64
63#define AFI_MSI_AXI_BAR_ST 0x68
64
65#define AFI_CONFIGURATION 0xac
66#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
67
68#define AFI_FPCI_ERROR_MASKS 0xb0
69
70#define AFI_INTR_MASK 0xb4
71#define AFI_INTR_MASK_INT_MASK (1 << 0)
72#define AFI_INTR_MASK_MSI_MASK (1 << 8)
73
74#define AFI_SM_INTR_ENABLE 0xc4
75#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
76#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
77#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
78#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
79#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
80#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
81#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
82#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
83
84#define AFI_AFI_INTR_ENABLE 0xc8
85#define AFI_INTR_EN_INI_SLVERR (1 << 0)
86#define AFI_INTR_EN_INI_DECERR (1 << 1)
87#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
88#define AFI_INTR_EN_TGT_DECERR (1 << 3)
89#define AFI_INTR_EN_TGT_WRERR (1 << 4)
90#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
91#define AFI_INTR_EN_AXI_DECERR (1 << 6)
92#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
93#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
94
95#define AFI_PCIE_CONFIG 0x0f8
96#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
97#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
98#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
99#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
100#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
101#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
102#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
103#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
104#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
105#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
106
107#define AFI_FUSE 0x104
108#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
109
110#define AFI_PEX0_CTRL 0x110
111#define AFI_PEX1_CTRL 0x118
112#define AFI_PEX2_CTRL 0x128
113#define AFI_PEX_CTRL_RST (1 << 0)
114#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
115#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
116#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
117
118#define AFI_PLLE_CONTROL 0x160
119#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
120#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
121
122#define AFI_PEXBIAS_CTRL_0 0x168
123
124#define PADS_CTL_SEL 0x0000009C
125
126#define PADS_CTL 0x000000A0
127#define PADS_CTL_IDDQ_1L (1 << 0)
128#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
129#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
130
131#define PADS_PLL_CTL_TEGRA20 0x000000B8
132#define PADS_PLL_CTL_TEGRA30 0x000000B4
133#define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
134#define PADS_PLL_CTL_LOCKDET (0x1 << 8)
135#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
136#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
137#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
138#define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
139#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
140#define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
141#define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
142#define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
143
144#define PADS_REFCLK_CFG0 0x000000C8
145#define PADS_REFCLK_CFG1 0x000000CC
146
147
148
149
150
151
152#define PADS_REFCLK_CFG_TERM_SHIFT 2
153#define PADS_REFCLK_CFG_E_TERM_SHIFT 7
154#define PADS_REFCLK_CFG_PREDI_SHIFT 8
155#define PADS_REFCLK_CFG_DRVI_SHIFT 12
156
157#define RP_VEND_XP 0x00000F00
158#define RP_VEND_XP_DL_UP (1 << 30)
159
160#define RP_VEND_CTL2 0x00000FA8
161#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
162
163#define RP_PRIV_MISC 0x00000FE0
164#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
165#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
166
167#define RP_LINK_CONTROL_STATUS 0x00000090
168#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
169#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
170
171enum tegra_pci_id {
172 TEGRA20_PCIE,
173 TEGRA30_PCIE,
174 TEGRA124_PCIE,
175 TEGRA210_PCIE,
176};
177
178struct tegra_pcie_port {
179 struct tegra_pcie *pcie;
180
181 struct fdt_resource regs;
182 unsigned int num_lanes;
183 unsigned int index;
184
185 struct list_head list;
186};
187
188struct tegra_pcie_soc {
189 unsigned int num_ports;
190 unsigned long pads_pll_ctl;
191 unsigned long tx_ref_sel;
192 u32 pads_refclk_cfg0;
193 u32 pads_refclk_cfg1;
194 bool has_pex_clkreq_en;
195 bool has_pex_bias_ctrl;
196 bool has_cml_clk;
197 bool has_gen2;
198 bool force_pca_enable;
199};
200
201struct tegra_pcie {
202 struct pci_controller hose;
203
204 struct fdt_resource pads;
205 struct fdt_resource afi;
206 struct fdt_resource cs;
207
208 struct list_head ports;
209 unsigned long xbar;
210
211 const struct tegra_pcie_soc *soc;
212 struct tegra_xusb_phy *phy;
213};
214
215static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
216 unsigned long offset)
217{
218 writel(value, pcie->afi.start + offset);
219}
220
221static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
222{
223 return readl(pcie->afi.start + offset);
224}
225
226static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
227 unsigned long offset)
228{
229 writel(value, pcie->pads.start + offset);
230}
231
232static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
233{
234 return readl(pcie->pads.start + offset);
235}
236
237static unsigned long rp_readl(struct tegra_pcie_port *port,
238 unsigned long offset)
239{
240 return readl(port->regs.start + offset);
241}
242
243static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
244 unsigned long offset)
245{
246 writel(value, port->regs.start + offset);
247}
248
249static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
250{
251 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
252 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
253 (where & 0xfc);
254}
255
256static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
257 int where, unsigned long *address)
258{
259 unsigned int bus = PCI_BUS(bdf);
260
261 if (bus == 0) {
262 unsigned int dev = PCI_DEV(bdf);
263 struct tegra_pcie_port *port;
264
265 list_for_each_entry(port, &pcie->ports, list) {
266 if (port->index + 1 == dev) {
267 *address = port->regs.start + (where & ~3);
268 return 0;
269 }
270 }
271 return -EFAULT;
272 } else {
273#ifdef CONFIG_TEGRA20
274 unsigned int dev = PCI_DEV(bdf);
275 if (dev != 0)
276 return -EFAULT;
277#endif
278
279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
280 return 0;
281 }
282}
283
284static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
285 uint offset, ulong *valuep,
286 enum pci_size_t size)
287{
288 struct tegra_pcie *pcie = dev_get_priv(bus);
289 unsigned long address, value;
290 int err;
291
292 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
293 if (err < 0) {
294 value = 0xffffffff;
295 goto done;
296 }
297
298 value = readl(address);
299
300#ifdef CONFIG_TEGRA20
301
302 if (PCI_BUS(bdf) == 0) {
303 if ((offset & ~3) == PCI_CLASS_REVISION) {
304 value &= ~0x00ff0000;
305 value |= PCI_CLASS_BRIDGE_PCI << 16;
306 }
307 }
308#endif
309
310done:
311 *valuep = pci_conv_32_to_size(value, offset, size);
312
313 return 0;
314}
315
316static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
317 uint offset, ulong value,
318 enum pci_size_t size)
319{
320 struct tegra_pcie *pcie = dev_get_priv(bus);
321 unsigned long address;
322 ulong old;
323 int err;
324
325 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
326 if (err < 0)
327 return 0;
328
329 old = readl(address);
330 value = pci_conv_size_to_32(old, value, offset, size);
331 writel(value, address);
332
333 return 0;
334}
335
336static int tegra_pcie_port_parse_dt(const void *fdt, int node,
337 struct tegra_pcie_port *port)
338{
339 const u32 *addr;
340 int len;
341
342 addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
343 if (!addr) {
344 error("property \"assigned-addresses\" not found");
345 return -FDT_ERR_NOTFOUND;
346 }
347
348 port->regs.start = fdt32_to_cpu(addr[2]);
349 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
350
351 return 0;
352}
353
354static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
355 enum tegra_pci_id id, unsigned long *xbar)
356{
357 switch (id) {
358 case TEGRA20_PCIE:
359 switch (lanes) {
360 case 0x00000004:
361 debug("single-mode configuration\n");
362 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
363 return 0;
364
365 case 0x00000202:
366 debug("dual-mode configuration\n");
367 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
368 return 0;
369 }
370 break;
371 case TEGRA30_PCIE:
372 switch (lanes) {
373 case 0x00000204:
374 debug("4x1, 2x1 configuration\n");
375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
376 return 0;
377
378 case 0x00020202:
379 debug("2x3 configuration\n");
380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
381 return 0;
382
383 case 0x00010104:
384 debug("4x1, 1x2 configuration\n");
385 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
386 return 0;
387 }
388 break;
389 case TEGRA124_PCIE:
390 case TEGRA210_PCIE:
391 switch (lanes) {
392 case 0x0000104:
393 debug("4x1, 1x1 configuration\n");
394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
395 return 0;
396
397 case 0x0000102:
398 debug("2x1, 1x1 configuration\n");
399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
400 return 0;
401 }
402 break;
403 default:
404 break;
405 }
406
407 return -FDT_ERR_NOTFOUND;
408}
409
410static int tegra_pcie_parse_port_info(const void *fdt, int node,
411 unsigned int *index,
412 unsigned int *lanes)
413{
414 struct fdt_pci_addr addr;
415 int err;
416
417 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
418 if (err < 0) {
419 error("failed to parse \"nvidia,num-lanes\" property");
420 return err;
421 }
422
423 *lanes = err;
424
425 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
426 if (err < 0) {
427 error("failed to parse \"reg\" property");
428 return err;
429 }
430
431 *index = PCI_DEV(addr.phys_hi) - 1;
432
433 return 0;
434}
435
436int __weak tegra_pcie_board_init(void)
437{
438 return 0;
439}
440
441static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
442 struct tegra_pcie *pcie)
443{
444 int err, subnode;
445 u32 lanes = 0;
446
447 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
448 &pcie->pads);
449 if (err < 0) {
450 error("resource \"pads\" not found");
451 return err;
452 }
453
454 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
455 &pcie->afi);
456 if (err < 0) {
457 error("resource \"afi\" not found");
458 return err;
459 }
460
461 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
462 &pcie->cs);
463 if (err < 0) {
464 error("resource \"cs\" not found");
465 return err;
466 }
467
468 err = tegra_pcie_board_init();
469 if (err < 0) {
470 error("tegra_pcie_board_init() failed: err=%d", err);
471 return err;
472 }
473
474 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
475 if (pcie->phy) {
476 err = tegra_xusb_phy_prepare(pcie->phy);
477 if (err < 0) {
478 error("failed to prepare PHY: %d", err);
479 return err;
480 }
481 }
482
483 fdt_for_each_subnode(fdt, subnode, node) {
484 unsigned int index = 0, num_lanes = 0;
485 struct tegra_pcie_port *port;
486
487 err = tegra_pcie_parse_port_info(fdt, subnode, &index,
488 &num_lanes);
489 if (err < 0) {
490 error("failed to obtain root port info");
491 continue;
492 }
493
494 lanes |= num_lanes << (index << 3);
495
496 if (!fdtdec_get_is_enabled(fdt, subnode))
497 continue;
498
499 port = malloc(sizeof(*port));
500 if (!port)
501 continue;
502
503 memset(port, 0, sizeof(*port));
504 port->num_lanes = num_lanes;
505 port->index = index;
506
507 err = tegra_pcie_port_parse_dt(fdt, subnode, port);
508 if (err < 0) {
509 free(port);
510 continue;
511 }
512
513 list_add_tail(&port->list, &pcie->ports);
514 port->pcie = pcie;
515 }
516
517 err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
518 if (err < 0) {
519 error("invalid lane configuration");
520 return err;
521 }
522
523 return 0;
524}
525
526static int tegra_pcie_power_on(struct tegra_pcie *pcie)
527{
528 const struct tegra_pcie_soc *soc = pcie->soc;
529 unsigned long value;
530 int err;
531
532
533 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
534 reset_set_enable(PERIPH_ID_AFI, 1);
535 reset_set_enable(PERIPH_ID_PCIE, 1);
536
537 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
538 if (err < 0) {
539 error("failed to power off PCIe partition: %d", err);
540 return err;
541 }
542
543 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
544 PERIPH_ID_PCIE);
545 if (err < 0) {
546 error("failed to power up PCIe partition: %d", err);
547 return err;
548 }
549
550
551 reset_set_enable(PERIPH_ID_AFI, 0);
552
553
554 clock_enable(PERIPH_ID_AFI);
555
556 if (soc->has_cml_clk) {
557
558 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
559 value |= (1 << 0);
560 value &= ~(1 << 1);
561 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
562 }
563
564 err = tegra_plle_enable();
565 if (err < 0) {
566 error("failed to enable PLLE: %d\n", err);
567 return err;
568 }
569
570 return 0;
571}
572
573static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
574{
575 const struct tegra_pcie_soc *soc = pcie->soc;
576 unsigned long start = get_timer(0);
577 u32 value;
578
579 while (get_timer(start) < timeout) {
580 value = pads_readl(pcie, soc->pads_pll_ctl);
581 if (value & PADS_PLL_CTL_LOCKDET)
582 return 0;
583 }
584
585 return -ETIMEDOUT;
586}
587
588static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
589{
590 const struct tegra_pcie_soc *soc = pcie->soc;
591 u32 value;
592 int err;
593
594
595 pads_writel(pcie, 0, PADS_CTL_SEL);
596
597
598 value = pads_readl(pcie, PADS_CTL);
599 value |= PADS_CTL_IDDQ_1L;
600 pads_writel(pcie, value, PADS_CTL);
601
602
603
604
605
606 value = pads_readl(pcie, soc->pads_pll_ctl);
607 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
608 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
609 pads_writel(pcie, value, soc->pads_pll_ctl);
610
611
612 value = pads_readl(pcie, soc->pads_pll_ctl);
613 value &= ~PADS_PLL_CTL_RST_B4SM;
614 pads_writel(pcie, value, soc->pads_pll_ctl);
615
616 udelay(20);
617
618
619 value = pads_readl(pcie, soc->pads_pll_ctl);
620 value |= PADS_PLL_CTL_RST_B4SM;
621 pads_writel(pcie, value, soc->pads_pll_ctl);
622
623
624 err = tegra_pcie_pll_wait(pcie, 500);
625 if (err < 0) {
626 error("PLL failed to lock: %d", err);
627 return err;
628 }
629
630
631 value = pads_readl(pcie, PADS_CTL);
632 value &= ~PADS_CTL_IDDQ_1L;
633 pads_writel(pcie, value, PADS_CTL);
634
635
636 value = pads_readl(pcie, PADS_CTL);
637 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
638 pads_writel(pcie, value, PADS_CTL);
639
640 return 0;
641}
642
643static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
644{
645 const struct tegra_pcie_soc *soc = pcie->soc;
646 struct tegra_pcie_port *port;
647 u32 value;
648 int err;
649
650 if (pcie->phy) {
651 value = afi_readl(pcie, AFI_PLLE_CONTROL);
652 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
653 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
654 afi_writel(pcie, value, AFI_PLLE_CONTROL);
655 }
656
657 if (soc->has_pex_bias_ctrl)
658 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
659
660 value = afi_readl(pcie, AFI_PCIE_CONFIG);
661 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
662 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
663
664 list_for_each_entry(port, &pcie->ports, list)
665 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
666
667 afi_writel(pcie, value, AFI_PCIE_CONFIG);
668
669 value = afi_readl(pcie, AFI_FUSE);
670
671 if (soc->has_gen2)
672 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
673 else
674 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
675
676 afi_writel(pcie, value, AFI_FUSE);
677
678 if (pcie->phy)
679 err = tegra_xusb_phy_enable(pcie->phy);
680 else
681 err = tegra_pcie_phy_enable(pcie);
682
683 if (err < 0) {
684 error("failed to power on PHY: %d\n", err);
685 return err;
686 }
687
688
689 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
690
691
692 value = afi_readl(pcie, AFI_CONFIGURATION);
693 value |= AFI_CONFIGURATION_EN_FPCI;
694 afi_writel(pcie, value, AFI_CONFIGURATION);
695
696
697 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
698 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
699 afi_writel(pcie, 0, AFI_INTR_MASK);
700 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
701
702 return 0;
703}
704
705static int tegra_pcie_setup_translations(struct udevice *bus)
706{
707 struct tegra_pcie *pcie = dev_get_priv(bus);
708 unsigned long fpci, axi, size;
709 struct pci_region *io, *mem, *pref;
710 int count;
711
712
713 fpci = 0xfe100000;
714 size = fdt_resource_size(&pcie->cs);
715 axi = pcie->cs.start;
716
717 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
718 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
719 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
720
721 count = pci_get_regions(bus, &io, &mem, &pref);
722 if (count != 3)
723 return -EINVAL;
724
725
726 fpci = 0xfdfc0000;
727 size = io->size;
728 axi = io->phys_start;
729
730 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
731 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
732 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
733
734
735 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
736 size = pref->size;
737 axi = pref->phys_start;
738
739 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
740 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
741 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
742
743
744 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
745 size = mem->size;
746 axi = mem->phys_start;
747
748 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
749 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
750 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
751
752
753 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
754 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
755 afi_writel(pcie, 0, AFI_FPCI_BAR4);
756
757 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
758 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
759 afi_writel(pcie, 0, AFI_FPCI_BAR5);
760
761
762 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
763 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
764 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
765 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
766
767
768 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
769 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
770 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
771 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
772
773 return 0;
774}
775
776static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
777{
778 unsigned long ret = 0;
779
780 switch (port->index) {
781 case 0:
782 ret = AFI_PEX0_CTRL;
783 break;
784
785 case 1:
786 ret = AFI_PEX1_CTRL;
787 break;
788
789 case 2:
790 ret = AFI_PEX2_CTRL;
791 break;
792 }
793
794 return ret;
795}
796
797static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
798{
799 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
800 unsigned long value;
801
802
803 value = afi_readl(port->pcie, ctrl);
804 value &= ~AFI_PEX_CTRL_RST;
805 afi_writel(port->pcie, value, ctrl);
806
807 udelay(2000);
808
809 value = afi_readl(port->pcie, ctrl);
810 value |= AFI_PEX_CTRL_RST;
811 afi_writel(port->pcie, value, ctrl);
812}
813
814static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
815{
816 struct tegra_pcie *pcie = port->pcie;
817 const struct tegra_pcie_soc *soc = pcie->soc;
818 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
819 unsigned long value;
820
821
822 value = afi_readl(pcie, ctrl);
823 value |= AFI_PEX_CTRL_REFCLK_EN;
824
825 if (pcie->soc->has_pex_clkreq_en)
826 value |= AFI_PEX_CTRL_CLKREQ_EN;
827
828 value |= AFI_PEX_CTRL_OVERRIDE_EN;
829
830 afi_writel(pcie, value, ctrl);
831
832 tegra_pcie_port_reset(port);
833
834 if (soc->force_pca_enable) {
835 value = rp_readl(port, RP_VEND_CTL2);
836 value |= RP_VEND_CTL2_PCA_ENABLE;
837 rp_writel(port, value, RP_VEND_CTL2);
838 }
839
840
841 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
842 if (soc->num_ports > 2)
843 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
844}
845
846static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
847{
848 unsigned int retries = 3;
849 unsigned long value;
850
851 value = rp_readl(port, RP_PRIV_MISC);
852 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
853 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
854 rp_writel(port, value, RP_PRIV_MISC);
855
856 do {
857 unsigned int timeout = 200;
858
859 do {
860 value = rp_readl(port, RP_VEND_XP);
861 if (value & RP_VEND_XP_DL_UP)
862 break;
863
864 udelay(2000);
865 } while (--timeout);
866
867 if (!timeout) {
868 debug("link %u down, retrying\n", port->index);
869 goto retry;
870 }
871
872 timeout = 200;
873
874 do {
875 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
876 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
877 return true;
878
879 udelay(2000);
880 } while (--timeout);
881
882retry:
883 tegra_pcie_port_reset(port);
884 } while (--retries);
885
886 return false;
887}
888
889static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
890{
891 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
892 unsigned long value;
893
894
895 value = afi_readl(port->pcie, ctrl);
896 value &= ~AFI_PEX_CTRL_RST;
897 afi_writel(port->pcie, value, ctrl);
898
899
900 value = afi_readl(port->pcie, ctrl);
901 value &= ~AFI_PEX_CTRL_REFCLK_EN;
902 afi_writel(port->pcie, value, ctrl);
903}
904
905static void tegra_pcie_port_free(struct tegra_pcie_port *port)
906{
907 list_del(&port->list);
908 free(port);
909}
910
911static int tegra_pcie_enable(struct tegra_pcie *pcie)
912{
913 struct tegra_pcie_port *port, *tmp;
914
915 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
916 debug("probing port %u, using %u lanes\n", port->index,
917 port->num_lanes);
918
919 tegra_pcie_port_enable(port);
920
921 if (tegra_pcie_port_check_link(port))
922 continue;
923
924 debug("link %u down, ignoring\n", port->index);
925
926 tegra_pcie_port_disable(port);
927 tegra_pcie_port_free(port);
928 }
929
930 return 0;
931}
932
933static const struct tegra_pcie_soc pci_tegra_soc[] = {
934 [TEGRA20_PCIE] = {
935 .num_ports = 2,
936 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
937 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
938 .pads_refclk_cfg0 = 0xfa5cfa5c,
939 .has_pex_clkreq_en = false,
940 .has_pex_bias_ctrl = false,
941 .has_cml_clk = false,
942 .has_gen2 = false,
943 },
944 [TEGRA30_PCIE] = {
945 .num_ports = 3,
946 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
947 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
948 .pads_refclk_cfg0 = 0xfa5cfa5c,
949 .pads_refclk_cfg1 = 0xfa5cfa5c,
950 .has_pex_clkreq_en = true,
951 .has_pex_bias_ctrl = true,
952 .has_cml_clk = true,
953 .has_gen2 = false,
954 },
955 [TEGRA124_PCIE] = {
956 .num_ports = 2,
957 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
958 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
959 .pads_refclk_cfg0 = 0x44ac44ac,
960 .has_pex_clkreq_en = true,
961 .has_pex_bias_ctrl = true,
962 .has_cml_clk = true,
963 .has_gen2 = true,
964 },
965 [TEGRA210_PCIE] = {
966 .num_ports = 2,
967 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
968 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
969 .pads_refclk_cfg0 = 0x90b890b8,
970 .has_pex_clkreq_en = true,
971 .has_pex_bias_ctrl = true,
972 .has_cml_clk = true,
973 .has_gen2 = true,
974 .force_pca_enable = true,
975 }
976};
977
978static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
979{
980 struct tegra_pcie *pcie = dev_get_priv(dev);
981 enum tegra_pci_id id;
982
983 id = dev_get_driver_data(dev);
984 pcie->soc = &pci_tegra_soc[id];
985
986 INIT_LIST_HEAD(&pcie->ports);
987
988 if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
989 return -EINVAL;
990
991 return 0;
992}
993
994static int pci_tegra_probe(struct udevice *dev)
995{
996 struct tegra_pcie *pcie = dev_get_priv(dev);
997 int err;
998
999 err = tegra_pcie_power_on(pcie);
1000 if (err < 0) {
1001 error("failed to power on");
1002 return err;
1003 }
1004
1005 err = tegra_pcie_enable_controller(pcie);
1006 if (err < 0) {
1007 error("failed to enable controller");
1008 return err;
1009 }
1010
1011 err = tegra_pcie_setup_translations(dev);
1012 if (err < 0) {
1013 error("failed to decode ranges");
1014 return err;
1015 }
1016
1017 err = tegra_pcie_enable(pcie);
1018 if (err < 0) {
1019 error("failed to enable PCIe");
1020 return err;
1021 }
1022
1023 return 0;
1024}
1025
1026static const struct dm_pci_ops pci_tegra_ops = {
1027 .read_config = pci_tegra_read_config,
1028 .write_config = pci_tegra_write_config,
1029};
1030
1031static const struct udevice_id pci_tegra_ids[] = {
1032 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1033 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1034 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1035 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1036 { }
1037};
1038
1039U_BOOT_DRIVER(pci_tegra) = {
1040 .name = "pci_tegra",
1041 .id = UCLASS_PCI,
1042 .of_match = pci_tegra_ids,
1043 .ops = &pci_tegra_ops,
1044 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
1045 .probe = pci_tegra_probe,
1046 .priv_auto_alloc_size = sizeof(struct tegra_pcie),
1047};
1048
