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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define CONFIG_DISPLAY_BOARDINFO
17
18#ifdef CONFIG_36BIT
19#define CONFIG_PHYS_64BIT
20#endif
21
22
23#define CONFIG_BOOKE 1
24#define CONFIG_E500 1
25#define CONFIG_MPC8548 1
26#define CONFIG_MPC8548CDS 1
27
28#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xfff80000
30#endif
31
32#define CONFIG_SYS_SRIO
33#define CONFIG_SRIO1
34
35#define CONFIG_PCI
36#define CONFIG_PCI1
37#define CONFIG_PCIE1
38#undef CONFIG_PCI2
39#define CONFIG_FSL_PCI_INIT 1
40#define CONFIG_PCI_INDIRECT_BRIDGE 1
41#define CONFIG_FSL_PCIE_RESET 1
42#define CONFIG_SYS_PCI_64BIT 1
43
44#define CONFIG_TSEC_ENET
45#define CONFIG_ENV_OVERWRITE
46#define CONFIG_INTERRUPTS
47#define CONFIG_FSL_LAW 1
48
49#define CONFIG_FSL_VIA
50
51#ifndef __ASSEMBLY__
52extern unsigned long get_clock_freq(void);
53#endif
54#define CONFIG_SYS_CLK_FREQ get_clock_freq()
55
56
57
58
59#define CONFIG_L2_CACHE
60#define CONFIG_BTB
61
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63
64
65#define CONFIG_ENABLE_36BIT_PHYS 1
66
67#ifdef CONFIG_PHYS_64BIT
68#define CONFIG_ADDR_MAP
69#define CONFIG_SYS_NUM_ADDR_MAP 16
70#endif
71
72#define CONFIG_SYS_MEMTEST_START 0x00200000
73#define CONFIG_SYS_MEMTEST_END 0x00400000
74
75#define CONFIG_SYS_CCSRBAR 0xe0000000
76#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
77
78
79#define CONFIG_SYS_FSL_DDR2
80#undef CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SPD_EEPROM
82#define CONFIG_DDR_SPD
83
84#define CONFIG_DDR_ECC
85#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
86#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
87
88#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
90
91#define CONFIG_NUM_DDR_CONTROLLERS 1
92#define CONFIG_DIMM_SLOTS_PER_CTLR 1
93#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
94
95
96#define SPD_EEPROM_ADDRESS 0x51
97
98
99#ifndef CONFIG_SPD_EEPROM
100#error ("CONFIG_SPD_EEPROM is required")
101#endif
102
103#undef CONFIG_CLOCKS_IN_MHZ
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168
169#define CONFIG_SYS_FLASH_BASE 0xff000000
170#ifdef CONFIG_PHYS_64BIT
171#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
172#else
173#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
174#endif
175
176#define CONFIG_SYS_BR0_PRELIM \
177 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
178#define CONFIG_SYS_BR1_PRELIM \
179 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
180
181#define CONFIG_SYS_OR0_PRELIM 0xff806e65
182#define CONFIG_SYS_OR1_PRELIM 0xff806e65
183
184#define CONFIG_SYS_FLASH_BANKS_LIST \
185 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
186#define CONFIG_SYS_MAX_FLASH_BANKS 2
187#define CONFIG_SYS_MAX_FLASH_SECT 128
188#undef CONFIG_SYS_FLASH_CHECKSUM
189#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
190#define CONFIG_SYS_FLASH_WRITE_TOUT 500
191
192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
193
194#define CONFIG_FLASH_CFI_DRIVER
195#define CONFIG_SYS_FLASH_CFI
196#define CONFIG_SYS_FLASH_EMPTY_INFO
197
198#define CONFIG_HWCONFIG
199
200
201
202
203#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
204#ifdef CONFIG_PHYS_64BIT
205#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
206#else
207#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
208#endif
209#define CONFIG_SYS_LBC_SDRAM_SIZE 64
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229#define CONFIG_SYS_BR2_PRELIM \
230 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
231 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
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246
247#define CONFIG_SYS_OR2_PRELIM 0xfc006901
248
249#define CONFIG_SYS_LBC_LCRR 0x00030004
250#define CONFIG_SYS_LBC_LBCR 0x00000000
251#define CONFIG_SYS_LBC_LSRT 0x20000000
252#define CONFIG_SYS_LBC_MRTPR 0x00000000
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259
260#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
261 | LSDMR_PRETOACT7 \
262 | LSDMR_ACTTORW7 \
263 | LSDMR_BL8 \
264 | LSDMR_WRC4 \
265 | LSDMR_CL3 \
266 | LSDMR_RFEN \
267 )
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299#define CONFIG_FSL_CADMUS
300
301#define CADMUS_BASE_ADDR 0xf8000000
302#ifdef CONFIG_PHYS_64BIT
303#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
304#else
305#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
306#endif
307#define CONFIG_SYS_BR3_PRELIM \
308 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
309#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
310
311#define CONFIG_SYS_INIT_RAM_LOCK 1
312#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
313#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
314
315#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
316#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
317
318#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
319#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
320
321
322#define CONFIG_CONS_INDEX 2
323#define CONFIG_SYS_NS16550_SERIAL
324#define CONFIG_SYS_NS16550_REG_SIZE 1
325#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
326
327#define CONFIG_SYS_BAUDRATE_TABLE \
328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
329
330#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
331#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
332
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335
336#define CONFIG_SYS_I2C
337#define CONFIG_SYS_I2C_FSL
338#define CONFIG_SYS_FSL_I2C_SPEED 400000
339#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
340#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
341#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
342
343
344#define CONFIG_ID_EEPROM
345#define CONFIG_SYS_I2C_EEPROM_CCID
346#define CONFIG_SYS_ID_EEPROM
347#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
348#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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353
354#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
355#ifdef CONFIG_PHYS_64BIT
356#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
357#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
358#else
359#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
360#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
361#endif
362#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
363#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
364#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
365#ifdef CONFIG_PHYS_64BIT
366#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
367#else
368#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
369#endif
370#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
371
372#ifdef CONFIG_PCIE1
373#define CONFIG_SYS_PCIE1_NAME "Slot"
374#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
375#ifdef CONFIG_PHYS_64BIT
376#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
377#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
378#else
379#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
380#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
381#endif
382#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
383#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
384#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
385#ifdef CONFIG_PHYS_64BIT
386#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
387#else
388#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
389#endif
390#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
391#endif
392
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395
396#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
397#ifdef CONFIG_PHYS_64BIT
398#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
399#else
400#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
401#endif
402#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
403
404#ifdef CONFIG_LEGACY
405#define BRIDGE_ID 17
406#define VIA_ID 2
407#else
408#define BRIDGE_ID 28
409#define VIA_ID 4
410#endif
411
412#if defined(CONFIG_PCI)
413
414#define CONFIG_PCI_PNP
415
416#undef CONFIG_EEPRO100
417#undef CONFIG_TULIP
418
419#define CONFIG_PCI_SCAN_SHOW
420
421#endif
422
423#if defined(CONFIG_TSEC_ENET)
424
425#define CONFIG_MII 1
426#define CONFIG_TSEC1 1
427#define CONFIG_TSEC1_NAME "eTSEC0"
428#define CONFIG_TSEC2 1
429#define CONFIG_TSEC2_NAME "eTSEC1"
430#define CONFIG_TSEC3 1
431#define CONFIG_TSEC3_NAME "eTSEC2"
432#define CONFIG_TSEC4
433#define CONFIG_TSEC4_NAME "eTSEC3"
434#undef CONFIG_MPC85XX_FEC
435
436#define CONFIG_PHY_MARVELL
437
438#define TSEC1_PHY_ADDR 0
439#define TSEC2_PHY_ADDR 1
440#define TSEC3_PHY_ADDR 2
441#define TSEC4_PHY_ADDR 3
442
443#define TSEC1_PHYIDX 0
444#define TSEC2_PHYIDX 0
445#define TSEC3_PHYIDX 0
446#define TSEC4_PHYIDX 0
447#define TSEC1_FLAGS TSEC_GIGABIT
448#define TSEC2_FLAGS TSEC_GIGABIT
449#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
450#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
451
452
453#define CONFIG_ETHPRIME "eTSEC0"
454#define CONFIG_PHY_GIGE 1
455#endif
456
457
458
459
460#define CONFIG_ENV_IS_IN_FLASH 1
461#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
462#define CONFIG_ENV_ADDR 0xfff80000
463#else
464#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
465#endif
466#define CONFIG_ENV_SECT_SIZE 0x20000
467#define CONFIG_ENV_SIZE 0x2000
468
469#define CONFIG_LOADS_ECHO 1
470#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
471
472
473
474
475#define CONFIG_BOOTP_BOOTFILESIZE
476#define CONFIG_BOOTP_BOOTPATH
477#define CONFIG_BOOTP_GATEWAY
478#define CONFIG_BOOTP_HOSTNAME
479
480
481
482
483#define CONFIG_CMD_IRQ
484#define CONFIG_CMD_REGINFO
485
486#if defined(CONFIG_PCI)
487 #define CONFIG_CMD_PCI
488#endif
489
490#undef CONFIG_WATCHDOG
491
492
493
494
495#define CONFIG_SYS_LONGHELP
496#define CONFIG_CMDLINE_EDITING
497#define CONFIG_AUTO_COMPLETE
498#define CONFIG_SYS_LOAD_ADDR 0x2000000
499#if defined(CONFIG_CMD_KGDB)
500#define CONFIG_SYS_CBSIZE 1024
501#else
502#define CONFIG_SYS_CBSIZE 256
503#endif
504#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
505#define CONFIG_SYS_MAXARGS 16
506#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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513#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
514#define CONFIG_SYS_BOOTM_LEN (64 << 20)
515
516#if defined(CONFIG_CMD_KGDB)
517#define CONFIG_KGDB_BAUDRATE 230400
518#endif
519
520
521
522
523#if defined(CONFIG_TSEC_ENET)
524#define CONFIG_HAS_ETH0
525#define CONFIG_HAS_ETH1
526#define CONFIG_HAS_ETH2
527#define CONFIG_HAS_ETH3
528#endif
529
530#define CONFIG_IPADDR 192.168.1.253
531
532#define CONFIG_HOSTNAME unknown
533#define CONFIG_ROOTPATH "/nfsroot"
534#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
535#define CONFIG_UBOOTPATH 8548cds/u-boot.bin
536
537#define CONFIG_SERVERIP 192.168.1.1
538#define CONFIG_GATEWAYIP 192.168.1.1
539#define CONFIG_NETMASK 255.255.255.0
540
541#define CONFIG_LOADADDR 1000000
542
543#undef CONFIG_BOOTARGS
544
545#define CONFIG_BAUDRATE 115200
546
547#define CONFIG_EXTRA_ENV_SETTINGS \
548 "hwconfig=fsl_ddr:ecc=off\0" \
549 "netdev=eth0\0" \
550 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
551 "tftpflash=tftpboot $loadaddr $uboot; " \
552 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
553 " +$filesize; " \
554 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
555 " +$filesize; " \
556 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
557 " $filesize; " \
558 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
559 " +$filesize; " \
560 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
561 " $filesize\0" \
562 "consoledev=ttyS1\0" \
563 "ramdiskaddr=2000000\0" \
564 "ramdiskfile=ramdisk.uboot\0" \
565 "fdtaddr=c00000\0" \
566 "fdtfile=mpc8548cds.dtb\0"
567
568#define CONFIG_NFSBOOTCOMMAND \
569 "setenv bootargs root=/dev/nfs rw " \
570 "nfsroot=$serverip:$rootpath " \
571 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
572 "console=$consoledev,$baudrate $othbootargs;" \
573 "tftp $loadaddr $bootfile;" \
574 "tftp $fdtaddr $fdtfile;" \
575 "bootm $loadaddr - $fdtaddr"
576
577#define CONFIG_RAMBOOTCOMMAND \
578 "setenv bootargs root=/dev/ram rw " \
579 "console=$consoledev,$baudrate $othbootargs;" \
580 "tftp $ramdiskaddr $ramdiskfile;" \
581 "tftp $loadaddr $bootfile;" \
582 "tftp $fdtaddr $fdtfile;" \
583 "bootm $loadaddr $ramdiskaddr $fdtaddr"
584
585#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
586
587#endif
588