1/* U-Boot for BlackVME. (C) Wojtek Skulski 2010. 2 * The board includes ADSP-BF561 rev. 0.5, 3 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), 4 * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), 5 * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB), 6 * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB), 7 * Spartan6-LX150 (memory-mapped; both PPIs also connected). 8 * See http://www.skutek.com 9 */ 10 11#ifndef __CONFIG_BLACKVME_H__ 12#define __CONFIG_BLACKVME_H__ 13 14#include <asm/config-pre.h> 15 16/* Debugging: Set these options if you're having problems 17 * #define CONFIG_DEBUG_EARLY_SERIAL 18 * #define DEBUG 19 * #define CONFIG_DEBUG_DUMP 20 * #define CONFIG_DEBUG_DUMP_SYMS 21 * CONFIG_PANIC_HANG means that the board will not auto-reboot 22 */ 23#define CONFIG_PANIC_HANG 0 24 25/* CPU Options */ 26#define CONFIG_BFIN_CPU bf561-0.5 27#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER 28 29/* 30 * CLOCK SETTINGS CAVEAT 31 * You CANNOT just change the clock settings, esp. the SCLK. 32 * The SDRAM timing, SPI baud, and the serial UART baud 33 * use SCLK frequency to set their own frequencies. Therefore, 34 * if you change the SCLK_DIV, you may also have to adjust 35 * SDRAM refresh and other timings. 36 * -------------------------------------------------------------- 37 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 38 * 25 * 8 / 1 = 200 MHz 39 * 25 * 16 / 1 = 400 MHz 40 * 25 * 24 / 1 = 600 MHz 41 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 42 * 25 * 8 / 2 = 100 MHz 43 * 25 * 24 / 6 = 100 MHz 44 * 25 * 24 / 5 = 120 MHz 45 * 25 * 16 / 3 = 133 MHz 46 * 25 MHz because the oscillator also feeds the ether chip. 47 * CONFIG_CLKIN_HZ is 25 MHz written in Hz 48 * CLKIN_HALF controls the DF bit in PLL_CTL 49 * 0 = CLKIN 1 = CLKIN / 2 50 * PLL_BYPASS controls the BYPASS bit in PLL_CTL 51 * 0 = do not bypass 1 = bypass PLL 52 * VCO_MULT = MSEL (multiplier) in PLL_CTL 53 * Values can range from 0-63 (where 0 means 64) 54 * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY) 55 * SCLK_DIV = system clock divider, 1 to 15 56 */ 57#define CONFIG_CLKIN_HZ 25000000 58#define CONFIG_CLKIN_HALF 0 59#define CONFIG_PLL_BYPASS 0 60#define CONFIG_VCO_MULT 8 61#define CONFIG_CCLK_DIV 1 62#define CONFIG_SCLK_DIV 2 63 64/* 65 * Ether chip in async memory space AMS3, same as BF561-EZ-KIT. 66 * Used in 32-bit mode. 16-bit mode not supported. 67 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 68 */ 69/* 70 * Network settings using a dedicated 2nd ether card in PC 71 * Windows will automatically acquire IP of that card 72 * Then use the dedicated card IP + 1 for the board 73 * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network 74 */ 75#define CONFIG_DRIVER_AX88180 1 76#define AX88180_BASE 0x2c000000 77 78#define CONFIG_HOSTNAME blackvme /* Bfin board */ 79#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */ 80#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */ 81#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */ 82#define CONFIG_NETMASK 255.255.255.0 83#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/ 84#define CFG_AUTOLOAD "no" 85 86/* 87 * SDRAM settings & memory map 88 */ 89 90#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ 91#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ 92/* 93 * SDRAM reference page 94 * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 95 * NOTE: BlackVME populates only SDRAM bank 0 96 */ 97/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */ 98#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */ 99#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */ 100 101/* Async memory global settings. (ASRAM, not SDRAM) 102 * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1 103 * CLKOUT enabled, all async banks enabled, core has priority 104 * bank 0&1 16 bit (FPGA) 105 * bank 2&3 32 bit (ether and USB chips) 106 */ 107#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */ 108 109/* Async mem timing: BF561 HRM page 16-12 and 16-15. 110 * Default values 0xFFC2 FFC2 are the slowest supported. 111 * Example settings of CONFIG_EBIU_AMBCTL1_VAL 112 * 1. EZ-KIT settings: 0xFFC2 7BB0 113 * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx 114 * See the following page: 115 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 116 * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz: 117 * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz 118 * One extra clock needed because AX88180 is asynchronous to CPU. 119 */ 120 /* bank 1 0 */ 121#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 122 /* bank 3 2 */ 123#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 124 125/* memory layout */ 126 127#define CONFIG_SYS_MONITOR_LEN (256 << 10) 128#define CONFIG_SYS_MALLOC_LEN (384 << 10) 129 130/* 131 * Serial SPI Flash 132 * For the M25P64 SCK should be kept < 15 MHz 133 */ 134#define CONFIG_BFIN_SPI 135#define CONFIG_ENV_IS_IN_SPI_FLASH 136#define CONFIG_ENV_OFFSET 0x40000 137#define CONFIG_ENV_SIZE 0x2000 138#define CONFIG_ENV_SECT_SIZE 0x40000 139 140#define CONFIG_ENV_SPI_MAX_HZ 15000000 141#define CONFIG_SF_DEFAULT_SPEED 15000000 142 143/* 144 * Interactive command settings 145 */ 146 147#define CONFIG_SYS_LONGHELP 1 148#define CONFIG_CMDLINE_EDITING 1 149#define CONFIG_AUTO_COMPLETE 1 150 151#define CONFIG_CMD_BOOTLDR 152#define CONFIG_CMD_CPLBINFO 153 154/* 155 * Default: boot from SPI flash. 156 * "sfboot" is a composite command defined in extra settings 157 */ 158#define CONFIG_BOOTCOMMAND "run sfboot" 159 160/* 161 * Console settings 162 */ 163#define CONFIG_BAUDRATE 57600 164#define CONFIG_LOADS_ECHO 1 165#define CONFIG_UART_CONSOLE 0 166#define CONFIG_BFIN_SERIAL 167 168/* 169 * U-Boot environment variables. Use "printenv" to examine. 170 * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env 171 */ 172#define CONFIG_BOOTARGS \ 173 "root=/dev/mtdblock0 rw " \ 174 "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ 175 "earlyprintk=serial,uart0," \ 176 __stringify(CONFIG_BAUDRATE) " " \ 177 "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " " 178 179/* Convenience env variables & commands. 180 * Reserve kernstart = 0x20000 = 128 kB for U-Boot. 181 * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size). 182 * U-Boot image is saved at flash offset=0. 183 * Kernel image is saved at flash offset=$kernstart. 184 * Instructions. Ksave takes about a minute to complete. 185 * 1. Update U-Boot: run uget; run usave 186 * 2. Update kernel: run kget; run ksave 187 * After updating U-Boot also update the kernel per above instructions 188 * to make the saved environment consistent with the flash. 189 */ 190#define CONFIG_EXTRA_ENV_SETTINGS \ 191 "kernstart=0x20000\0" \ 192 "kernarea=0x500000\0" \ 193 "uget=tftp u-boot.ldr\0" \ 194 "kget=tftp uImage\0" \ 195 "usave=sf probe 2; " \ 196 "sf erase 0 $(kernstart); " \ 197 "sf write $(fileaddr) 0 $(filesize)\0" \ 198 "ksave=sf probe 2; " \ 199 "saveenv; " \ 200 "echo Now patiently wait for the prompt...; " \ 201 "sf erase $(kernstart) $(kernarea); " \ 202 "sf write $(fileaddr) $(kernstart) $(filesize)\0" \ 203 "sfboot=sf probe 2; " \ 204 "sf read $(loadaddr) $(kernstart) $(filesize); " \ 205 "run addip; bootm\0" \ 206 "addip=setenv bootargs $(bootargs) " \ 207 "ip=$(ipaddr):$(serverip):$(gatewayip):" \ 208 "$(netmask):$(hostname):eth0:off\0" 209 210/* 211 * Soft I2C settings (BF561 does not have hard I2C) 212 * PF12,13 on SPI connector 0. 213 */ 214#ifdef CONFIG_SYS_I2C_SOFT 215# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12 216# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13 217# define CONFIG_SYS_I2C_SPEED 50000 218# define CONFIG_SYS_I2C_SLAVE 0xFE 219#endif 220 221/* 222 * No Parallel Flash on this board 223 */ 224#define CONFIG_SYS_NO_FLASH 225#undef CONFIG_CMD_JFFS2 226 227#endif 228