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7#ifndef __FM_ETH_H__
8#define __FM_ETH_H__
9
10#include <common.h>
11#include <phy.h>
12#include <asm/types.h>
13
14enum fm_port {
15 FM1_DTSEC1,
16 FM1_DTSEC2,
17 FM1_DTSEC3,
18 FM1_DTSEC4,
19 FM1_DTSEC5,
20 FM1_DTSEC6,
21 FM1_DTSEC9,
22 FM1_DTSEC10,
23 FM1_10GEC1,
24 FM1_10GEC2,
25 FM1_10GEC3,
26 FM1_10GEC4,
27 FM2_DTSEC1,
28 FM2_DTSEC2,
29 FM2_DTSEC3,
30 FM2_DTSEC4,
31 FM2_DTSEC5,
32 FM2_DTSEC6,
33 FM2_DTSEC9,
34 FM2_DTSEC10,
35 FM2_10GEC1,
36 FM2_10GEC2,
37 NUM_FM_PORTS,
38};
39
40enum fm_eth_type {
41 FM_ETH_1G_E,
42 FM_ETH_10G_E,
43};
44
45#ifdef CONFIG_SYS_FMAN_V3
46#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
47#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
48#if (CONFIG_SYS_NUM_FMAN == 2)
49#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
50#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
51#endif
52#else
53#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
54#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
55#endif
56
57#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
58#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
59
60
61#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
62 .fm = idx, \
63 .phy_regs = (void *)pregs, \
64 .enet_if = PHY_INTERFACE_MODE_NONE, \
65
66#ifdef CONFIG_SYS_FMAN_V3
67#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
68{ \
69 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
70 .index = idx, \
71 .num = n - 1, \
72 .type = FM_ETH_1G_E, \
73 .port = FM##idx##_DTSEC##n, \
74 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
75 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
76 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
77 offsetof(struct ccsr_fman, memac[n-1]),\
78}
79
80#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
81#define FM_TGEC_INFO_INITIALIZER(idx, n) \
82{ \
83 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
84 .index = idx, \
85 .num = n - 1, \
86 .type = FM_ETH_10G_E, \
87 .port = FM##idx##_10GEC##n, \
88 .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
89 .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
90 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
91 offsetof(struct ccsr_fman, memac[n-1]),\
92}
93#else
94#if (CONFIG_SYS_NUM_FMAN == 2)
95#define FM_TGEC_INFO_INITIALIZER(idx, n) \
96{ \
97 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
98 .index = idx, \
99 .num = n - 1, \
100 .type = FM_ETH_10G_E, \
101 .port = FM##idx##_10GEC##n, \
102 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
103 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
104 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
105 offsetof(struct ccsr_fman, memac[n-1+8]),\
106}
107#else
108#define FM_TGEC_INFO_INITIALIZER(idx, n) \
109{ \
110 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
111 .index = idx, \
112 .num = n - 1, \
113 .type = FM_ETH_10G_E, \
114 .port = FM##idx##_10GEC##n, \
115 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
116 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
117 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
118 offsetof(struct ccsr_fman, memac[n-1+8]),\
119}
120#endif
121#endif
122
123#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
124#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
125{ \
126 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
127 .index = idx, \
128 .num = n - 1, \
129 .type = FM_ETH_10G_E, \
130 .port = FM##idx##_10GEC##n, \
131 .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
132 .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
133 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
134 offsetof(struct ccsr_fman, memac[n-1-2]),\
135}
136#endif
137
138#else
139#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
140{ \
141 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
142 .index = idx, \
143 .num = n - 1, \
144 .type = FM_ETH_1G_E, \
145 .port = FM##idx##_DTSEC##n, \
146 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
147 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
148 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
149 offsetof(struct ccsr_fman, mac_1g[n-1]),\
150}
151
152#define FM_TGEC_INFO_INITIALIZER(idx, n) \
153{ \
154 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
155 .index = idx, \
156 .num = n - 1, \
157 .type = FM_ETH_10G_E, \
158 .port = FM##idx##_10GEC##n, \
159 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
160 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
161 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
162 offsetof(struct ccsr_fman, mac_10g[n-1]),\
163}
164#endif
165struct fm_eth_info {
166 u8 enabled;
167 u8 fm;
168 u8 num;
169 u8 phy_addr;
170 int index;
171 u16 rx_port_id;
172 u16 tx_port_id;
173 enum fm_port port;
174 enum fm_eth_type type;
175 void *phy_regs;
176 phy_interface_t enet_if;
177 u32 compat_offset;
178 struct mii_dev *bus;
179};
180
181struct tgec_mdio_info {
182 struct tgec_mdio_controller *regs;
183 char *name;
184};
185
186struct memac_mdio_info {
187 struct memac_mdio_controller *regs;
188 char *name;
189};
190
191int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
192int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
193
194int fm_standard_init(bd_t *bis);
195void fman_enet_init(void);
196void fdt_fixup_fman_ethernet(void *fdt);
197phy_interface_t fm_info_get_enet_if(enum fm_port port);
198void fm_info_set_phy_address(enum fm_port port, int address);
199int fm_info_get_phy_address(enum fm_port port);
200void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
201void fm_disable_port(enum fm_port port);
202void fm_enable_port(enum fm_port port);
203void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
204 unsigned int port_num, int phy_base_addr);
205int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
206 unsigned int port_num, unsigned regnum);
207
208#endif
209
