LXR uboot/include/phy.h

   1/*
   2 * Copyright 2011 Freescale Semiconductor, Inc.
   3 *      Andy Fleming <afleming@gmail.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 *
   7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   8 */
   9
  10#ifndef _PHY_H
  11#define _PHY_H
  12
  13#include <linux/list.h>
  14#include <linux/mii.h>
  15#include <linux/ethtool.h>
  16#include <linux/mdio.h>
  17
  18#define PHY_MAX_ADDR 32
  19
  20#define PHY_FLAG_BROKEN_RESET   (1 << 0) /* soft reset not supported */
  21
  22#define PHY_DEFAULT_FEATURES    (SUPPORTED_Autoneg | \
  23                                 SUPPORTED_TP | \
  24                                 SUPPORTED_MII)
  25
  26#define PHY_10BT_FEATURES       (SUPPORTED_10baseT_Half | \
  27                                 SUPPORTED_10baseT_Full)
  28
  29#define PHY_100BT_FEATURES      (SUPPORTED_100baseT_Half | \
  30                                 SUPPORTED_100baseT_Full)
  31
  32#define PHY_1000BT_FEATURES     (SUPPORTED_1000baseT_Half | \
  33                                 SUPPORTED_1000baseT_Full)
  34
  35#define PHY_BASIC_FEATURES      (PHY_10BT_FEATURES | \
  36                                 PHY_100BT_FEATURES | \
  37                                 PHY_DEFAULT_FEATURES)
  38
  39#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  40                                 PHY_1000BT_FEATURES)
  41
  42#define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  43                                SUPPORTED_10000baseT_Full)
  44
  45#ifndef PHY_ANEG_TIMEOUT
  46#define PHY_ANEG_TIMEOUT        4000
  47#endif
  48
  49
  50typedef enum {
  51        PHY_INTERFACE_MODE_MII,
  52        PHY_INTERFACE_MODE_GMII,
  53        PHY_INTERFACE_MODE_SGMII,
  54        PHY_INTERFACE_MODE_SGMII_2500,
  55        PHY_INTERFACE_MODE_QSGMII,
  56        PHY_INTERFACE_MODE_TBI,
  57        PHY_INTERFACE_MODE_RMII,
  58        PHY_INTERFACE_MODE_RGMII,
  59        PHY_INTERFACE_MODE_RGMII_ID,
  60        PHY_INTERFACE_MODE_RGMII_RXID,
  61        PHY_INTERFACE_MODE_RGMII_TXID,
  62        PHY_INTERFACE_MODE_RTBI,
  63        PHY_INTERFACE_MODE_XGMII,
  64        PHY_INTERFACE_MODE_NONE,        /* Must be last */
  65
  66        PHY_INTERFACE_MODE_COUNT,
  67} phy_interface_t;
  68
  69static const char *phy_interface_strings[] = {
  70        [PHY_INTERFACE_MODE_MII]                = "mii",
  71        [PHY_INTERFACE_MODE_GMII]               = "gmii",
  72        [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
  73        [PHY_INTERFACE_MODE_SGMII_2500]         = "sgmii-2500",
  74        [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
  75        [PHY_INTERFACE_MODE_TBI]                = "tbi",
  76        [PHY_INTERFACE_MODE_RMII]               = "rmii",
  77        [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
  78        [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
  79        [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
  80        [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
  81        [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
  82        [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
  83        [PHY_INTERFACE_MODE_NONE]               = "",
  84};
  85
  86static inline const char *phy_string_for_interface(phy_interface_t i)
  87{
  88        /* Default to unknown */
  89        if (i > PHY_INTERFACE_MODE_NONE)
  90                i = PHY_INTERFACE_MODE_NONE;
  91
  92        return phy_interface_strings[i];
  93}
  94
  95
  96struct phy_device;
  97
  98#define MDIO_NAME_LEN 32
  99
 100struct mii_dev {
 101        struct list_head link;
 102        char name[MDIO_NAME_LEN];
 103        void *priv;
 104        int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
 105        int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
 106                        u16 val);
 107        int (*reset)(struct mii_dev *bus);
 108        struct phy_device *phymap[PHY_MAX_ADDR];
 109        u32 phy_mask;
 110};
 111
 112/* struct phy_driver: a structure which defines PHY behavior
 113 *
 114 * uid will contain a number which represents the PHY.  During
 115 * startup, the driver will poll the PHY to find out what its
 116 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 117 * gotten from the PHY will be masked to
 118 * discard any bits which may change based on revision numbers
 119 * unimportant to functionality
 120 *
 121 */
 122struct phy_driver {
 123        char *name;
 124        unsigned int uid;
 125        unsigned int mask;
 126        unsigned int mmds;
 127
 128        u32 features;
 129
 130        /* Called to do any driver startup necessities */
 131        /* Will be called during phy_connect */
 132        int (*probe)(struct phy_device *phydev);
 133
 134        /* Called to configure the PHY, and modify the controller
 135         * based on the results.  Should be called after phy_connect */
 136        int (*config)(struct phy_device *phydev);
 137
 138        /* Called when starting up the controller */
 139        int (*startup)(struct phy_device *phydev);
 140
 141        /* Called when bringing down the controller */
 142        int (*shutdown)(struct phy_device *phydev);
 143
 144        int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 145        int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 146                        u16 val);
 147        struct list_head list;
 148};
 149
 150struct phy_device {
 151        /* Information about the PHY type */
 152        /* And management functions */
 153        struct mii_dev *bus;
 154        struct phy_driver *drv;
 155        void *priv;
 156
 157#ifdef CONFIG_DM_ETH
 158        struct udevice *dev;
 159#else
 160        struct eth_device *dev;
 161#endif
 162
 163        /* forced speed & duplex (no autoneg)
 164         * partner speed & duplex & pause (autoneg)
 165         */
 166        int speed;
 167        int duplex;
 168
 169        /* The most recently read link state */
 170        int link;
 171        int port;
 172        phy_interface_t interface;
 173
 174        u32 advertising;
 175        u32 supported;
 176        u32 mmds;
 177
 178        int autoneg;
 179        int addr;
 180        int pause;
 181        int asym_pause;
 182        u32 phy_id;
 183        u32 flags;
 184};
 185
 186struct fixed_link {
 187        int phy_id;
 188        int duplex;
 189        int link_speed;
 190        int pause;
 191        int asym_pause;
 192};
 193
 194static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 195{
 196        struct mii_dev *bus = phydev->bus;
 197
 198        return bus->read(bus, phydev->addr, devad, regnum);
 199}
 200
 201static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 202                        u16 val)
 203{
 204        struct mii_dev *bus = phydev->bus;
 205
 206        return bus->write(bus, phydev->addr, devad, regnum, val);
 207}
 208
 209#ifdef CONFIG_PHYLIB_10G
 210extern struct phy_driver gen10g_driver;
 211
 212/* For now, XGMII is the only 10G interface */
 213static inline int is_10g_interface(phy_interface_t interface)
 214{
 215        return interface == PHY_INTERFACE_MODE_XGMII;
 216}
 217
 218#endif
 219
 220int phy_init(void);
 221int phy_reset(struct phy_device *phydev);
 222struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 223                phy_interface_t interface);
 224#ifdef CONFIG_DM_ETH
 225void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 226struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 227                                struct udevice *dev,
 228                                phy_interface_t interface);
 229#else
 230void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 231struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 232                                struct eth_device *dev,
 233                                phy_interface_t interface);
 234#endif
 235int phy_startup(struct phy_device *phydev);
 236int phy_config(struct phy_device *phydev);
 237int phy_shutdown(struct phy_device *phydev);
 238int phy_register(struct phy_driver *drv);
 239int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 240int genphy_config_aneg(struct phy_device *phydev);
 241int genphy_restart_aneg(struct phy_device *phydev);
 242int genphy_update_link(struct phy_device *phydev);
 243int genphy_parse_link(struct phy_device *phydev);
 244int genphy_config(struct phy_device *phydev);
 245int genphy_startup(struct phy_device *phydev);
 246int genphy_shutdown(struct phy_device *phydev);
 247int gen10g_config(struct phy_device *phydev);
 248int gen10g_startup(struct phy_device *phydev);
 249int gen10g_shutdown(struct phy_device *phydev);
 250int gen10g_discover_mmds(struct phy_device *phydev);
 251
 252int phy_mv88e61xx_init(void);
 253int phy_aquantia_init(void);
 254int phy_atheros_init(void);
 255int phy_broadcom_init(void);
 256int phy_cortina_init(void);
 257int phy_davicom_init(void);
 258int phy_et1011c_init(void);
 259int phy_lxt_init(void);
 260int phy_marvell_init(void);
 261int phy_micrel_init(void);
 262int phy_natsemi_init(void);
 263int phy_realtek_init(void);
 264int phy_smsc_init(void);
 265int phy_teranetics_init(void);
 266int phy_ti_init(void);
 267int phy_vitesse_init(void);
 268int phy_xilinx_init(void);
 269
 270int board_phy_config(struct phy_device *phydev);
 271int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
 272
 273/**
 274 * phy_get_interface_by_name() - Look up a PHY interface name
 275 *
 276 * @str:        PHY interface name, e.g. "mii"
 277 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 278 */
 279int phy_get_interface_by_name(const char *str);
 280
 281/**
 282 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 283 * is RGMII (all variants)
 284 * @phydev: the phy_device struct
 285 */
 286static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 287{
 288        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 289                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 290}
 291
 292/**
 293 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 294 * is SGMII (all variants)
 295 * @phydev: the phy_device struct
 296 */
 297static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 298{
 299        return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
 300                phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 301}
 302
 303/* PHY UIDs for various PHYs that are referenced in external code */
 304#define PHY_UID_CS4340  0x13e51002
 305#define PHY_UID_TN2020  0x00a19410
 306
 307#endif
 308